JPH06196504A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To provide a semiconductor device of high reliability which can be easily manufactured without using fluorocarbon gas, and its manufacturing method. CONSTITUTION:An InGaP layer 2 is interposed between an N<+> type AlGaAs layer 10 and an N'' type GaAs layer 12 of a usual HEMT. In the case of etching using sulfuric acid and hydrogen peroxide or the like for forming a recessed part 14, the etching rate of the InGaP layer 2 is extremely smaller than that of the N<+> type GaAs layer 12. Hence when the N<+> type GaAs layer 12 is etched, the progress of etching can be interrupted in the vicinity of the junction surface of the layer 12 and the InGaP layer 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a technique capable of easily and accurately manufacturing a semiconductor device such as a so-called HEMT without using a CFC gas.

[0002]

2. Description of the Related Art In recent years, semiconductor devices have been required to operate at high speed, and so have the so-called HEMT (High E
lectron Mobility Transistor) has been proposed. The structure of this HEMT is shown in FIG. 4A. HE as shown
A semi-insulating gallium histograph (GaAs) substrate 4 is used for MT. Since GaAs has a higher electron mobility than silicon (Si), it is possible to realize a high-speed semiconductor device.

On the GaAs substrate 4, undoped GaAs is sequentially formed.
Layer 6, undoped aluminum gallium histograph (AlGaA
s) layer 8, N ⁺ type aluminum gallium histograph (AlGaAs) layer 10, heavily doped N ⁺ type gallium histograph (GaAs) layer 1
Two are stacked.

A recess 14 is formed in the N ⁺ type GaAs layer 12, and a gate electrode 30 is provided on the recess bottom surface 14M of the recess 14. The Schottky barrier phenomenon occurs due to the provision of the gate electrode 30. A source electrode 32 and a drain electrode 34 are provided on the surface of the N ⁺ type GaAs layer 12 with the recess 14 in between. The N ⁺ type GaAs layer 12 is the source electrode 3
2, a layer formed to reduce the ohmic resistance of the drain electrode 34, and is highly doped.

Since the N ⁺ type AlGaAs layer 10 has a weaker electron affinity than the undoped type GaAs layer 6, the N ⁺ type AlGaA layer 10 has a weaker electron affinity.
The electrons generated in the s layer 10 are supplied to the undoped GaAs layer 6. Then, the electrons supplied to the undoped type GaAs layer 6 are accumulated on the heterojunction surface, and the two-dimensional electron gas layer 6W is formed there. This two-dimensional electron gas layer 6
W serves as a current flowing between the source electrode 32 and the drain electrode 34, is controlled by being applied to the gate electrode 30, and functions as a transistor.

Next, a method of manufacturing the HEMT shown in FIG. 4A will be described. The above layers stacked on the GaAs substrate 4 are sequentially formed by the epitaxial growth method. Then, in order to isolate and insulate each element region, an isolation region 50H shown in FIG. 4A is formed. The isolation region 50H is formed by adding ions. The isolation region 50H is removed by etching to separate each element region,
Some are insulated.

After element isolation, a source electrode 32 and a drain electrode 34 are provided on the surface of the N ⁺ type GaAs layer 12 by a resist pattern. Then, these source electrodes 32,
The recessed recess 14 and the gate electrode 30 are formed at approximately the middle position of the drain electrode 34. A method of forming the recessed portion 14 and the gate electrode 30 will be described below.

First, as shown in FIG. 4B, a resist 20 is formed on the N ⁺ type GaAs layer 12, and a resist opening 20K is positioned at a corresponding position of the gate electrode 30 for patterning. Then, a CFC gas is supplied through the resist opening 20K to perform dry etching. When dry etching is performed using CFC gas, N ⁺ type GaAs
The etching rate of the layer 12 is extremely slow as compared with the etching rate of the N ⁺ -type AlGaAs layer 10. Therefore, the etching almost stops near the junction surface between the N ⁺ type GaAs layer 12 and the N ⁺ type AlGaAs layer 10, and the ideal depth of the recess recess 14 can be obtained.

Although the etching depth stops, N
The lateral expansion in the ⁺ type GaAs layer 12 proceeds at a constant speed. Therefore, by adjusting the etching time, it is possible to accurately control the width F of the recess 14 while ensuring an ideal depth.

Another method for forming the recess 14 is shown in FIG. 5A. In this method, the recess recess 14 is formed by performing wet etching using an etching chemical such as sulfuric acid and hydrogen peroxide, phosphoric acid and hydrogen peroxide, citric acid and hydrogen peroxide, etc. without using CFC gas. However, when these etching chemicals are used, the etching rates of the N ⁺ type GaAs layer 12 and the N ⁺ type AlGaAs layer 10 are almost the same.

Therefore, in order to control the etching depth, the source electrode 32 and the drain electrode 34 are connected to the measuring device 2.
Connect to No. 4 and proceed with the etching process while monitoring the change in current. FIG. 5B shows the relationship of the change in the current ID of the drain electrode 34 with respect to the voltage VDS between the source electrode 32 and the drain electrode 34. The etching depth has increased,
The current ID becomes smaller as the recess 14 becomes deeper.

For example, assuming that the current ID of the recess 14 having a desired depth is the line L1, the line continuously changes from L9 to L8 and L7 as the etching progresses, and when the line reaches L1. Stop the etching process. As a result, the recess recess 14 having a desired depth is formed.

After the recess 14 is formed as described above, the resist 20 is used as a mask to form the resist opening 20.
A gate electrode 30 is provided through K. Then, the resist 20 is removed to obtain a HEMT as shown in FIG. 4A.

[0014]

The above-mentioned conventional semiconductor device and the manufacturing method thereof have the following problems. Regarding the formation of the recessed portion 14, first, in the method shown in FIG. 4B, etching using CFC gas is performed. However, in recent years, environmental problems such as ozone layer depletion due to CFCs have been pointed out, and the use of CFCs is severely restricted. Therefore, it is practically impossible to use CFC gas.

On the other hand, in the method shown in FIG. 5A, the recess 14 can be formed by using sulfuric acid and hydrogen peroxide, phosphoric acid and hydrogen peroxide, citric acid and hydrogen peroxide, etc. without using CFC gas. Therefore, the above environmental problems do not occur. However, this method has the following new problems.

In order to obtain the recess 14 having a desired size, it is necessary to stop the etching at an appropriate position. However, in the etching using sulfuric acid and hydrogen peroxide or the like, there is no great difference in etching rate between the N ⁺ type GaAs layer 12 and the N ⁺ type AlGaAs layer 10, unlike the case of using freon gas. Therefore, the etching depth is N ⁺ type GaAs.
It does not stop near the junction surface between the layer 12 and the N ⁺ -type AlGaAs layer 10, and even within the N ⁺ -type AlGaAs layer 10, the N ⁺ -type GaAs layer 12
Etching progresses at almost the same speed.

Therefore, as described above, the measuring device 24 is used to measure the voltage between the source electrode 32 and the drain electrode 34, and the etching process is performed while monitoring the voltage. However, in this method, the wiring of the measuring device 24 is required first, and the source electrode 32 and the drain electrode 3 are also required.
The etching process must be advanced in small steps while observing the voltage change between the four. As described above, there is a problem that the etching work is troublesome and the work efficiency is reduced.

Further, the method shown in FIG. 5A has a problem that the width F of the recess 14 cannot be controlled accurately and the reliability of the semiconductor device is deteriorated. That is, unlike the case where the CFC gas is used, the etching in this case does not stop in the vicinity of the bonding surface between the N ⁺ type GaAs layer 12 and the N ⁺ type AlGaAs layer 10 and is in the N ⁺ type AlGaAs layer 10. However, it also advances in the depth direction at the same speed as in the width direction. Therefore, it is impossible to accurately control the width F of the recess 14 while ensuring an ideal depth.

The width F of the recess 14 is controlled to secure the breakdown voltage of the gate electrode 30 and to reduce the resistance between the source electrode 32 and the drain electrode 34. If the width F of the recess 14 is too narrow, the gate electrode 30 and the heavily doped N ⁺ -type GaAs layer 12 are located close to each other, and the breakdown voltage of the gate electrode 30 cannot be secured. On the contrary, if the width F of the recess 14 is too wide,
The distance between the source electrode 32 and the drain electrode 34 becomes long and the resistance becomes high. Therefore, the recess recess 1
Accurate control of the width F of 4 is required.

As described above, various problems occur regardless of the manufacturing method shown in FIGS. 4B and 5A. Therefore, an object of the present invention is to provide a semiconductor device which can be manufactured without using CFC gas, is easy to manufacture and has high reliability, and a manufacturing method thereof.

[0021]

A semiconductor device according to a first aspect of the present invention includes an undoped semiconductor layer formed on a semi-insulating semiconductor substrate, and an undoped semiconductor layer formed on the undoped semiconductor layer. A doped semiconductor layer having an electron affinity smaller than that of the layer, an intervening semiconductor layer formed on the doped semiconductor layer, and a cap semiconductor layer formed on the intervening semiconductor layer, the etching chemical substance being different from CFC gas. In the etching using, a cap semiconductor layer having an etching speed extremely higher than that of the intervening semiconductor layer, a source electrode formed on the surface of the cap semiconductor layer, a drain electrode formed on the surface of the cap semiconductor layer, and a cap semiconductor layer formed The recessed portion of the cap semiconductor layer is formed at a substantially intermediate position between the source electrode and the drain electrode. It is characterized by comprising intermediate semiconductor layer and the cap semiconductor layer recess formed so as to reach the vicinity of the boundary surface between the cap semiconductor layer, capping semiconductor layer concave recess bottom surface formed gate electrode, the.

A method of manufacturing a semiconductor device according to claim 2 is
Forming an undoped semiconductor layer on the semi-insulating semiconductor substrate; forming a doped semiconductor layer having an electron affinity lower than that of the undoped semiconductor layer on the undoped semiconductor layer; The step of forming an intervening semiconductor layer in the step of forming an intervening semiconductor layer and the step of forming a cap semiconductor layer on the intervening semiconductor layer. Forming a cap semiconductor layer, a source electrode formed on the surface of the cap semiconductor layer, a drain electrode formed on the surface of the cap semiconductor layer, an etching chemical different from CFC gas is used for the cap semiconductor layer. By etching the cap semiconductor layer Forming a cap semiconductor layer recess so as to reach near the boundary surface between the intervening semiconductor layer and the cap semiconductor layer, the cap semiconductor layer recess being formed substantially at an intermediate position between the source electrode and the drain electrode. And a step of forming a gate electrode on the bottom surface of the recess.

A semiconductor device according to a third aspect of the present invention includes an undoped type gallium histograph (GaAs) layer formed on a semi-insulating gallium histograph (GaAs) substrate and an upper part of the undoped type gallium histograph (GaAs) layer. A doped aluminum gallium histograph (AlGaAs) layer having an electron affinity smaller than that of the undoped gallium histograph (GaAs) layer, and indium gallium phosphide (InGaP) formed on the doped aluminum gallium histograph (AlGaAs) layer.
Layer, a heavily-doped gallium histo- (GaAs) layer formed on the indium gallium phosphide (InGaP) layer, a source electrode formed on the surface of the heavily-doped gallium-histo (GaAs) layer, and the heavily-doped The drain electrode formed on the surface of the gallium histo (GaAs) layer, and the layer recess formed in the heavily doped gallium histo (GaAs) layer, which is formed at a substantially intermediate position between the source electrode and the drain electrode, Characterized by comprising a layer recess formed so as to reach near the interface between the gallium phosphide (InGaP) layer and the highly doped gallium histograph (GaAs) layer, and a gate electrode formed on the bottom of the recess of the layer recess. There is.

A method of manufacturing a semiconductor device according to claim 4 is
Forming an undoped gallium histograph (GaAs) layer on a semi-insulating gallium histograph (GaAs) substrate, and doping the upper part of the undoped gallium histograph (GaAs) layer with an electron affinity lower than that of the undoped gallium histograph (GaAs) layer. A step of forming an indium gallium arsenide (AlGaAs) layer, indium gallium phosphide (In) is formed on the doped aluminum gallium arsenide (AlGaAs) layer.
Forming a GaP) layer, forming a heavily doped gallium histo (GaAs) layer on the indium gallium phosphide (InGaP) layer, and forming a source electrode on the surface of the heavily doped gallium histo (GaAs) layer The step of forming a drain electrode on the surface of the heavily-doped gallium histio (GaAs) layer, and the step of forming a layer recess in the heavily-doped gallium histo-GaAs (GaAs) layer. Is formed almost in the middle position of the indium gallium phosphide (InGaP)
And a step of forming a layer recess so as to reach the vicinity of a boundary surface between the layer and the heavily doped gallium histo (GaAs) layer, and a step of forming a gate electrode on the bottom surface of the recess of the layer recess.

[0025]

According to the semiconductor device of the first aspect and the method of manufacturing the semiconductor device of the second aspect, the intervening semiconductor layer is formed on the doped semiconductor layer, and the cap semiconductor layer is further provided on the intervening semiconductor layer. It is formed. Then, the cap semiconductor layer has an extremely high etching rate as compared with the intervening semiconductor layer in the etching using the etching chemical substance different from the CFC gas. Further, a cap semiconductor layer recess is formed in the cap semiconductor layer, and the cap semiconductor layer recess is formed so as to reach near the boundary surface between the intervening semiconductor layer and the cap semiconductor layer.

As described above, the cap semiconductor layer has an extremely high etching rate as compared with the intervening semiconductor layer. Therefore, the cap semiconductor layer can be etched using an etching chemical different from the CFC gas to easily stop the recess of the cap semiconductor layer in the vicinity of the interface between the intervening semiconductor layer and the cap semiconductor layer. Further, since the etching proceeds at a high speed in the cap semiconductor layer even after the etching is stopped near the boundary surface, it is possible to easily control the spread of the cap semiconductor layer recess in the cap semiconductor layer.

In the semiconductor device according to claim 3 and the method for manufacturing a semiconductor device according to claim 4, an indium gallium phosphide (InGaP) layer is formed on a doped aluminum gallium histograph (AlGaAs) layer. A heavily doped gallium histo (GaAs) layer is formed on the indium gallium phosphide (InGaP) layer. Then, a layer recess is formed in the heavily doped gallium histo (GaAs) layer, and the layer recess is formed so as to reach the vicinity of the interface between the indium gallium phosphide (InGaP) layer and the heavily doped gallium histo (GaAs) layer. It

Here, when the heavily doped gallium histograph (GaAs) layer is wet-etched by using, for example, sulfuric acid and hydrogen peroxide, phosphoric acid and hydrogen peroxide, citric acid and hydrogen peroxide, etc. The etching rate of the (GaAs) layer is extremely higher than that of the indium gallium phosphide (InGaP) layer.

Therefore, the heavily doped gallium histograph (GaAs) layer is etched by using an etching chemical substance different from the CFC gas, and the indium gallium phosphide (InGaP) layer and the heavily doped gallium histograph (GaA) are added.
s) The layer recess can be easily stopped near the interface with the layer. Even after the etching is stopped near the boundary surface, the etching proceeds at high speed in the heavily-doped gallium histograph (GaAs) layer, so that the heavily-doped gallium histograph (Ga)
It is possible to easily control the spread of the layer recess in the As) layer.

Indium gallium phosphide (InGaP)
Since the layer is formed, the doped aluminum gallium histograph (AlGaAs) layer is not exposed to the outside. Therefore, it is possible to prevent the doped aluminum gallium histograph (AlGaAs) layer from being oxidized.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor device and a method of manufacturing the same according to the present invention will be described with reference to the drawings. In this embodiment, a so-called HEMT (High Electron) is used as a semiconductor device.
Mobility Transistor) is taken as an example. First, FIG. 1 schematically shows the structure of this HEMT.

On the gallium histograph (GaAs) substrate 4 as the semi-insulating semiconductor substrate, an undoped type gallium histograph (GaAs) layer 6, an undoped type aluminum gallium histograph (AlGaAs) layer 8 and a doped type semiconductor are sequentially formed. Layer N ⁺ type aluminum gallium histograph (AlGaA
s) layer 10, an indium gallium phosphide (InGaP) layer 2 that is an intervening semiconductor layer, and a highly-doped N ⁺ -type gallium histograph (GaAs) layer 12 that is a cap semiconductor layer are stacked.

The source electrode 3 is formed on the surface of the N ⁺ type GaAs layer 12.
2. A drain electrode 34 is provided. Also, N ⁺ type G
In the aAs layer 12, a recess recess 14 which is a cap semiconductor layer recess is formed substantially at an intermediate position between the source electrode 32 and the drain electrode 34, and the recess recess 14 is N ^+.
It reaches near the boundary surface between the type GaAs layer 12 and the InGaP layer 2. Further, the gate electrode 30 is provided on the recess bottom surface 14M of the recess recess 14. Highly doped N
^{The +} type GaAs layer 12 has a source electrode 32 and a drain electrode 34.
Is a layer formed to relax the ohmic resistance of.

Since the N ⁺ type AlGaAs layer 10 has a smaller electron affinity than the undoped type GaAs layer 6, the N ⁺ type AlG layer 10 has a smaller electron affinity.
The electrons generated in the aAs layer 10 are supplied to the undoped type GaAs layer 6. Then, the electrons supplied to the undoped type GaAs layer 6 are accumulated on the heterojunction surface, and the two-dimensional electron gas layer 6W is formed there. The two-dimensional electron gas layer 6W becomes a current flowing between the source electrode 32 and the drain electrode 34 and is controlled by application to the gate electrode 30,
Functions as a transistor.

Next, based on FIG. 2 and FIG.
An example of a method of manufacturing T will be described. First, each layer is epitaxially grown on the GaAs substrate 4 through the following processing steps (FIG. 2). The undoped GaAs layer 6 on the GaAs substrate 4 is formed by introducing source gases AsH ₃ and (C ₂ H ₅ ) ₃ Ga by MOCVD (Metal Organic Chemical Vapor Deposition) and reacting for about 10 minutes. As a result, the undoped GaAs layer 6 having a thickness of 2000 to 6000 Å can be obtained. Then, an undoped AlGaAs layer 8 is formed on the undoped GaAs layer 6. Also in this case, the source gases AsH ₃ , (C ₂ H ₅ ) ₃ Ga, and (CH ₃ ) ₃ Al are introduced using the MOCVD method,
Incubate for about 6 seconds. As a result, the Al composition ratio is 15 to 35
%, Undoped Al with a thickness of 10-40 Å
The GaAs layer 8 can be formed.

After the undoped AlGaAs layer 8 is formed, the N ⁺ type AlGaAs layer 10 is grown on the undoped AlGaAs layer 8. That is,
Using MOCVD method, source gas AsH ₃ , (C ₂ H ₅ ) ₃ Ga, (CH ₃ )
₃ Al is introduced, and SiH ₄ is further introduced as an impurity source and reacted for about 1 minute to grow epitaxially. As a result, the Al composition ratio is 15 to 35%, the Si concentration is 1 to 3 × 10 ¹⁸ cm
^- 3, having a thickness of 200 to 400 Å N ⁺ -type AlGaA
The s layer 10 can be formed.

Next, the InGaP layer 2 is formed on the N ⁺ type AlGaAs layer 10.
To form. By the MOCVD method, the raw material gas PH ₃ , (C ₂
H ₅ ) ₃ Ga and (CH ₃ ) ₃ In were introduced, and SiH ₄ was added as an impurity source.
Is introduced and reacted for about 15 seconds. In composition ratio 4
0-60%, Si concentration 1-3 × 10 ¹⁸ cm ^-3 , thickness 50-1
An InGaP layer 2 of 50 Å can be epitaxially grown. Since the InGaP layer 2 is formed extremely thin in this way, the influence caused by the InGaP layer 2 can be suppressed to a small level and the proper operation of the transistor is not hindered.

Then, an N ⁺ type GaAs layer 12 is formed on the InGaP layer 2.
Grow. Also in this case, the source gas AsH ₃ and (C ₂ H ₅ ) ₃ Ga are introduced by the MOCVD method, and SiH is used as an impurity source.
Introduce ₄ and react for about 2 minutes. As a result, the Si concentration is 4 to 8 × 10 ¹⁸ cm ⁻³ and the high concentration is 500 to 1000.
The Angstrom N ⁺ -type GaAs layer 12 can be formed.

As described above, as shown in FIG.
Each layer is formed on the As substrate 4. After that, in order to isolate and insulate each element region, an isolation region 50H shown in the figure is formed. The isolation region 50H is formed by adding ions. The isolation region 50H may be removed by etching to isolate and insulate each element region. After element isolation, a source electrode 32 and a drain electrode 34 are provided on the surface of the N ⁺ type GaAs layer 12 (see FIG. 2). In this case, first, a resist film is formed on a portion other than the electrode formation portion, and the electrode portion is patterned (not shown). After depositing AuGe and Ni on the entire surface, AuGe,
The resist film on which Ni is deposited is removed. Due to the removal of the resist film, AuGe and Ni remain only at the patterning portion, and further heated at about 430 ° C. for about 5 minutes in the N ₂ atmosphere to form the source electrode 32 and the drain electrode 34.

Next, the source electrode 32 and the drain electrode 34
Recess recesses 14 (see FIG. 1) are formed by recess etching at positions approximately in the middle of. This recess etching is performed as follows. First, as shown in FIG. 3, a resist film 20 is applied on the entire surface and a part of the resist film 20 is removed to form a resist opening 20K. Then, an etching process is performed using a mixed solution of sulfuric acid and hydrogen peroxide as an etching chemical substance.

Here, the etching rate of the N ⁺ type GaAs layer 12 when a mixed solution of sulfuric acid and hydrogen peroxide is used is about 1000 angstroms per minute. On the other hand, the InGaP layer 2 has a thickness of about 10 to 70 angstroms per minute. As described above, when a mixed solution of sulfuric acid and hydrogen peroxide is used, the etching rate of the N ⁺ type GaAs layer 12 is 10 to 100 times as fast as the etching rate of the InGaP layer 2.

Therefore, the recess etching is performed by N ⁺ type G
It almost stops near the bonding surface between the aAs layer 12 and the InGaP layer 2, and the ideal depth of the recess 14 can be obtained. Although the depth of the recess etching is stopped, the lateral expansion in the N ⁺ type GaAs layer 12 proceeds at a constant speed. Therefore, the width F of the recess 14 can be controlled by adjusting the etching time.

In this way, recess etching is performed without using CFC gas, and while maintaining an ideal depth,
The width F of the recess 14 can be accurately controlled.
The withstand voltage of the gate electrode 30 is ensured by controlling the width F of the recessed portion 14. In addition, since the recess recess 14 can be formed by wet etching, the facility cost can be reduced as compared with dry etching using CFC gas. Instead of the mixed solution of sulfuric acid and hydrogen peroxide, chemical substances for etching such as phosphoric acid and hydrogen peroxide or citric acid and hydrogen peroxide may be used.

After forming the recess 14 in this manner, a gate electrode is provided on the bottom surface 14M of the recess. To form this gate electrode, the resist film 20 and the resist opening 20K during recess etching are used. That is, using the resist film 20 shown in FIG.
Å, Pt is deposited to a thickness of about 500 Å, and Au is deposited to a thickness of about 4500 Å.

After that, Ti, Pt and Au are removed by the lift-off method.
The resist film 20 on which is deposited is removed. By removing the resist film 20, the T of the resist opening 20K is removed.
i, Pt, Au remain, and as shown in FIG.
The gate electrode 30 is formed on the. When forming the gate electrode, Ti may be deposited to a thickness of about 100 Å and AI may be deposited to a thickness of about 6000 Å.
Is about 100 angstrom, Al is about 6000
It may be angstrom deposited.

Through the above steps, H shown in FIG.
EMT can be obtained. The N ⁺ type AlGaAs layer 10
By interposing the InGaP layer 2 between the N ⁺ -type GaAs layer 12 and the N ⁺ -type GaAs layer 12, it is possible to prevent the N ⁺ -type AlGaAs layer 10 from being exposed from the recess bottom surface 14M. As a result, the N ⁺ type AlGaAs layer 10
Can be prevented. In addition, the gate electrode 30
After forming, a protective film may be formed over the entire surface to more reliably prevent oxidation. In the HEMT shown in FIG. 1, the undoped GaAs layer 6 and the undoped AlGaAs layer 8 are
Further, undoped InGaAs can be positioned between and. Also, without providing the undoped AlGaAs layer 8, H
You may comprise EMT. Further, the intervening semiconductor layer is not limited to the InGaP layer 2, but when the etching chemical substance other than CFC gas is used for etching, the etching rate thereof is much slower than the etching rate of the cap semiconductor layer. However, other substances may be used. Further, although the above-described embodiment has been described by taking the HEMT as shown in FIG. 1 as an example, the present invention is not limited to this and can be applied to other semiconductor devices.

[0047]

According to the semiconductor device of the first aspect and the method of manufacturing the semiconductor device of the second aspect, the intervening semiconductor layer is formed on the doped semiconductor layer, and the cap semiconductor is further provided on the intervening semiconductor layer. A layer is formed. Then, the cap semiconductor layer has an extremely high etching rate as compared with the intervening semiconductor layer in the etching using the etching chemical substance different from the CFC gas. Further, a cap semiconductor layer recess is formed in the cap semiconductor layer, and the cap semiconductor layer recess is formed so as to reach near the boundary surface between the intervening semiconductor layer and the cap semiconductor layer.

As described above, the cap semiconductor layer has an extremely high etching rate as compared with the intervening semiconductor layer. That is, the cap semiconductor layer can be etched using a chemical substance for etching different from the CFC gas to easily stop the recess of the cap semiconductor layer in the vicinity of the interface between the intervening semiconductor layer and the cap semiconductor layer. Therefore, it is possible to obtain a semiconductor device that can be manufactured without using CFC gas.

Further, since the etching proceeds at a high speed in the cap semiconductor layer even after the etching is stopped near the boundary surface, it is possible to easily control the spread of the cap semiconductor layer recess in the cap semiconductor layer. Therefore,
The recess of the cap semiconductor layer can be formed easily and accurately, and a highly reliable semiconductor device can be obtained.

In the semiconductor device according to claim 3 and the method for manufacturing a semiconductor device according to claim 4, an indium gallium phosphide (InGaP) layer is formed on an upper portion of a doped aluminum gallium histograph (AlGaAs) layer, and A heavily doped gallium histo (GaAs) layer is formed on the indium gallium phosphide (InGaP) layer. Then, a layer recess is formed in the heavily doped gallium histo (GaAs) layer, and the layer recess is formed so as to reach the vicinity of the interface between the indium gallium phosphide (InGaP) layer and the heavily doped gallium histo (GaAs) layer. It

Here, when the heavily doped gallium histograph (GaAs) layer is wet-etched by using, for example, sulfuric acid and hydrogen peroxide, phosphoric acid and hydrogen peroxide, citric acid and hydrogen peroxide, etc. The etching rate of the (GaAs) layer is extremely higher than that of the indium gallium phosphide (InGaP) layer.

That is, the heavily-doped gallium histograph (GaAs) layer is etched by using an etching chemical different from the CFC gas, and the indium gallium phosphide (InGaP) layer and the heavily-doped gallium histograph (GaA) are added.
s) The layer recess can be easily stopped near the interface with the layer. Therefore, it is possible to obtain a semiconductor device that can be manufactured without using CFC gas.

Further, since the etching progresses at a high speed in the heavily doped gallium histo (GaAs) layer even after the etching is stopped in the vicinity of the boundary surface, the layer concave portion spreads in the heavily doped gallium histo (GaAs) layer. Can be controlled easily. Therefore, the layer recess can be formed easily and accurately, and a highly reliable semiconductor device can be obtained.

Further, indium gallium phosphide (InGa
Since the P) layer is formed, the doped aluminum gallium histograph (AlGaAs) layer is not exposed to the outside. Therefore, the doped aluminum gallium histograph (AlGaA
s) It is possible to prevent the layer from being oxidized. Therefore, a more reliable semiconductor device can be obtained.

[0055]

[Brief description of drawings]

FIG. 1 shows H in an embodiment of a semiconductor device according to the present invention.
It is a figure which shows the structure of EMT.

FIG. 2 is a diagram showing a step in the method of manufacturing the HEMT shown in FIG.

FIG. 3 is a diagram showing a step of the method of manufacturing the HEMT shown in FIG. 1.

FIG. 4 is a diagram showing a structure of a conventional HEMT and one step of a manufacturing method thereof.

FIG. 5 is a diagram showing a step of another method of manufacturing the conventional HEMT.

[Explanation of symbols]

2 ... Indium gallium phosphide (InGaP) layer 4 ... Gallium histograph (GaAs) substrate 6 ... Undoped type gallium histograph (GaAs) layer 8 ... Undoped type aluminum gallium histograph (AlGaAs) ) Layer 10 ... N ⁺ type aluminum gallium histograph (AlGaA
s) layer 12: heavily doped N ⁺ type gallium histograph (GaA)
s) layer 14 ... recessed recess 30 ... gate electrode 32 ... source electrode 34 ... drain electrode

Claims (4)

[Claims] 1. An undoped semiconductor layer formed on a semi-insulating semiconductor substrate, a doped semiconductor layer formed on an undoped semiconductor layer and having an electron affinity lower than that of the undoped semiconductor layer, and a doped semiconductor layer. The intervening semiconductor layer formed on top of the semiconductor layer and the cap semiconductor layer formed on top of the intervening semiconductor layer are much faster than the intervening semiconductor layer when etching with an etching chemical different from CFC gas. A cap semiconductor layer having an etching rate, a source electrode formed on the surface of the cap semiconductor layer, a drain electrode formed on the surface of the cap semiconductor layer, and a cap semiconductor layer concave portion formed on the cap semiconductor layer, which is a source electrode. It is formed almost in the middle of the drain electrode, and the boundary between the intervening semiconductor layer and the cap semiconductor layer The semiconductor device characterized by comprising capping semiconductor layer recess formed so as to reach the surface vicinity, capping semiconductor layer concave recess bottom surface formed gate electrode, the. 2. A step of forming an undoped semiconductor layer on the semi-insulating semiconductor substrate, a step of forming a doped semiconductor layer having an electron affinity lower than that of the undoped semiconductor layer on the undoped semiconductor layer, doping The step of forming the intervening semiconductor layer on the upper part of the interstitial semiconductor layer, the step of forming the cap semiconductor layer on the upper part of the intervening semiconductor layer. Step of forming a cap semiconductor layer having an extremely fast etching rate, step of forming a source electrode on the surface of the cap semiconductor layer, step of forming a drain electrode on the surface of the cap semiconductor layer, etching of the cap semiconductor layer different from CFC gas By etching with chemicals A step of forming a recessed portion of the cap semiconductor layer, the step of forming the recessed portion of the cap semiconductor layer so that the recessed portion is formed substantially at an intermediate position between the source electrode and the drain electrode and reaches near the boundary surface between the intervening semiconductor layer and the cap semiconductor layer. And a step of forming a gate electrode on the bottom surface of the concave portion of the cap semiconductor layer concave portion, the method for manufacturing a semiconductor device. 3. An undoped gallium histograph (GaAs) layer formed on a semi-insulating gallium histograph (GaAs) substrate, and an undoped gallium histograph (GaAs) layer formed on the undoped gallium histograph (GaAs) layer. ) Layer has a smaller electron affinity than the doped aluminum gallium histograph (AlGaAs) layer, and indium gallium phosphide (InGa) formed on the doped aluminum gallium histograph (AlGaAs) layer.
P) layer, a highly-doped gallium histo- (GaAs) layer formed on the indium gallium phosphide (InGaP) layer, a source electrode formed on the surface of the heavily-doped gallium-histo (GaAs) layer, the high concentration A drain electrode formed on the surface of the doped gallium histograph (GaAs) layer; a layer recess formed in the highly-doped gallium histograph (GaAs) layer, which is formed substantially at an intermediate position between the source electrode and the drain electrode, The indium gallium phosphide (In
A semiconductor device comprising: a layer recess formed so as to reach the vicinity of a boundary surface between the GaP) layer and the heavily doped gallium histograph (GaAs) layer; and a gate electrode formed on a bottom surface of the recess of the layer recess. . 4. A step of forming an undoped gallium histograph (GaAs) layer on a semi-insulating gallium histograph (GaAs) substrate, wherein the undoped gallium histograph (GaAs) layer is formed on the upper part of the undoped gallium histograph (GaAs) layer. Doped aluminum gallium histograph (AlGaAs) with low electron affinity
Forming a layer, forming an indium gallium phosphide (InGaP) layer on the doped aluminum gallium phosphide (AlGaAs) layer, and heavily doping gallium phosphide (GaAs) on the indium gallium phosphide (InGaP) layer. Forming a layer, forming a source electrode on the surface of the heavily doped gallium histo (GaAs) layer, forming a drain electrode on the surface of the heavily doped gallium histo (GaAs) layer, the heavily doped In the step of forming a layer recess in the gallium histio (GaAs) layer, the indium gallium phosphide (InGaP) layer and the heavily doped gallium histio (GaA
s) A step of forming a layer recess so as to reach the vicinity of a boundary surface with the layer, and a step of forming a gate electrode on the bottom surface of the layer recess.