JPS633415A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the scattering of Ga and As while an alloy treatment process is being performed by a method wherein, before the performance of the alloy treatment process, the entire side face of the conductive layer containing the metal to be formed into an ohmic electrode is coated by the silicon nitride film containing hydrogen. CONSTITUTION:A mesa M has been formed by removing an N-type GaAs layer 4 and a buffer layer 3 from a GaAs semiconductor surface 1, a photoresist 5 is removed, and the Au-Ge/Ni 6 to be turned into a source and drain is formed. Then, after a silicon nitride film 7 containing hydrogen has been formed on the entire side face of the layer 4, the Au-Ge/Ni 6 and the layer 4 are ohmic- contacted. Subsequently, an aperture part 8 is provided on the film 7 using the photoresist 8, and after a recess 4a has been formed on the layer 4, an Al gate 10 is formed on the recess 4a. A window is formed at the point corresponding to the ohmic electrode of the film 7, a wiring metal consisting of Ti and Au is Vapor-deposited, and a wiring and a pad 13 are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a method for manufacturing a compound semiconductor device, and more particularly to a method for forming a good ohmic electrode on a compound semiconductor.

<Prior art and its problems> In general, in compound semiconductor devices used in the high frequency region, especially GaAs MESFETs, the noise Fl number (NF)
In order to improve high frequency characteristics such as power gain (G a ),
Improved mutual conductance (gm) and gate-source spacing! ) (Cgs), source-to-gate series resistance (Rs), and other parasitic parameters.

In particular, reducing Rs is an important issue, and shortening the distance between the source and gate and forming a high concentration n'' layer are effective in reducing the contact resistance of the ohmic electrode.

On the other hand, in order to improve gm and reduce Cgs, it is necessary to shorten the gate length C1g), and therefore -
Generally, microfabrication on the submicron order is essential for GaAs MESFETs and the like. Normally, photolithography is often used to form gates on the submicron order, but the yield is good (in order to form a resist pattern, in addition to improving lithography technology, it is necessary to smooth the wafer surface and process the wafer. It is necessary to reduce warpage.Especially in the case of contact exposure, the gap between the wafer and photomask is closely related to processing accuracy and yield, so it is important to smooth the wafer surface and eliminate warpage as much as possible. This has become a major issue.

By the way, in compound semiconductors mainly made of GaAs, 5
It is thermally unstable at a temperature of about 00°C, and
Since vapor phase diffusion for forming extremely high concentration layers such as 20 layers is not easy, alloy type ohmic electrodes are often used. Specifically, taking an nGaAs ohmic electrode as an example, an Au-Ge low melting point alloy or the like is formed on GaAs and heated to an appropriate temperature, for example, 350°C to 550°C.
By heating these materials to excite interfacial reactions, they are alloyed with each other (alloying treatment) to form ohmic electrodes with low contact resistance. In this alloying process, Ga and As, which are the constituent elements of GaAs, are
-Ge diffuses into GaAs, and then Au and Ge interdiffuse into GaAs, forming an extremely highly concentrated n+ layer on the GaAs surface layer. The formation of this n0 layer creates an internal electric field, generates a tunnel current, and realizes ohmic contact between the AuGe electrode and the n-GaAs.

However, due to the above-mentioned interfacial reaction, a large amount of Ga and As, which are the constituent elements of the semiconductor, are dispersed and diffused from the surface, which not only results in an increase in contact resistance (
Warpage may occur in the wafer, or agglomeration may occur in the ohmic electrode due to changes in electrode composition, making it impossible to smooth the electrode surface. As mentioned above, such wafer warpage and damage to the smoothness of the wafer can cause a decrease in resist opening dimensional accuracy and a decrease in yield due to wire breakage during the post-process, such as the roughening process during submicron gate formation and the metallization process. It has become.

Furthermore, Ga melted into the Au-Ge electrode is buried on the surface, and a part of the surface of the Au-Ga formed on the surface of the ohmic electrode is oxidized, increasing the contact resistance with the wiring metal. , the adhesion between them decreases, which in turn causes a decrease in product reliability.

As mentioned above, the alloying process not only forms an ohmic electrode with low resistance, but also has a large impact on the subsequent manufacturing process and device characteristics 1, so various devises and improvements have been made in the past. ing.

A typical example is the reduction in the time required for the alloying process.

This is effective because it shortens the time of the alloying process in order to suppress the amount of Ga and As scattered from GaAs as much as possible. However, as a practical matter, a liquid phase occurs in a part of the Au-Ge alloy at a temperature of 360'C, and because the reaction occurs in this liquid phase, the reaction progresses rapidly, and in fact G
It is difficult to control the amount of a and As scattered.

Therefore, 5i0 formed at a relatively low temperature by CVD method etc.
A method has been proposed in which a wafer on which an Au-Ge alloy layer is formed is coated with two films and then an alloying process is performed. According to this method, the 5iQ2 film is robust and Au-
Although it is effective because it mechanically suppresses the aggregation of Ge,
On the other hand, 3i02 has a large diffusion coefficient for Ga, and
Since the 5i02 film formed at a relatively low temperature is porous, decomposition of the GaAs surface cannot be suppressed. Furthermore, the oxygen in 5i02 oxidizes the Ga melted into the Au-Ge, so when forming A u / Ti etc. as wiring on the Au-Ge ohmic electrode later, the gallium oxide on the surface will be oxidized. The presence of the layer results in poor contact, increased contact resistance, and reduced reliability.

The present invention has been made in view of the above, and its main purpose is to provide a compound semiconductor with a low contact resistance, a smooth surface, and suppress the generation of gallium oxide, etc., so that the contact resistance with wiring metal is low. The purpose is to provide a method for forming an ohmic electrode with good adhesion, and another purpose is to provide a method for forming an ohmic electrode with good adhesion.
An object of the present invention is to provide a method for manufacturing a compound semiconductor device that can suppress thermal decomposition of a semiconductor surface layer, reduce warpage of a wafer, and facilitate the subsequent step of forming a submicron gate.

Means for Solving the Problems> The present invention will be described with reference to FIGS. 3 to 10, which are embodiment drawings.

First, as shown in FIG. 3, on the surface of the conductive layer 4 of the compound semiconductor wafer 1, a metal (for example, Au-Ge/N1) 6.6 to be made into an ohmic electrode is formed by vapor deposition. Then the fourth
As shown in the figure, a semiconductor wafer 1 containing this metal 6.6
A silicon nitride film 7 containing hydrogen is deposited on at least the entire surface of the conductive layer 4 side by plasma CVD. In this state, an alloy treatment is performed at a predetermined temperature in order to form an ohmic connection between the conductive layer 4 and the metals 6, 6.

Thereafter, as shown in FIG. 8, a window 7b is formed in the silicon nitride film 7 above the metals 6, 6 by etching.

After forming a wiring metal (for example, Au/Li) 13.13 on the upper surface of the metal 6.6 through the windows 7b, 7b, the entire wafer is heated at a lower temperature than that in the alloy processing described above. Heat treatment.

Action〉 Before the alloying process, as shown in Fig. 4, the metal 6,
Since the entire surface of the conductive layer 4 side including 6 is covered with the silicon nitride film 7 containing hydrogen, for example, when the semiconductor is GaAs,
The amount of Ga and As scattered from the wafer during the alloying process is suppressed, and metals such as 6, 6, e.g. Au-Qe
As a result of suppressing agglomeration during the alloying process, the contact resistance between the semiconductor and metal 6.6 (ohmic electrode) is reduced, the electrode surface is smoothed, and wafer warping is suppressed. . Furthermore, the hydrogen in the silicon nitride film 7 prevents the generation of gallium oxide, which is caused by Ga melting into the ohmic electrode (metal 6, 6) and depositing on the surface during the alloying process. The adhesion of the wiring metal 13 to the ohmic electrode (metal 6) is improved, and the parasitic resistance between them is reduced.

<Example> Embodiments of the present invention will be described below based on the drawings.

1 to 10 show the present invention in GaAs MESFET (
FIG. 4 is an explanatory diagram showing an example in the order of manufacturing steps when the present invention is applicable to gallium and arsenic mesa type FETs.

As shown in FIG. 1, a GaAs semiconductor wafer 1 is prepared. This wafer 1 is made of GaAs grown by vapor phase epitaxial growth.
Then, on the <100> azimuth horizontal Bridgman Cr-doped semi-insulating substrate 2 (thickness 400 μm), an undoped G
a A s buffing layer 3 (thickness 2 μm, carrier concentration l
Q” cm-yo or less), and n-type QaAs (conductive) layer 4 (thickness 0.5 μm, carrier concentration 3 × 10
It is formed by sequential epitaxial growth of "cm° yo)".

On the surface of the semiconductor wafer 1, as shown in FIG. 2, a desired region of the n-type GaAs layer 4 and the haphazard layer 3 are removed by photoetching to form a mesa M for device isolation. Here 5 is photoresist AZ-
It is 1350. In addition, for etching GaAs, a solution with a sulfuric acid:hydrogen peroxide:water ratio of 3:1:1 was used.
The depth of mesa M is 1.5 μm.

Next, after removing the photoresist 5 and cleaning the surface of the wafer 1, as shown in FIG.
On the upper surface of the As layer 4, Au--Ge/Ni6.6, which will become the source and drain, is formed by vapor deposition using a lift-off method.

Here, the thickness of Au-Ge/Ni is 0.15
p m was set at 10.05 p m.

Thereafter, as shown in FIG.
A hydrogen-containing silicon nitride film (SiNx:H) is deposited on the entire surface of the layer 4 side using a parallel plate plasma CVD method.
7 to 0.05 to 0.5. c+ m thickness, control target thickness 0.1
Formed at ~0.4 μm. Here, N2-diluted 10% 5iHa gas and NH3 gas were used as raw material gases, and the gas flow ratios were 120 SCCM and 48 SCCM, respectively. The pressure during film formation was 1 torr.

The RF power is Q, 5w/Cm2. The hydrogen content of the S i N x film formed under these conditions is 5 atm %. Note that the hydrogen content in the silicon nitride film 7 is
It can be controlled by changing the power, deposition pressure, and gas flow rate ratio, but especially silane (S i H4
) Hydrogen could be effectively introduced into the membrane by increasing the flow rate ratio of NH3 gas to gas. Furthermore, when the flow rate ratio of NH3 gas was reduced, the formed SiNx film became hard and the hydrogen content decreased. Introducing H2 as an additive gas was also effective in increasing the hydrogen content.

Next, alloy processing is performed in the state shown in FIG.

That is, heat treatment is performed at 400° C. for 1 minute in a nitrogen atmosphere to bring the Au-Ge/Ni 6.6 and n-type GaAs layer 4 into ohmic contact. As a result, A u −G
e/N i 6, 6 are ohmic electrodes 6, 6
becomes. Here, the silicon nitride film 7 is dense and Ga
Since the scattering of Ga and As from the As crystal surface is suppressed, there is little damage to the GaA3 surface. .6, no agglomeration occurs, a smooth electrode surface is formed, and warping of the wafer l is prevented (2) Furthermore, due to the reduction action of hydrogen in the silicon nitride film 7, oxidation of Qa deposited on the surface of the AuGe layer is prevented. is suppressed.

Subsequently, as shown in FIG. 5, a photoresist (AZ-1350) 8 is applied onto the silicon nitride film 7, and an opening 8a having a length of 0.3 μm and a width of 200 μm is formed in the photoresist 8 by etching. . During this photoetching, A u -G of the ohmic electrode 6°6
Since the e-alloy layer is smooth and the wafer 1 does not warp, submicron processing becomes easy. After forming the photoresist patterns 8 and 8a, the silicon nitride l117 in the portion communicating with the opening 8a is removed using CF4 gas or active ion etching to form the window 7a, and the n-type G
A portion of the aAS layer 4 is exposed. Next, a recess 4 is formed in the exposed portion of the n-type GaAs layer 4 by etching using a solution containing a mixture of sulfuric acid: hydrogen peroxide: water in a ratio of 1:1:10.
form a. This state is shown in FIG.

Next, as shown in FIG. 7, a photoresist pattern 8.
After 19.10 is deposited from above 8a to a thickness of 0.4 μm by electron beam evaporation, only A19 on the photoresist 8 is removed by dissolving the photoresist 8 using an organic solvent such as acetone. . As a result, AI! A gate 10 made of metal will be formed.

Next, as shown in FIG. 8, photoresist 11 is applied again, and the ohmic electrode 6 is formed using the photoetching method.
．． A window 11a is formed in the photoresist 11 at a location corresponding to the source and drain power supply portions of No. 6.

11a is formed. Then, the portions of the silicon nitride film 7 communicating with the windows 11a and lla are removed by mild UHF to form windows 7b and 7b.

After that, as shown in FIG.
1. Wiring metal consisting of Ti and Au is deposited from above 11a and 11a. As a result, the wiring metals 12 and 13.1 are placed on the ohmic electrodes 6, 6 through the photoresist 11 and the windows 7b, 7b, respectively.
3 is deposited. Next, the photoresist 11 is removed using an organic solvent, and as shown in FIG. Pad 13
゜13. Thereafter, heat treatment is performed at 350°C for 20 minutes to complete the process.

GaAsMESF manufactured according to the above embodiments of the present invention
In ET, when the contact resistance between the wiring metal Ti and the ohmic electrode was measured, it was found to be I x 10-9ΩcI112
It turned out to be small. By the way, when a SiO2 film is deposited on the wafer surface using the CVD method before alloy processing, this contact resistance is I x 10-'Ωcm2, which can be reduced by about one order of magnitude with the present invention. . The reason for this is thought to be that the present invention suppresses the formation of a gallium oxide layer on the surface of the ohmic electrode 6.6.

In addition, GaAsMESF manufactured according to the embodiment of the present invention
When the ET was subjected to a high temperature test at 150°C, there was no change in source/drain resistance and no change in drain current was observed.

Note that the present invention is not limited to the above embodiments (
, e.g. InP, AI GaAs, InGaAs
The present invention can also be applied to methods of manufacturing other compound semiconductor devices such as P.

<Effects of the Invention> As explained above, according to the present invention, when forming an ohmic electrode on a conductive layer of a compound semiconductor wafer such as GaAs, A u -G e to be an ohmic electrode is formed.
After forming a conductive layer by vapor deposition, a silicon nitride film containing hydrogen is deposited on the entire conductive layer side surface of the wafer containing this metal by plasma CVD method before alloying process. The amount of constituent elements such as Ga and As that are scattered from the wafer during the process is suppressed, and at the same time, the aggregation of metals such as Au-Ge, which form the ohmic electrode, is suppressed, and the contact between the semiconductor and the ohmic electrode is suppressed. Resistance is reduced, the electrode surface is smoothed, and wafer warpage is suppressed. Furthermore, hydrogen in the silicon nitride film prevents oxidation of Ga melted on the Au-Ge electrode or the like in the alloying process.

Smoothing the electrode surface and preventing the formation of gallium oxide on the electrode surface improves the adhesion between the two and reduces the contact resistance between the two during the subsequent process of vapor deposition of wiring metal. Coupled with the reduction in contact resistance between electrodes, a good and highly reliable ohmic electrode is obtained.

In addition, in the process of forming the ohmic electrode, warping of the wafer is suppressed as described above, so that the formation of the submicron gate, which is a subsequent process, is facilitated.

[Brief explanation of the drawing]

FIGS. 1 to 10 are explanatory diagrams sequentially showing the manufacturing process of an embodiment of the present invention. 1...GaAs semiconductor wafer 2...GaAs substrate 3...Buffer 1 layer 4''.n-type GaAs (conductive) layer 4a...Recess 5...Photoresist 6...Ohmic electrode ( A u - G e /N
i) 7...Silicon nitride films 7a, 7b...Window 8...Photoresist 8a...Opening 9...AJ10...Meet (, 11...Photoresist 11a...・Window 12-A u/T i

Claims (1)

[Claims] A method for forming an ohmic electrode on the surface of a conductive layer of a compound semiconductor wafer, wherein a metal to be formed as an ohmic electrode is formed on the surface of the conductive layer by vapor deposition, and then at least one of the semiconductor wafers containing this metal is formed on the surface of the conductive layer. After a silicon nitride film containing hydrogen is deposited on the entire surface of the conductive layer side by plasma CVD, an alloying process is performed at a predetermined temperature to form an ohmic bond between the compound semiconductor and the metal. After that, a window is formed in the silicon nitride film above the metal by etching, and a wiring metal is deposited on the upper surface of the metal through this window, and then the entire wafer is heated at a temperature lower than that in the alloy process. A method for manufacturing a semiconductor device, the method comprising heat treatment.