JPH05275688A - Planar type power semiconductor element - Google Patents

Abstract

PURPOSE:To provide a planar type power semiconductor element which is improved in trade off between a turn-OFF loss and a voltage blocking capacity. CONSTITUTION:A P-type silicon substrate 2 serving as a P<+>-type emitter layer is directly joined to an N-type silicon substrate 6 which serves as a base of high resistance for the formation of a wafer, an IGBT is formed of the wafer concerned and provided with a P-type base layer 7 whose junction terminates at the surface of the wafer, where a deep N<+>-type buffer layer 5 is selectively formed in a region of the surface of the N-type silicon substrate 6 where a main current of the element flows, and the surface of the substrate 6 is joined to the P<+>-type silicon substrate 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a planar type power semiconductor device having a structure in which the main junction of the device terminates on the surface of a semiconductor wafer.

[0002]

2. Description of the Related Art In a power semiconductor element such as an IGBT or a thyristor, p is selectively formed on the surface of a high resistance n-type base layer.
There is a planar type element in which a p-base / n-base junction (main junction) is terminated on the wafer surface by forming a die base layer by diffusion. In this type of planar element, the electric field concentration when applying a forward bias is greatest in the junction termination region of the main junction. Therefore, breakdown is likely to occur in the junction termination region.

In order to improve the voltage blocking capability of such a planar power semiconductor device, it is effective to increase the thickness of the high resistance n-type base layer. This is p base /
This is because when a reverse bias is applied to the n-base junction, the thicker the n-type base layer is, the more the depletion layer can be expanded in the n-type base layer, and the electric field strength at the junction can be reduced. However, when the thickness of the high-resistance n-type base layer is increased, the amount of carriers accumulated in the device during energization increases, and the carrier discharge time at turn-off increases. As a result, turn-off loss increases and device characteristics deteriorate.

As a method of improving the trade-off between the voltage blocking capability and the turn-off loss in such a planar type power semiconductor device, the present inventor has already found that the region in which the main current mainly flows (hereinafter referred to as the main operation). It is proposed to increase the thickness of the junction termination region in comparison with the thickness of the n-type base layer (referred to as region) (Japanese Patent Application No. 62-043163).

On the other hand, a method of directly joining two mirror-polished semiconductor substrates is known as an effective method for obtaining a wafer for a power semiconductor device. 6 (a) to 6 (c) show steps of manufacturing an IGBT using this method. As shown in FIG. 6 (a), p ⁺ P ⁺ which is the first semiconductor substrate to be the emitter layer Providing a n-type silicon substrate 6 which is a second semiconductor substrate serving as the -type silicon substrate 2 and the n-type base layer, in advance to the n-type silicon substrate 6 side n ⁺ Type buffer layer 5
And p ⁺ P ^{+ which is} a part of the emitter layer The mold layer 4 is formed. These are directly bonded as shown in FIG. 6 (b) to obtain an integrated wafer. After adjusting the n-type base layer side to a predetermined thickness using this wafer, as shown in FIG. 6 (c), p
Mold base layer 7, n ⁺ The type emitter layer 8 and the MOS gate are formed to obtain an IGBT.

In the IGBT using this direct bonding wafer, n ⁺ The mold buffer layer 5 is uniformly formed in the wafer. Therefore, when a reverse bias is applied between the p base and the n base, the depletion layer extends as shown by the broken line in the figure,
Since the curvature of the curved portion 19 is small, strong electric field concentration occurs. In order to alleviate this electric field concentration and obtain a high voltage blocking ability, it is preferable that the thickness of the n-type base layer is large, but if so, the turn-off loss becomes large as described above.

[0007]

As described above, in the conventional planar power semiconductor device using the wafer by the direct bonding method, a sufficiently high voltage blocking capability cannot be obtained unless the turn-off loss is increased. was there.

The present invention has been made in view of the above points,
An object of the present invention is to provide a planar power semiconductor device in which the trade-off between turn-off loss and voltage blocking capability is improved by using a wafer formed by direct bonding.

[0009]

According to the present invention, a first semiconductor substrate of a first conductivity type or a second conductivity type is directly bonded to a second semiconductor substrate having a high resistance base layer of a second conductivity type. A planar power type power source, which is formed by using the semiconductor wafer obtained by the above, and in which a first conductivity type semiconductor layer which selectively forms a main junction with the high resistance base layer is formed on the surface of the high resistance base layer by diffusion. In the semiconductor element, a deep second conductivity type buffer layer is selectively formed in advance in a main operation region of a surface of the second semiconductor substrate to be joined to the first semiconductor substrate.

[0010]

According to the present invention, it is possible to obtain a planar power semiconductor device in which the junction termination region is larger than the high resistance base layer thickness in the main operation region of the device while using the direct junction wafer. This improves the trade-off between turn-off loss and voltage blocking capability.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an IGBT according to an embodiment of the present invention.
FIG. 5 is a cross-sectional view of the manufacturing process of As shown in FIG. 1 (a), p ⁺
P ⁺ which becomes the emitter layer The n-type silicon substrate 2 and the n-type silicon substrate 6 serving as the high-resistance n-base are prepared, and p ⁺ P ^{+ which is} a part of the emitter layer Mold layer 4 and n ⁺ The mold buffer layer 5 is formed. Outside the main operation region of the n-type silicon substrate 6, that is, outside the junction termination region, n ⁺ Is the buffer layer 5
Shallower n ⁺ The mold buffer layer 3 is formed. Next, these substrates are directly bonded as shown in FIG. 1 (b) to obtain an integrated wafer. The broken line 20 indicates the bonding interface.

After the high resistance n base layer side of the wafer thus integrated is polished to a predetermined thickness, FIG.
An IGBT is formed as shown in FIG. That is, first, the oxide film 10 is formed on the surface of the polished n base layer, and is patterned so as to cover the field region. Then, a gate oxide film 11 is formed, and a gate electrode 12 made of a polycrystalline silicon film is patterned on the gate oxide film 11. Thereafter, boron is selectively diffused using the gate electrode 12 as a mask to form the p-type base layer 7, and then n ⁺ Type emitter layer 8 and n ⁺ The mold contact layer 9 is formed. Next, semi-insulating SIPOS
A film is formed over the field region to form the resistive field plate 14. Then, Al is vapor-deposited and patterned to form the p-type base layer 7 and the n ⁺ Type emitter layer 8
Electrode 15 connected to the n-type base layer through the contact layer 9 simultaneously with the cathode electrode 15
To form. The cathode electrode 15 is patterned on the resistive field plate 14 so as to extend a predetermined distance outward from the junction termination of the p-type base layer 7. Finally p
⁺ Amode electrode 1 with V / Ni / Au film on the mold substrate 2 side
To complete.

In the IGBT of this embodiment, when a reverse bias is applied to the p base / n base junction, the depletion layer extending to the n base side is as shown by the broken line in the figure. Assuming that the n base thickness in the main operation region is the same as that of the conventional FIG. 6 (c), the n base layer thickness in the junction termination region is larger than that of the conventional one. Therefore, the curvature of the depletion layer curved portion 17 just below the junction termination portion is larger than that of the curved portion 19 in FIG. 6 (c). The distance between the p base layer 7 and the curved portion 17 is also larger than that of the conventional one. As described above, according to this embodiment, it is possible to obtain a higher voltage blocking capability than the conventional one with the same turn-off loss as the conventional one.

2 and 3 show another embodiment of the IGBT.
FIG. 5 is a cross-sectional view of the manufacturing process of The parts corresponding to those of the previous embodiment are designated by the same reference numerals. In this embodiment, first, p ⁺ As shown in FIG. 2 (a), a groove is formed on the surface of the type silicon substrate 2, and then the surface on which the groove is formed is
An oxide film 18 is formed as shown in (b). Then, the surface on the side where the oxide film 18 is formed is polished, and as shown in FIG. 2 (c), the convex portion of the groove is flat with the silicon substrate exposed and the oxide film 18 left in the concave portion. Get the mirror surface.

The other n-type silicon substrate 6 has a structure shown in FIG.
As shown in (d), p ⁺ Mold layer 4 and n
⁺ The mold buffer layer 5 is selectively formed. Then, these substrates are directly bonded to obtain a wafer as shown in FIG. Thereafter, an IGBT as shown in FIG. 3B is formed on this wafer through the same steps as those in the previous embodiment.

In the case of this embodiment, the n ⁺ base of the previous embodiment is provided at the bottom of the n base of the junction termination region. The structure is such that an oxide film 18 is buried in place of the mold buffer layer 3. When a reverse bias is applied to the p-base / n-base junction, even if the depletion layer tip reaches the oxide film 18, a potential gradient is generated in the oxide film 18 to relax the junction electric field. Therefore, also in this embodiment, the trade-off between the voltage blocking capability and the turn-off loss is improved.

Although the embodiment of the IGBT has been described above, the present invention is not limited to this, and the present invention is applied to other various planar type power semiconductor devices configured by using a direct bonding wafer. It is possible.

For example, FIG. 4 shows an embodiment in which the present invention is applied to a thyristor with a MOS gate. Also in this example,
The parts corresponding to those in FIG. 1 are designated by the same reference numerals as those in FIG.
In this embodiment, the cathode electrode 15 is not in contact with the p-type base layer 7 for thyristor operation, but the other structure and manufacturing process are basically the same as those of the IGBT of FIG. In this embodiment, the same effect as that of the previous embodiment can be obtained.

FIG. 5 shows an embodiment applied to a planar type high breakdown voltage diode. Also in this embodiment, portions corresponding to those in FIG. 1 are designated by the same reference numerals. P in the previous example
⁺ In this embodiment, n ^+, which becomes the cathode region, is used instead of the type silicon substrate 2. The mold silicon substrate 21 is used. n-type p-type anode layer 22 junction terminating on the surface of the base layer 6 is formed diffusion anode electrode 23 is formed on this, n ⁺ A cathode electrode 24 is formed on the back surface of the mold substrate 21. Also in this embodiment, n ^{+ is} selectively preliminarily selected in the main operation region on the n base side from the bonding interface 20 of the two substrates. The mold buffer layer 5 is formed. Also in this embodiment, the same effect as the previous embodiment can be obtained.

[0021]

As described above, according to the present invention, it is possible to provide a planar type power semiconductor device in which the trade-off between the turn-off loss and the voltage blocking ability is improved by using a wafer formed by direct bonding.

[Brief description of drawings]

FIG. 1 is a diagram showing a manufacturing process of an IGBT according to an embodiment of the present invention.

FIG. 2 is a diagram showing a manufacturing process of an IGBT of another embodiment.

FIG. 3 is a view showing a manufacturing process of the IGBT of the same embodiment.

FIG. 4 is a diagram showing a thyristor with a MOS gate according to another embodiment.

FIG. 5 is a diagram showing a planar diode according to another embodiment.

FIG. 6 is a diagram showing a manufacturing process of a conventional IGBT.

[Explanation of symbols]

1 ... Anode electrode, 2 ... p ⁺ Type silicon substrate (p ⁺ Type emitter layer), 3 ... n ⁺ Type buffer layer, 4 ... p ⁺ Mold layer, 5 ... n ⁺ Type buffer layer, 6 ... n type silicon substrate (high resistance n type base layer), 7 ... p type base layer, 8 ... n ⁺ Type cathode layer, 10 ... Oxide film, 11 ... Gate oxide film, 12 ... Gate electrode, 14 ... Resistive field plate, 15 ... Anode electrode.

Claims (1)

[Claims] 1. A second semiconductor substrate having a first conductivity type or a second conductivity type first semiconductor substrate and a second conductivity type high-resistance base layer.
A semiconductor substrate obtained by directly bonding to the semiconductor substrate, and a first conductivity type semiconductor layer selectively forming a main bond with the high resistance base layer on the surface of the high resistance base layer. In the diffused planar power semiconductor device, a deep second conductivity type buffer layer is selected in advance in a region where a main current of the device on the surface of the second semiconductor substrate to be joined to the first semiconductor substrate flows. Planer type power semiconductor device characterized by being formed in a uniform manner.