JPH0528859B2 - - Google Patents
Info
- Publication number
- JPH0528859B2 JPH0528859B2 JP62142311A JP14231187A JPH0528859B2 JP H0528859 B2 JPH0528859 B2 JP H0528859B2 JP 62142311 A JP62142311 A JP 62142311A JP 14231187 A JP14231187 A JP 14231187A JP H0528859 B2 JPH0528859 B2 JP H0528859B2
- Authority
- JP
- Japan
- Prior art keywords
- channel
- chp
- che
- processing device
- processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14231187A JPS63307565A (ja) | 1987-06-09 | 1987-06-09 | チャネル処理装置 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14231187A JPS63307565A (ja) | 1987-06-09 | 1987-06-09 | チャネル処理装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63307565A JPS63307565A (ja) | 1988-12-15 |
| JPH0528859B2 true JPH0528859B2 (enExample) | 1993-04-27 |
Family
ID=15312407
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14231187A Granted JPS63307565A (ja) | 1987-06-09 | 1987-06-09 | チャネル処理装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63307565A (enExample) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5837578B2 (ja) * | 1975-11-07 | 1983-08-17 | 株式会社日立製作所 | チヤネルソウチ |
| JPS55140923A (en) * | 1979-04-18 | 1980-11-04 | Hitachi Ltd | Information processing system |
| JPS5994129A (ja) * | 1982-11-19 | 1984-05-30 | Mitsubishi Electric Corp | 論理チヤネル番号割当て方法 |
-
1987
- 1987-06-09 JP JP14231187A patent/JPS63307565A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63307565A (ja) | 1988-12-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4991079A (en) | Real-time data processing system | |
| US4674033A (en) | Multiprocessor system having a shared memory for enhanced interprocessor communication | |
| US4096572A (en) | Computer system with a memory access arbitrator | |
| JPH02289017A (ja) | コンピユータシステム内でデータ転送方法 | |
| US5255369A (en) | Multiprocessor system with reflective memory data transfer device | |
| KR950010529B1 (ko) | 프로세서간 통신을 위한 메모리 공유 장치 | |
| US5581732A (en) | Multiprocessor system with reflective memory data transfer device | |
| JP2591502B2 (ja) | 情報処理システムおよびそのバス調停方式 | |
| JPH0528859B2 (enExample) | ||
| JPS602710B2 (ja) | 複合計算機システム | |
| JPH0238968B2 (enExample) | ||
| JPH087738B2 (ja) | エンディアン変換方式 | |
| JPH0140432B2 (enExample) | ||
| JP2536162B2 (ja) | デ―タ転送システム | |
| JPS598845B2 (ja) | チヤンネル制御方式 | |
| KR940003300B1 (ko) | 파이프라인 버스 프로토콜을 사용하는 시스템의 메모리큐 | |
| JP2718661B2 (ja) | デュアルポートメモリ制御装置 | |
| JP3443787B2 (ja) | 自立分散型プラント制御マンマシン装置 | |
| JPS5846423A (ja) | ダイレクトメモリアクセス装置のインタ−フエイス回路 | |
| JPS61234447A (ja) | バス獲得制御装置 | |
| JPS61117651A (ja) | インタ−フエイス装置 | |
| JPH04360248A (ja) | リモートファイル更新方式 | |
| JPH02148305A (ja) | ファームウエアによるデータ転送装置 | |
| JPH01112452A (ja) | デイスクキヤツシユ制御方式 | |
| JPS63217444A (ja) | 多重ポ−トメモリ |