JPH05275544A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To dispense with the margin of a contact hole to conductor wiring layers and to contrive the improvement of the integration degree of a semiconductor integrated circuit device by a method wherein the surface of an interlayer insulating film covering the upper surface of the first conductor wiring layer is etched flat to the surface height of the first conductor wiring layer and after that, the second conductor wiring layer is formed. CONSTITUTION:A first conductor wiring layer 3 is formed on a semiconductor substrate 1 via a silicon oxide film 2. After an interlayer insulating film 4 formed with the aim of insulating from a second conductor wiring layer is grown on the layer 3, a photoresist 5 is applied in such a way that its surface is formed flat. The film 4 is flatly etched to the position of the surface of the layer 3 by an etchback technique. Moreover, a second conductor wiring layer 6 is formed, is patterned and the layers 3 and 6 are made to connect to each other without the intermediary of a contact hole. Thereby, the margin of the contact hole to the layers 3 and 6, which has been hitherto required in a semiconductor integrated circuit device, becomes unnecessary and the integration degree of the device can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for connecting conductor wirings of two layers.

[0002]

2. Description of the Related Art In a conventional semiconductor device, generally two conductor wiring layers are connected to each other.
As shown in the sectional view of the ZZ portion in FIG.
Connection is made by forming a contact hole 44 in an interlayer insulating film formed for insulating the first conductor wiring layer 43 and the second conductor wiring layer 45 on the silicon oxide film 42 on the semiconductor substrate 41. I was going. However, according to the conventional method of forming the contact hole 44 in the interlayer insulating film, as shown in FIG. 4A, the conductor wiring layers 43 and 45 in the portion where the contact hole 44 is formed are formed by photoetching for forming the conductor wiring layer. A margin of a certain dimension is required to prevent the contact hole from protruding from the conductor wiring layer due to misalignment between the process and the photoetching process for opening the contact hole, overetching of each process, and the like.

[0003]

However, in recent semiconductor integrated circuit devices, the margin between the contact hole and the conductor wiring layer cannot be secured due to the reduction in element size. In a memory IC typified by VLSI, the pitch of the conductor wiring layer is determined by the size of the memory cell. Therefore, in particular, the polycrystalline silicon wiring forming the word selection line and the upper portion of the dynamic random access memory (DRAM) are formed. In the wiring layer connecting portion, when the above-mentioned margin is attempted to be taken as shown in FIG. 5, a design standard violation occurs in the semiconductor wiring layer interval. For example, 64 Mbit DR
In AM, it is considered that the memory cell pitch is 1.0 μm or less, the contact hole size is 0.5 μm, and the margin between the contact hole and polycrystalline silicon is about 0.2 μm. When the contact hole 52 is formed on the polycrystalline silicon wiring 51 by designing the portion shown in FIG. 5 based on such design criteria, the minimum polycrystalline silicon wiring spacing in FIG. 5 is about 0.2 μm.
m, which is about 0.4 μm, which violates the design standard of polycrystalline silicon wiring.

As described above, in a semiconductor integrated circuit device which requires a high degree of integration such as a memory IC, it is necessary to eliminate the margin between the contact hole and the conductor wiring layer.

[0005]

According to a method of manufacturing a semiconductor integrated circuit device of the present invention, a surface of an interlayer insulating film covering an upper surface of a first conductor wiring portion is flatly etched to a height of the first conductor wiring surface, After that, the second conductor wiring is formed. As a result, the margin between the contact hole and the conductor wiring layer, which is required in the conventional semiconductor integrated circuit device, is unnecessary.

[0006]

The present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing a method of manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention in the order of manufacturing steps. Figure 1
(A) shows a state in which the first conductor wiring layer 3 is formed on the conductor substrate 1 with the silicon oxide film 2 interposed therebetween. The present invention can be applied to the first conductor wiring layer 3 made of polycrystalline silicon or metal. Here, the first conductor wiring layer 3 is patterned by a generally known photoetching technique. Next, as shown in FIG. 1B, a second conductor is formed on the first conductor wiring layer 3.
After growing the interlayer insulating film 4 for insulation from the conductor wiring, the photoresist 5 is applied so that the surface becomes flat. After that, FIG. 1C shows a state in which the surface of the first conductor wiring layer is flatly etched by a generally known etchback technique. After that, the state in which the second conductor wiring layer 6 is formed and patterned is shown in FIG.
Here, the second conductor wiring layer 6 may be made of polycrystalline silicon or metal, like the first conductor wiring layer 3, and the present invention can be applied. In this way, the first conductor wiring layer 3 and the second conductor wiring layer 6 can be connected without passing through a contact hole. When the first conductor wiring layer of this embodiment is made of polycrystalline silicon having a relatively high resistance, the contact wiring is opened by using the conductor wiring layer having a lower resistance as the second layer wiring. Without it, the resistance of polycrystalline silicon can be lowered.

Next, FIGS. 2 and 3 show a semiconductor integrated circuit device according to a second embodiment of the present invention. 2 is a plan view thereof, and FIG. 3 is a sectional view showing the XX portion and the YY portion of FIG. 2 in the order of steps.

First, as shown in FIG. 3A, the first conductor wiring layer 2 is formed on the silicon oxide film 32 on the semiconductor substrate 31.
1 is formed by patterning, an interlayer insulating film 34 is formed thereon, and a first photoresist 35 having a flat surface is further formed, and then a second photoresist 36 is formed on the interlayer insulating film 34. Patterning is performed on a portion other than where the hole portion 23 is formed. Next, as in the first embodiment, the first conductor wiring layer 21 is exposed only in the opening 23 of the interlayer insulating film 34 by the etch back technique as shown in FIG. By forming and patterning the second conductor wiring layer 22 as shown in (c), the structure of the present invention can be realized only in a part of the semiconductor device. By using the second embodiment, for example, in order to realize the connection between the polycrystalline silicon wiring layer forming the word selection line of the DRAM and the upper wiring, the polycrystalline silicon wiring width 0.4 μm, the wiring interval 0.4 μm, Even if the upper wiring width is 0.5 μm and the wiring interval is 0.4 μm, it becomes 0.9 μm and 1.0 μm.
It becomes possible to connect within a pitch of memory cells of m or less.

[0009]

As described above, according to the method of the semiconductor integrated circuit device of the present invention, the surface of the interlayer insulating film covering the upper surface of the first conductor wiring portion is flatly etched to the height of the first conductor wiring surface. After that, the second conductor wiring is formed, so that the margin between the contact hole and the conductor wiring layer, which is required in the conventional semiconductor integrated circuit device, can be made unnecessary.

[Brief description of drawings]

FIG. 1 is a vertical sectional view showing a first embodiment of the present invention in the order of manufacturing steps.

FIG. 2 is a plan view showing a second embodiment of the present invention.

FIG. 3 is a vertical cross-sectional view showing the XX section and the YY section of FIG. 2 in the order of manufacturing steps.

4A and 4B are diagrams showing a conventional contact hole forming method, in which FIG. 4A is a plan view and FIG. 4B is a vertical sectional view of a ZZ portion in FIG.

FIG. 5 is a diagram showing a method of forming contact holes at a DRAM memory cell pitch.

[Explanation of symbols]

 1, 31, 41 Semiconductor substrate 2, 32, 42 Silicon oxide film 3, 21, 43 First conductor wiring layer 4, 34 Interlayer insulating film 5, 35, 36 Photoresist 6, 22, 45 Second conductor wiring layer 23 Opening of interlayer insulating film 44, 52 Contact hole 51 Polycrystalline silicon wiring

Claims (1)

[Claims] 1. A surface of an interlayer insulating film, which covers an upper surface of a first semiconductor wiring portion formed on a semiconductor surface, is flatly etched to a height of the first semiconductor wiring surface to expose a first conductor wiring layer, and thereafter. A method of manufacturing a semiconductor device, comprising forming a second conductor wiring to connect the first conductor wiring layer and the second conductor wiring layer.