JPH01199462A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enhance integration and improve reliability by a method wherein an impurity-containing first polycrystalline silicon layer to serve as a wire for a resistance element to be formed on an insulating film on a semiconductor substrate is formed on the insulating film and a second polycrystalline silicon layer is formed to extend from the first polycrystalline silicon layer to the insulating film. CONSTITUTION:An impurity-containing first polycrystalline silicon layer 103, which is to serve as a wire for a resistance element to be formed on an insulating layer 102 on a semiconductor substrate 101, is formed on the insulating film 102; and a second polycrystalline silicon layer 104, which is to serve as a resistor, is formed, extending from the first polycrystalline silicon layer 103 to land on the insulating film 102. The first polycrystalline silicon layer 103 should preferably be thicker than the second polycrystalline silicon layer 104. In such a design, with a wire and a resistor being connected not through the intermediary of a contact hole, overlap for a photoetching process may be dispensed with between the two, which enables miniaturization. There exists a stable contact resistance between the wire and the resistor in the presence of a larger area of contact between the two, which contributes to the improvement on reliability.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device, and particularly to a resistor element structure of a semiconductor device.

(Prior Art) As the degree of integration of LSIs improves, polycrystalline silicon resistor technology is becoming increasingly important. In the case of a high resistance load type static RAM, a resistance element with a very high resistance value is required.

As a recent example, “The advent of IMSRAM heralds the beginning of the era of high integration and high speed”; Nikkei Micro Devices, 198.
There is a technique disclosed in the March 2007 issue, pp. 53-65.

Figure PJJ2 is a cross-sectional view of the resistance element structure extracted from this document. This conventional structure consists of a first polycrystalline silicon layer containing impurities to serve as wiring, a second polycrystalline silicon layer containing no impurities or a trace amount of impurities to serve as resistance, and contact holes in the living room insulation film. It was tied together.

[Problem to be solved by the invention]

The conventional technology has the following drawbacks.

The first polycrystalline silicon layer 201, which is a wiring, and the second
The polycrystalline silicon layer 202 is connected to the interlayer insulating LI 203 via a contact hole, that is,
The interlayer insulating film 2 is formed on the first polycrystalline silicon layer 201.
It is necessary to form a contact hole 03. Therefore, since a margin for overlapping must be provided, the area of the first polycrystalline silicon 201 must be made large, which is a major barrier to miniaturization.

Further, the second polycrystalline silicon 202 also requires a margin for overlapping with the contact hole, making it impossible to miniaturize the resistor element and thus the chip area.

Furthermore, since the contact area between the first polycrystalline silicon 201 and the second polycrystalline silicon 202 is small, the contact resistance becomes unstable, which leads to a decrease in reliability.

As described above, the above-mentioned conventional technology has the problem that high integration is impossible and reliability is low.

(Means for Solving the Problems) In the semiconductor device of the present invention, in a resistive element formed on an insulating film on a semiconductor substrate, a first polycrystalline silicon layer containing impurities that becomes a wiring is formed on the insulating film. The semiconductor device is characterized in that a second polycrystalline silicon layer is formed on the first polycrystalline silicon layer and serves as a resistor, and the second polycrystalline silicon layer is formed on the first polycrystalline silicon layer and on the insulating film. The film thickness of the second polycrystalline silicon layer is thicker than the film thickness of the second polycrystalline silicon layer.

(Embodiment) FIG. 1 is a sectional view of a semiconductor device in an embodiment of the present invention. 101 is a semiconductor substrate, 102 is an insulating film, 103
is the first polycrystalline silicon containing impurities which is a wiring, 10
4 is a second polycrystalline silicon which is a resistor and does not contain impurities or contains a trace amount of impurities.

The details will be explained step by step (Fig. 3). First, as shown in FIG. 3(a), an insulating film 302 with a thickness of 4000 angstroms is formed on a semiconductor substrate 301 to isolate it from other elements.

On top of that, the first polycrystalline silicon 303 that will become the wiring is placed at 250 mm.
The first polycrystalline silicon 303 is deposited by thermally decomposing the normal monosilane gas that forms 0 (angstroms) at 620 ("C). Amorphous silicon deposited at a low temperature of 560 ("C) may also be used.

Next, as shown in FIG. 3(b), the first polycrystalline silicon 30
In order to lower the resistance value of 3, impurity ions such as phosphorus and boron are implanted. In order to sufficiently lower the resistance value, the dose is preferably 5XIOIS (cm-'') or more.

Next, as shown in FIG. 3(C), the first polycrystalline silicon 30
A second resist 306 is formed in areas other than unnecessary portions 3, and using this as a mask, the first polycrystalline silicon 303 is etched. After that, the first Lujist 306 is removed.

Next, as shown in FIG. 3(d), second polycrystalline silicon 305, which will become a resistor, is deposited in the same manner as the first polycrystalline silicon 303. The thickness of the second polycrystalline silicon 305 is determined depending on the required resistance value. Note that 3-morphous silicon may also be used.

Next, as shown in FIG. 3(e), a second resist is formed so as to cover the first polycrystalline silicon 303 in the area required as a resistor, and only the second polycrystalline silicon is isotropically etched. . Then, the second resist 307 is removed,
In order to activate the impurities in the first polycrystalline silicon 303, an annealing process of 1000C (30 seconds) is performed.

Through the above steps, the resistance element of the present invention is completed. forming the first polycrystalline silicon 303, and then forming the first polycrystalline silicon 303;
Metal silicide may be formed on the polycrystalline silicon 303 to lower the resistance value.

Further, it is possible to freely change the film thicknesses of the first polycrystalline silicon 303 and the second polycrystalline silicon 305.

That is, the film thickness of the first polycrystalline silicon 304 is increased;
By reducing the thickness of the second polycrystalline silicon 305, it is possible to fabricate a resistance element having wiring with a low sheet resistance value and a very high sheet resistance value.

It goes without saying that the present invention is not limited to the above-described embodiments, and that various changes can be made without departing from the gist thereof.

(Effects of the Invention) As described above, according to the invention, the following effects can be obtained.

(1) Since the wiring and the resistor are not connected through a contact hole, there is no need for overlapping allowance for photo-etching, making it possible to miniaturize the device and reduce the chip area. .

(2) Since the wiring and the resistor are not connected through a contact hole, the contact area between the wiring and the resistor can be large, and the contact area is also good, so the contact surface is stable, that is, the contact resistance is low. Since it is stable, reliability is improved.

(3) Since there is no interlayer insulating film between the wiring and the resistor, the surface is planarized accordingly. Also, the number of steps is small.

[Brief explanation of the drawing]

FIG. 1 is a main sectional view showing an embodiment of the semiconductor device of the present invention. FIG. 2 is a main sectional view showing a conventional semiconductor device. FIGS. 3(a) to 3(e) are main sectional views of each manufacturing process of a semiconductor device showing an embodiment of the present invention. 101... Semiconductor substrate 102... Insulating film 103... First polycrystalline silicon 104... Second polycrystalline silicon 201... First polycrystalline silicon 202... Second polycrystalline silicon 203... ...Interlayer insulating film 204...Insulating film 205...Semiconductor substrate 301...Semiconductor substrate 302...Insulating film 303...First polycrystalline silicon 304...Durium ion beam 305... ...Applicant for polycrystalline silicon and above Seiko Epson Co., Ltd. Patent attorney Tsutomu Mogami (1 other person) Figure 3

Claims (2)

[Claims] (1) A first polycrystalline silicon layer containing impurities, which is formed on an insulating film on a semiconductor substrate and serves as wiring for a resistance element, is formed on the insulating film, and a second polycrystalline silicon layer, which serves as a resistor, is formed on the insulating film. . A semiconductor device, wherein the semiconductor device is formed from above the first polycrystalline silicon layer to above the insulating film. (2) The first polycrystalline silicon layer is thicker than the second polycrystalline silicon layer.
1. Semiconductor device described in Section 1.