JPS6194368A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a device having high density and high performance by superposing an inter-layer insulating film while coating the upper surface of a gate electrode with an insulating film and forming a connecting hole partially superposed to the gate electrode on viewing from an upper surface by etching the inter-layer insulating film in an anisotropic manner. CONSTITUTION:A P type Si substrate 1 is insulated and isolated 2, a gate electrode 4 is shaped onto the gate insulating film 2, a CVDSiO2 film 9 is superposed, and As is implanted to form source-drain layers 5. A CVDSiO2 film 6 and a resist 10 are superposed, and an opening is bored so as to be superposed to the electrode 4. SiO2 is left on the side surface of the electrode 4 through anisotropic etching by CHF3 gas while using the resist 10 as a mask, and an Al wiring 8 is shaped. According to the constitution, the opening 7 is shaped to the gate electrode 4 in a self-alignment shape, thus forming a device having high density. The distance of a channel under the gate electrode and the hole 7 is shortened, and a resistance component in the source-drain layers can be reduced, thus obtaining the device having high performance.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device in which a contact hole is formed in a self-aligned manner in a gate electrode pattern.

Conventional Structures and Their Problems As semiconductor devices become increasingly finer, pattern misalignment between different masks has become a problem in their manufacture. Therefore, in mask design, it is necessary to provide a margin in consideration of pattern misalignment, which makes it difficult to realize fine elements.

FIG. 1 shows a cross-sectional view of a conventional MIS transistor. A
The contact hole 7 between the C wiring layer 8 and the source/drain region 6 is not allowed to come into contact with the gate electrode 4 . Therefore, a sufficient distance margin was required between the contact hole 7 and the gate electrode 4 in consideration of mask misalignment. Therefore, the source/drain region 5 has to be formed with a large area, which increases the size of the transistor. In addition, the resistance component of the source/drain region 5 existing between the channel portion under the gate electrode 4 and the contact surface of the contact hole 7 also had an adverse effect on the operation of the transistor.

OBJECTS OF THE INVENTION The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device in which a contact hole can be formed in a self-aligned manner with a gate electrode pattern.

Structure of the Invention The present invention involves coating the upper surface of a gate electrode in advance with an insulating film, and then depositing an interlayer insulating film over the entire surface, and forming a contact hole that partially overlaps with the gate electrode when viewed from the upper surface of a semiconductor substrate using the interlayer insulating film. By forming the film by anisotropic etching, it is possible to manufacture high-density, high-performance semiconductor devices.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention is shown in FIGS. 2(a) to (d). These figures show cross-sectional views of a semiconductor device in the order of steps. For example, after forming an insulating isolation portion 2 on a P-type Si substrate 1, a gate insulating film 3 is formed.

In the conventional method, a gate electrode material made of polycrystalline silicon, a high melting point metal, or a silicide thereof is deposited thereon to form the gate electrode 4, but in the present invention, after depositing the gate electrode material, the gate electrode 4 is further formed by, for example, CVD. S by law
By depositing, for example, 3,000 102 films and anisotropically etching them, the S 1
The 02 films 9 are in an overlapping state. In this case, for example, As
Ion implantation is performed to form source/drain regions 5.

(Fig. 2(a)) Next, an interlayer insulating film 6 is formed by depositing, for example, 5,000 51o2 films on the entire surface by CVD, and a contact hole pattern is formed on the interlayer insulating film 6 using a photoresist 1o. Form it so that it overlaps 4. (Figure 2(b))
When the SiO2 film 6 is anisotropically etched using, for example, CHF3 gas using the photoresist 10 as a mask, a SiO2 film 6' remains on the side surface of the gate electrode 4. (Figure 2 (C)
) Further, a metal wiring layer 8 made of, for example, an A2 alloy is formed to complete the process.

(FIG. 2(d)) As described above, according to this embodiment, the gate electrode 4 and the metal wiring layer 8 in the contact hole 7 are connected to the S z O2 film 9 formed on the gate electrode 4 and the interlayer insulation. S as membrane 6
The contact hole 7 is insulated by the residual 5102 film e' on the side surface of the gate electrode 4 produced by anisotropic etching of the iO2 film, and is formed in a self-aligned manner with the gate electrode 4.

In this embodiment, the insulating film 9 on the gate electrode 4 and the interlayer insulating film 6 are made of S102 film by CVD method, but they may also be made of insulating films such as S102 film or 513N4 film by other forming methods. You may use them together.

Effects of the Invention As described above, the present invention forms an insulating film on the gate electrode in advance, and forms a contact hole by anisotropically etching the interlayer insulating film deposited on the insulating film, thereby making the gate electrode self-contained. Since contact can be formed between the source/drain region and the metal wiring layer in a consistent manner, the area of the source/drain region can be reduced, and a high-density semiconductor device can be designed. Furthermore, since the distance between the contact hole and the channel portion under the gate electrode is reduced, the resistance component of the source/drain region that exists between them can be reduced, making it possible to manufacture high-performance semiconductor devices. This makes it possible to manufacture an excellent semiconductor device that also has the advantage of being possible.

Figure 1 is a cross-sectional view of a conventional MIS transistor; Figure 2 is a cross-sectional view of a conventional MIS transistor;
a) to (d) are cross-sectional views showing the manufacturing process of a MIS transistor according to an embodiment of the present invention.

1... Semiconductor substrate, 4... Gate electrode, 5...
... source/drain region, 6... interlayer insulating film,
7...Contact hole, 9...Insulating film.

Name of agent: Patent attorney Toshio Nakao and 1 other person C’2　　　　　　　　dr (Q knee 1. /

Claims (1)

[Claims] An interlayer insulating film made of the insulating film material or another insulating film material is deposited on the entire surface of the semiconductor substrate whose upper surface of the gate electrode is covered with an insulating film, and partially overlaps with the gate electrode when viewed from the upper surface of the semiconductor substrate. A method of manufacturing a semiconductor device, characterized in that a contact hole is formed by anisotropic etching of the interlayer insulating film.