JPH0527412A - Device for verifying mask pattern of integrated circuit - Google Patents

Abstract

PURPOSE:To verify the mask patterns partially varying in geometrical design rules with high accuracy in a short period of time. CONSTITUTION:The respective verification results of a partial design rule verifying means 7, a region assigning design rule verifying means 8, and a design rule verifying means 10 are edited by a verification error editing means 15 and are outputted by a verification result outputting means 18. The mask pattern verification is executed for each of the mask patterns in correspondence to the respective different design rules by such constitution, by which the verification results are outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit mask pattern verification device for verifying the geometrical design of a mask pattern such as LSI (Large Scale Integrated Circuit).

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing the structure of a conventional integrated circuit mask pattern verification device. 2 is a mask pattern data reading means for reading the mask pattern data 1 of the integrated circuit to be verified, and 10 is a geometrical design in which the mask pattern indicated by the mask pattern data read by the mask pattern data reading means 2 is manually described Design rule verification means for verifying whether rule 9 is violated, 11 is design rule verification means 1
Design rule verification result by 0, 18 is a verification result output means for performing graphic display 16 and list output 17 of the design rule verification result 11.

Next, the operation of this conventional example will be described with reference to the flowchart of FIG. First, the mask pattern data 1 is read by the mask pattern data reading means 2 (step S11). Next, the mask pattern violating the geometrical design rule 9 described by hand or the like is verified by the design rule verification means 10 (step S12), and the design rule verification result 11 is created. Thereafter, the design rule verification result 11 is displayed by the verification result output means 18 as a graphic display 16 and a list output 1.
7 is performed (step S13). Such a design rule verification result 11 includes the error content when the corresponding mask pattern violates the geometric design rule 9, and the error content is notified to the user as a graphic display 16 and a list output 17. Will be.

[0004]

However, in the case of verifying a mask pattern having partially different geometric design rules, the conventional integrated circuit mask pattern verifying apparatus as described above is designed as shown in FIG. 6 for each design rule. There is a problem that it is necessary to repeat the processing of the flowcharts to execute the verification of the mask pattern, and many pseudo errors may occur.

The present invention has been made in order to solve the above problems, and extracts design rules partially added to mask patterns having different geometric design rules to deal with different design rules. It is an object of the present invention to provide an integrated circuit mask pattern verification device capable of verifying a mask pattern for each mask pattern.

[0006]

An integrated circuit mask pattern verification apparatus according to the present invention is a design rule for extracting a geometric design rule 5 added to a mask pattern data 1 read by a mask pattern data reading means 2. The extracting means 3, the area design rule extracting means 4 for extracting the design rule 6 of the specified mask pattern among the mask pattern areas to which the added geometric design rule 5 is different, and the design rule extracting means 3 Partial design rule verification means 7 for carrying out partial verification of the geometrical design rule 5 extracted in step 4, and area design rule verification means for verifying the area design rule 6 extracted by the area design rule extraction means 4. 8 and the verification result 11 of the design rule verification verification means 10 and the above Edit each error content of the verification result 13 of the verification result 12 and the area designation design rule check means 8 minute design rule verification unit 7 gives the edits to the verification result output unit 18 validation error editing means 15
It is equipped with and.

[0007]

The design rule extracting means 3 extracts the geometric design rule 5 of the mask pattern data 1, and the area design rule extracting means 4 extracts the geometric design rule 5.
The design rule 6 of the specified mask pattern is extracted from the mask pattern areas having different values. The partial design rule verification means 7 performs a partial verification of the geometric design rule 5 extracted by the design rule extraction means 3, and the area designation design rule verification means 8 verifies the area designation design rule 6. The verification error editing means 15 edits each error content of the verification result 11 of the design rule verification means 10, the verification result 12 of the partial design verification means 7 and the verification result 13 of the area design rule verification means 8 and verifies the edited content. It is given to the output means 18. Thus, the mask pattern verification is performed for each mask pattern corresponding to each different geometric design rule, and the verification result is edited and output.

[0008]

1 is a block diagram showing the configuration of an integrated circuit mask pattern verification apparatus according to an embodiment of the present invention.
In FIG. 1, 2 is a mask pattern data reading means for reading the mask pattern data 1 of the integrated circuit to be verified, 3 is a design rule extracting means for automatically extracting the geometrical design rule 5 added to the mask pattern data 1, 4 is the geometrical design rule 5 added above
Area design rule extracting means for extracting the design rule 6 of the specified mask pattern and the design rule file name of the mask pattern areas different from each other, and the geometric design rule 5 extracted by the design rule extracting means 3. Partial design rule verification means for carrying out partial verification of 8 and area designation design rule extraction means 4
The area designation design rule verification means for verifying the area design rule 6 extracted in step 10 is a design rule verification means for verifying the mask pattern of the mask pattern data 1 according to the geometric design rule 9 described manually. Reference numeral 11 is a design rule verification result by the design rule verification means 10, 12 is a design rule verification result by the partial design rule verification means 7, 13 is a design rule verification result by the area designation design rule verification means 8, 15 is a design rule verification result 11, 12, 1
A verification error editing means for editing the error content 3 and creating the error data 14, and a verification result outputting means 18 for displaying the error data 14 graphically 16 and outputting a list 17.

Next, the operation of this embodiment will be described with reference to the flow chart of FIG. First, the mask pattern data 1 is read by the mask pattern data reading means 2 (step S1). Next, the geometric rule added to the mask pattern as shown in FIG. 3 is extracted by the design rule extracting means 3 (step S2).
The design rule 5 of the extraction result also includes the coordinate value of the corresponding mask pattern. Next, as shown in FIG. 4, the area design data (coordinate value) and the design rule name, which are the information of the geometric design rule added to the mask pattern, are extracted by the area design rule extracting means 4 (step S3). That is, the design rule 6 of the specified mask pattern in the mask pattern areas having different geometric design rules is extracted. After that, the design rule verification means 10 verifies the design rule of the mask pattern data 1 according to the design rule 9 described and created by a human or the like to create the design rule verification result 11 (step S4). Next, the partial design rule verification means 7 performs the partial design rule verification according to the design rule 5 of the extraction result, and the design rule verification result 12
Is created (step S5). Next, the area designation design rule verification means 8 performs the design rule verification of the mask pattern in which the area is designated by the design rule 6, and creates the verification result 13 (step S6). Next, the design rule verification results 11, 12, and 13 are used as verification error editing means 1
5 inputs and edits the verification error content (step S
7). Thereafter, the edited verification error content is displayed graphically 16 and list output 17 by the verification result output means 18 (step S8).

In the above embodiment, the partial design rule verification means 7 and the area designation design rule verification means 8 are provided separately, but these means are used.
It may be provided in 0.

[0011]

As described above, according to the present invention, the geometrical design rule added to the mask pattern data is extracted, the mask pattern is verified for each mask pattern corresponding to each design rule, and the verification result is obtained. Since the error contents of are edited and displayed graphically and output as a list, if the design rules of the mask pattern are partially different, mask pattern verification can be performed for each mask pattern corresponding to different design rules.
As a result, it is not necessary to change the design rule for the same mask pattern and perform verification multiple times, and it is unnecessary to identify pseudo errors. Therefore, it is possible to shorten the mask pattern verification period and improve accuracy. can get.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an integrated circuit mask pattern verification device according to an embodiment of the present invention.

FIG. 2 is a flowchart showing the operation of this embodiment.

FIG. 3 is a diagram for explaining an example of a design rule added to a mask pattern in this embodiment.

FIG. 4 is a diagram for explaining an example of a design rule for designating a region added to a mask pattern in this embodiment.

FIG. 5 is a block diagram showing a configuration of a conventional integrated circuit mask pattern verification device.

FIG. 6 is a flowchart showing the operation of this conventional example.

[Explanation of symbols]

 2 mask pattern data reading means 3 design rule extracting means 4 area design rule extracting means 7 partial design rule verifying means 8 area design design rule verifying means 10 design rule verifying means 15 verification error editing means 18 verification result outputting means

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI technical display location H01L 21/66 J 7013-4M

Claims (1)

Claims: 1. A mask pattern data reading means for reading mask pattern data of an integrated circuit to be verified,
A design rule verification means for verifying whether or not the mask pattern of the read mask pattern data violates a geometric design rule described by hand, and a verification result output means for outputting the verification result are provided. In the integrated circuit mask pattern verification device, the design rule extracting means for extracting the geometric design rule added to the mask pattern data read by the mask pattern data reading means is different from the added geometric design rule. Area design rule extracting means for extracting design rules of a specified mask pattern in the mask pattern area, and partial design rule verifying means for partially verifying the geometric design rules extracted by the design rule extracting means. , Designated area above Area design rule verification means for verifying the area design rule extracted by the extraction means, verification result of the design rule verification means, verification result of the partial design verification means, and verification result of the area design rule verification means And a verification error editing means for editing each error content and applying the edited content to the verification result output means.