JPH0950457A - Layout vertification rule generator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a layout verification rule generator capable of easily preparing highly reliable layout verification rules. SOLUTION: In this device for generating layout verification rule for verifying whether or not the layout pattern is prepared in a prescribed layout pattern in the process of semiconductor manufacture, a layout verification rule generation means 3 for generating the layout verification rule with the model 1 of the layout verification rule prepared beforehand and a check value table 4 for describing variable for the verification item of a design rule and check value as input is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to layout verification performed when designing a layout pattern of an LSI.

[0002]

2. Description of the Related Art In a layout verification apparatus for verifying whether or not each process is created in a layout pattern according to a design manual in a manufacturing process of an LSI, a layout verification rule serving as a judgment standard is conventionally created manually. . Therefore, when creating a layout verification rule, it is necessary to check the reliability of the rule itself in all items of the design manual, which is very troublesome.

[0003]

SUMMARY OF THE INVENTION A layout verification rule generation device according to the present invention aims to easily create a highly reliable layout verification rule in order to solve the above problems.

A first aspect of the present invention is to obtain a layout verification rule generation device which can easily create a highly reliable layout verification rule.

A second aspect of the present invention is to obtain a layout verification rule generating apparatus which can easily create a more reliable layout verification rule.

[0006]

Means for Solving the Problems In the first invention,
A layout verification rule template prepared in advance to generate a layout verification rule for verifying whether or not the layout pattern is created in a predetermined layout pattern in the semiconductor manufacturing process, and verification items of the design rule. A layout verification rule generating means for generating a layout verification rule is provided by using as input a variable and a check value table describing check values.

In the second aspect of the invention, the layout pattern is a predetermined layout pattern in the process of the semiconductor manufacturing process by using the template of the layout verification rule and the check value table in which variables and check values for the verification items of the design rule are described. In order to generate the layout verification rule for verifying whether or not it is created in, the verification item library in which the verification rule of each verification item is registered and which verification item A layout verification rule template generating means for inputting a select table designating whether to select is provided.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a functional block diagram showing the configuration of an embodiment of the present invention. The layout verification rule template 1 prepared in advance and the check value table 4 in which variables and check values for verification items of the design rule are described are input to the layout verification rule generating means 3. The layout verification rule generating means 3 replaces the variable portion of the template 1 of the layout verification rule with the check value in the check value table 4 to generate the layout verification rule 6. As a criterion for determining the reliability of the generated layout verification rule 6, the layout verification device 8 verifies whether or not the layout pattern 5 is created according to the design manual of the corresponding process, and displays the result in the verification result list 9. Output. The error content is displayed on the CRT 7.

FIG. 2 shows an example of the layout verification rule 6 generated by the layout verification rule generation means 3 in the layout verification rule generation device 2 of the present invention. FIG. 3 is an example of template 1 of the layout verification rule prepared in advance. The difference is that the variable "NSNFSP" in FIG. 3 is replaced by the check value "1.0" in FIG. 2 by the layout verification rule generating means.

FIG. 4 shows the layout verification rule generating means 3
6 is a flowchart showing the operation of the first embodiment. First, read one line of template 1 of the layout verification rule (step S
1). Next, it is judged whether all the lines of the template 1 of the layout verification rule have been processed (step S
2) If the processing is performed, the process ends. If no processing has been performed, the check value table 4 is read (step S3) and compared with the line read in step S1 (step S4). Next, it is determined whether the variables match according to the compared contents (step S5), and if they match, the variables are converted into check values in the check value table 4 (step S6), and the layout verification rule 6 (Step S7). If they do not match, the line of step 1S is output as it is as the layout verification rule 6 (step S7).

As described above, according to the layout verification rule generation means 3 of the layout verification rule generation device 2, only the check value is replaced by using a template with a proven track record of the prepared layout verification rule. Since the layout verification rule is generated, a highly reliable rule can be obtained. Further, even if a new process is derived by shrinking from an existing process, there is an advantage that a layout verification rule can be easily created only by preparing a check value table.

Embodiment 2. In the first embodiment,
It is necessary to prepare template 1 for layout verification rules. When only the check values are different in the derived process and the verification items are almost the same, the preparation of the template 1 of the layout verification rule can be easily created from the layout verification rule 6 of the existing process. However, when creating template 1 of the layout verification rule for a completely new process,
Since the verification items and the processing contents thereof are not the same as those of the existing process, it is necessary to combine the necessary verification items with each other, and it takes time to create the rule. Therefore, the layout verification rule template generation means 12 for creating the layout verification rule template 1 from the verification item library 10 is added.

FIG. 5 is a functional block diagram showing the configuration of the second embodiment. A verification item library 10 which is a library of template verification rules divided into each verification item;
The select table 11 describing which verification item to select is input to the layout verification rule template generation means 12 of the layout verification rule generation device 2. The layout verification rule template generation unit 12 searches the verification item library 10 for the verification rule of the verification item designated by the select table 11, pastes it into the layout verification rule template 1, and then the layout verification rule template 1 To generate. The subsequent operation is the same as the operation of the layout verification rule creating means in the first embodiment.

FIG. 6 is a flowchart showing the operation of the layout verification rule template generating means. First, one designated verification item is read from the select table 11 (step S8). Next, it is determined whether or not all the verification items designated in the select table 11 have been processed (step S9), and if the processing has been completed, the process ends. When the processing is not performed, the verification item library 10 is read, the verification rule of the specified verification item is searched (step S10), the found verification rule is pasted, and the template 1 of the layout verification rule is output.

As described above, according to the layout verification rule template generation means 12 of the layout verification rule generation device 2, the layout verification rule template 1 of a completely new process can be easily created. Also, regarding the reliability of the verification rule itself, since it is sufficient to confirm the operation of the rule only for the verification rule of the newly created verification item, a highly reliable layout verification rule can be created in a short period of time.

[Brief description of drawings]

FIG. 1 is a block diagram of a layout verification rule generation device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an example of a layout verification rule generated by the layout verification rule generation device according to the first embodiment of the present invention.

FIG. 3 is a diagram showing an example of a template of a layout verification rule input by the layout verification rule generation device according to the first embodiment of the present invention.

FIG. 4 is a flowchart showing the operation of the layout verification rule generating means of the layout verification rule generating device according to the first embodiment of the present invention.

FIG. 5 is a block diagram of a layout verification rule generation device according to a second embodiment of the present invention.

FIG. 6 is a flowchart showing the operation of the layout verification rule template generation unit of the layout verification rule generation device according to the second embodiment of the present invention.

[Explanation of symbols]

1 layout verification rule template, 2 layout verification rule generation device, 3 layout verification rule generation means,
4 Check value table, 5 Layout pattern, 6
Layout verification rules 6, 7 CRT, 8 layout verification device, 9 verification result list, 10 verification item library, 11 select table, 12 layout verification rule template generation means.

Claims (2)

[Claims] 1. A layout verification rule template prepared in advance for generating a layout verification rule for verifying whether or not the layout pattern is created in a predetermined layout pattern in a semiconductor manufacturing process. A layout verification rule generating device comprising a layout verification rule generating means for generating a layout verification rule by inputting a check value table in which variables and check values for verification items of a design rule are described. 2. A layout pattern is created in a predetermined layout pattern in a semiconductor manufacturing process by using a layout verification rule template and a check value table in which variables and check values for verification items of a design rule are described. In generating the layout verification rule for verifying whether or not to verify, the verification item library in which the verification rule of each verification item is registered and which verification item to select are used as a means to generate the template of the layout verification rule. A layout verification rule generation device, characterized in that a layout verification rule template generating means for inputting a select table to be designated is provided.