JPH0499354A - Apparatus for designing integrated circuit - Google Patents

Abstract

PURPOSE:To facilitate design of multiple-pin LSI by giving pad names to external pins in circuit layout data to eliminate the addition of text (pad name) before layout verification preceded by layout design. CONSTITUTION:Means 1 prepares circuit diagram data, and the means 1 includes means 1a for naming pads corresponding to individual pins. The data with pad names are supplied to wiring/layout means 2 and layout verifier means 4. In the means 2, the data is processed after pad names are removed by means 2a. Then, the pins are made to correspond to the pad names, and the data verification is performed. Finally, data output means 5 produces an output for preparation of mask data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is utilized for an integrated circuit design device, and particularly relates to an integrated circuit design device that improves an integrated circuit layout design method.

〔overview〕

The present invention provides an integrated circuit design apparatus having means for creating circuit diagram data from integrated circuit design information and creating layout data from this circuit diagram data. given name(
By adding a number), it is possible to automate the correspondence between external terminal names and pads during layout verification or back annotation of wiring delay amount, making the process easier and more accurate.

[Conventional technology]

A conventional integrated circuit design apparatus that performs layout design performs placement and wiring using connection information from a circuit diagram as input.

Even after wiring, many modifications were made to improve characteristics.

For these processes, an automatic layout means is provided, and the layout is verified before outputting the mask data.

FIG. 5 is a block diagram showing the main parts of such a conventional integrated circuit design apparatus.

This conventional example includes a circuit diagram creation unit 11 that creates circuit diagram information based on design information, a placement and wiring unit 12 that performs layout placement and wiring based on the created circuit diagram information, and verification of the created layout data. It includes a layout verification means 14, a data output means 15 that converts and outputs layout data into mask data, and a control means 16 that performs overall control. Then, the layout verification means 14
includes text adding means 14a for adding text to the layout data each time according to the bin name of the circuit diagram data.

Next, the operation of this conventional example will be explained with reference to the flowchart shown in FIG.

First, circuit diagram data is created by the circuit diagram creation means 11 (step 511). Next, the placement and wiring means 12 performs placement, wiring, and modification of the layout to obtain a layout diagram, and the layout creation means 13 edits the layout data to generate layout data (steps 312 and 513). Next, the layout verification means 14 checks the layout data for the seventh
As shown in the figure, each time the band salt is manually added to text according to the pin name of the circuit diagram data and the layout data is verified (steps 514, S15 and 516).
).

If the determination result is a failure, the process returns to step S12 and the process is repeated; if the determination result is a failure, the data output means 1
5, it is converted into mask data and output (step 51).
7). In this way, placement and routing are repeated many times in order to optimize the layout. In some cases, the design is performed manually within a block, and the wiring between blocks is designed using automatic layout means. As described above, since a part of the design process involves manual design, layout verification is essential in layout design.

[Problem to be solved by the invention]

As explained above, in the conventional integrated circuit design apparatus, the layout data after automatic placement and routing cannot be directly input as input data to the layout verification means 14, so the means 14a adds text to the layout data every time. I manually added text to match the pin names in the circuit diagram data. This is because the data structure is different between the automatic layout means and the layout verification means. For example, there is a difference between independent text and dependent text, when internal text from the automatic layout means is output, or when the meaning of text expression is different.

Therefore, it is necessary to manually add text for at least the number of pads before layout verification. LSIs with a large number of pins have the drawbacks of requiring a large amount of man-hours to add text and significantly reducing the convergence of layout verification results due to careless mistakes in adding text.

The correspondence between this external terminal name and band salt is handled as follows.
In addition to the above-mentioned layout verification, back annotation of wiring delay amount is also a problem.

SUMMARY OF THE INVENTION An object of the present invention is to provide an integrated circuit design apparatus that can easily and accurately perform layout verification, for example, by eliminating the above-mentioned drawbacks.

[Means to solve the problem]

The present invention provides circuit diagram creation means for creating circuit diagram data based on design information, layout and wiring means for arranging and wiring a layout based on the created circuit diagram information, layout creation means for editing and creating layout data, and In the integrated circuit design apparatus, the circuit diagram creation means includes pad salts on the layout in addition to external terminal names as external terminal name information in the schematic information. The layout and wiring means includes pad name addition means for adding a pad name, and the placement and wiring means includes pad name removal means for removing the added pad salt from the circuit diagram data input from the circuit diagram creation means. .

[Effect]

The circuit diagram creating means adds a pad salt (often designated by a number) on the circuit diagram data to an external terminal name on the circuit diagram data using a pad name adding means.

Then, the placement and wiring means removes the added pad salt using the pad name removal means, performs processing, and creates layout data. In the case of layout verification, the layout verification means verifies the layout data based on the circuit diagram data to which the pad salt is added, which is input from the circuit diagram creation means.

Therefore, text addition, which was conventionally performed by the layout verification means, is no longer necessary, and it is simplified and can be automated instead of being done manually, making it possible to eliminate careless mistakes and improve accuracy.

Note that the above-described process of corresponding the external terminal name in the circuit diagram data and the pad salt on the layout data can be similarly easily and accurately performed in the case of back annotation of the amount of wiring delay, for example.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the main parts of a first embodiment of the present invention.

The bookcase embodiment includes a circuit diagram creation means 1 for creating circuit diagram data based on design information, a layout and wiring means 2 for arranging a layout and wiring based on the created circuit diagram data,
Layout creation means 3 for editing and creating layout data
In an integrated circuit design apparatus comprising: a layout verification means 4 for verifying created layout data; a data output means 5 for converting the layout data into mask data; and a control means 6 for overall control. , the circuit diagram creation means 1, which is a feature of the present invention, includes a pad name addition means 1a that adds a pad salt on the layout in addition to the external terminal name as external terminal name information in the circuit diagram information, and Means 2 is
It includes a pad name removing means 2a for removing the added pad salt from the circuit diagram data inputted from the circuit diagram creating means 1.

Next, the operation of the bookcase embodiment will be explained with reference to the flowchart shown in FIG. 2 and the applied circuit diagram example shown in FIG.

First, circuit diagram data is created by circuit diagram creation means 1,
The pad name adding means 1a adds a pad name (in this case, a number) on the layout to the pin name to the created circuit diagram data (step Sl). An example is shown in FIG.

In FIG. 3, CK;1 is written as a CK1 pad name (pad number) with 1 after a semicolon. This means that the external terminal name of CK on the circuit diagram corresponds to the No. 1 pad on the layout. Similarly, external terminals CKBSTl and T2 are connected to numbers 2 and 3.
2 and 3, meaning they correspond to pads numbered and numbered four.
and a pad salt (number) of 4 is added. Adding pad salt to this circuit diagram data can be easily done because the pin numbers are known in advance.

The circuit diagram data to which this pad salt has been added is input to the placement and wiring means 2 and the layout verification means 4. but,
Since the layout and wiring means 2 cannot process the circuit diagram data to which this pad salt is added, the added pad salt is removed by the pad name removing means 2a (step S2).

After that, similar to the conventional example described above, layout processing is performed and layout data is generated (steps S3 and S4).
.

Next, the layout data generated by the layout verification means 4 is verified (steps 85 to S7).

At this time, the input data is circuit diagram data to which a pad salt has been added, and this pad salt is extracted (step S5), and made to correspond to the bat name (number) of the extracted layout data while referring to the bottle salt.

As an example of this pad name extraction method (corresponding method), by specifying only the pad position corresponding to pin 1 from the outside and searching counterclockwise for only the pad layer, the pad salt can be matched. can. Pad data is rectangular and has a small amount of data, so it can be easily processed.

After associating bottle salt and pad salt in this way,
Verification processing similar to the conventional method is performed (steps S6 and S7), and mask data is created and outputted by the data output means 5 (step 38).

FIG. 4 is a block configuration diagram showing the main part of the second embodiment of the present invention, and the present invention is useful when extracting wiring delay values from layout data after placement and routing and adding annotations thereof to the original data. It was applied.

According to FIG. 4, in the second embodiment, the pad name adding means 1
circuit diagram creation means 1 including pad name removal means 2a, layout creation means 3, data output means 5, control means 6, and annotation means for back-annotating wiring delay values. 7.

In the second embodiment, the annotation means 7 extracts the delay value of the wiring from the layout data after placement and wiring, and inputs it to the circuit diagram creation means 1. The circuit diagram creating means 1 can easily annotate delay values on the circuit diagram data by associating the pad salts of the layout data with the external terminal names of the circuit diagram data.

As described above, the present invention is effective as an application tool for inputting or outputting both circuit diagram data and layout data.

〔Effect of the invention〕

As explained above, the present invention adds text (number) on the layout to the external terminal name of the circuit diagram data as a preprocessing for layout verification processing after layout design. pad salt)
is no longer needed. This has the effect of reducing the amount of man-hours required to add text each time layout data is revised, which is generally done many times. Furthermore, since the recognized pad salt (bottle salt) information is accurate since no manual is involved, careless mistakes regarding bottle salt are eliminated and the convergence of layout verification results is significantly improved.

Therefore, according to the present invention, it is possible to easily and accurately design a multi-pin LSI, and the effects thereof are significant.

FIG. 7 is a diagram showing an example of the circuit diagram data.

1.11... Circuit diagram creation means, 1a... Pad name addition means, 2.12... Placement and wiring means, 2a... Pad name removal means, 3.13... Layout creation means, 4
．． 14...Layout verification means, 5.15...Data output means, 6.16...Control means, 7...Annotation means, 14a...Text attachment means, 31-S8, Sl
l-S17...Step.

Claims (1)

[Claims] 1. Circuit diagram creation means for creating circuit diagram data based on design information; Placement and wiring means for arranging and wiring a layout based on the created circuit diagram information; Layout creation for editing and creating layout data. and a layout verification means for verifying the created layout data, wherein the circuit diagram creation means includes information on layout data in addition to external terminal names as external terminal name information in the circuit diagram information. pad name adding means for adding a pad name, the placement and routing means:
An integrated circuit designing apparatus comprising: a pad name removing means for removing the added pad name from the circuit diagram data input from the circuit diagram creating means.