JP2583631B2 - Circuit model generation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is to execute a CAD tool for performing layout data of a cell used as a part of a semiconductor integrated circuit, logic verification, timing verification, test generation, and the like. And a circuit model generation method for generating a circuit model which is the data of (1).

[Conventional technology]

FIG. 4 is a flowchart illustrating the operation of a circuit model generation method for generating layout data and a circuit model in a conventional cell generation system.

Next, the operation of the circuit model generating method will be described. First, a parameter value indicating a characteristic of a cell generated as a circuit model is read (step ST1), and cell layout data corresponding to the read parameter value is generated (step ST2). Then, connection information between the elements in the cell is extracted from the generated layout data (step ST3), and a circuit model of the cell is generated (step ST4). Note that the circuit model of the cell generated as described above is input data of a CAD tool for verifying an actual circuit as a whole.

[Problems to be solved by the invention]

Since the conventional circuit model generation method is configured as described above, connection information data representing a connection relationship between elements constituting a cell can be generated as a circuit model, but a functional expression representing a function or operation of the cell. There is a problem that data cannot be generated, and logic verification at a function level using function expression data that can be performed at higher speed than logic verification using connection information data cannot be performed. Also, since a circuit model cannot be generated until after layout data is generated, layout data must be generated once even when a circuit is to be verified before generating layout data. It took a long time.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and a cell generation method for generating a circuit model of connection information data or function expression data independently of generation of layout data, using a circuit model of a cell. An object of the present invention is to obtain a method for generating a circuit model in a system.

[Means for solving the problem]

A circuit model generation method according to the present invention includes a symbol that is replaced with a parameter value itself indicating a characteristic of the cell, a symbol that specifies the number of repetitions for generating a predetermined expression by the parameter value, and Connection information data and function expression data as data for generating a circuit model including an undetermined element portion composed of a symbol that does not depend on the expression form of the circuit model of a symbol that can be selected from a plurality of expression candidates by parameter values. Prepared in advance, of the circuit model generation data, the connection information data instructed from outside, or the undefined element portion and the undetermined element portion of the function expression data are separated, and the parameter in which the undetermined element portion is read Replacement processing for replacing with the value itself, generating a predetermined expression the number of times the parameter value is specified Repeat the process, or among a plurality of expressions prepared in advance, edited by performing a selection process to sift the instructed represented by the parameter values,
The circuit model of the cell corresponding to the read parameter value is generated.

(Operation)

The circuit model generation data in the present invention is independent of generation of connection information data described in an expression format that can be identified as an undetermined element portion in a circuit model, and layout data read and prepared as function expression data. A circuit model of a cell can be generated by editing an undetermined element portion in any of the connection information data and the function expression data.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a hardware configuration diagram for realizing a circuit model generation method according to one embodiment of the present invention. In the figure, reference numeral 1 denotes a circuit model generation data storage unit that stores connection information data and function expression data; Reference numeral 2 denotes a parameter value storage unit for temporarily storing the read parameter values, and 3 denotes a circuit model generation unit. Connection information data, which is the circuit model generation data, or an undetermined element portion and an undetermined element portion of the function expression data. From the parameter value storage means 2 to extract necessary parameter values for specifying the undetermined element portion separated by the analysis means 3a, and from the analysis means 3a. Substitution processing is performed from the obtained undetermined element part and the undetermined element part, and the parameter value obtained from the necessary parameter value extracting means 3b. Editing processing means 3c for performing processing, repetition processing, selection processing and editing. Reference numeral 4 denotes circuit model storage means for storing the circuit model of the cell generated by the circuit model generation means 3.

FIG. 3 is a diagram showing an example of data stored or generated in the configuration shown in FIG. 1. In this embodiment, a case where a circuit model of a multiplier cell is generated is shown. FIG. 2A shows a part of the function expression data stored in the circuit model generation data storage means 1. In the figure, "_MPYNAME" on the first line indicates a cell name designated by the user and Symbols to be replaced “_XNUM” on the second line and “_Y” on the third line
"NUM" is a symbol to be replaced with a numerical value specified by the user (e.g., corresponding to the number of bits of a multiplier and a multiplicand in the case of a multiplier cell), "_XIN [i]" on the second line and "_YIN" on the third line
"[I]" is a symbol to be replaced with the input terminal name set by the user. "_IL" on the fourth line is a flag for specifying the value 1 when the user does not specify the value 1 when attaching the input latch. In the second line, “_ # 1oop (i = _XNUM; i>
= 1; -1) # [...] # "decreases the value of" i "by 1 from the value of" _XNUM "to 1 while"#[","]
A symbol that repeats the description in “#”, “_ # if (...) on the fourth line
# [...] # "is"#"when the value in"(",")"is 1.
This symbol is used to select the description (expression) in [","] # ". Further, FIG. 2B is a diagram for editing the function expression data which is read and temporarily stored in the parameter value storage means 2. FIG. 4C shows a part of a parameter value, FIG. 4C shows a part of a circuit model edited by the cell generation system, and FIG. 5D is stored in the circuit model generation data storage means 1. FIG. 4E shows a part of the connection information data, and FIG. 4E shows a part of the parameter value for editing the connection information data which is read and temporarily stored in the parameter value storage means 2. (f) is a diagram showing a part of the circuit model edited by the circuit model generation method.

Next, the operation of the cell generation system will be described with reference to the flowchart of FIG. First, parameter values such as the cell name, the number of bits of the multiplier and the multiplicand, the input terminal name, the value of the flag, and the like set by the user from the outside are read and stored in the parameter value storage means 2 (step ST).
Five). Further, it is determined whether the user's instruction is to generate layout data or a circuit model (step ST).
6) If layout data generation is instructed, layout data of the instructed cell is generated (step ST
16), the editing is ended. When the circuit model generation is instructed in step ST6, first, it is determined which of the function expression data and the connection information data has been instructed as the circuit model generation data (step ST7). Function expression data from the circuit model generation data storage means 1 (FIG. 3A)
(Step ST8a) or connection information data (FIG. 3 (d)) (step ST8b). Then, the extracted circuit model generation data is divided into an undetermined element part and an undetermined element part by the analysis means 3a (step ST9), and each of the divided parts is determined one by one.
It is determined whether or not each element is an undetermined element (steps ST10 and ST1).
1) If it is an undetermined element portion, first, the necessary parameter value extraction means 3b indicates the parameter value (if the function expression data is specified as the circuit model generation data, the connection information data is specified in FIG. 3B). If it is done, it is extracted (shown in FIG. 3 (e)) (step ST12),
Editing by the parameter value is performed by the editing processing means 3c (step ST13), and when it is confirmed that the processing has been completed for all portions cut by the analysis means 3a (step ST13)
14), a circuit model of the cell is generated by editing the undetermined element portion and the undetermined element portion replaced with the parameter values (step ST15). The circuit model of the cell generated as described above verifies the actual circuit as a whole.
It becomes the input data of the CAD tool.

〔The invention's effect〕

As described above, according to the present invention, the function expression data and the connection information data including the undetermined element portion depending on the parameter value read as the circuit model generation data are prepared in advance, and the Since the circuit model of the cell is generated by editing, it is possible to obtain a circuit model generation method capable of generating a circuit model using either the function expression data or the connection information data independently of the generation of the layout data. is there.

[Brief description of the drawings]

FIG. 1 is a hardware configuration diagram for realizing a circuit model generating method according to one embodiment of the present invention, FIG. 2 is a flowchart for explaining the operation of the circuit model generating method of the present invention, and FIG. 3 is a circuit model of the present invention. FIG. 4 shows an example of data stored or generated by the generation method, and FIG. 4 is a flowchart for explaining the operation of the conventional circuit model generation method. In the figure, reference numeral 1 denotes a circuit model generation data storage unit;
Is a parameter value storage means, 3 is a circuit model generation means, 3a
Is an analyzing means, 3b is a necessary parameter value extracting means, 3c is an editing processing means, and 4 is a circuit model storing means. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] A parameter value indicating characteristics of a cell used as a part of a semiconductor integrated circuit is read, and layout data of a cell having the characteristic read as the parameter value, and verification and test generation of the semiconductor integrated circuit are performed. Do
In a circuit model generation method for generating a circuit model that is data for executing a CAD tool, a portion of the circuit model that depends on a parameter to be read is determined by a symbol that does not depend on an expression form of the circuit model. Prepare circuit model generation data consisting of connection information data and function expression data described in an expression format that can be identified as an element part, and connect the connection information data that is the circuit model generation data or the undetermined element part in the function expression data. Performing the separation from the undetermined element portion according to an external instruction, and editing the separated undetermined element portion with the read parameter value, thereby generating a circuit model corresponding to the parameter value. Circuit model generation method.