JP2760212B2 - Scan path design method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CAD system,
In particular, the present invention relates to a scan path design method for automatically inserting a scan path description into a function description of a logic circuit.

[0002]

2. Description of the Related Art In a logic circuit, a scan path is conventionally provided for facilitating a test.

By the way, when designing a scan path,
Conventionally, a designer manually converts a function description of a logic circuit having no scan path description into a gate-level circuit description by using a method of manually describing a scan path description in a function description of the logic circuit or a CAD system, After that, a scan path connection is performed by designating the connection order of the scan paths.

[0004]

Among the above-mentioned prior arts, the former requires a designer to be conscious of a scan shift operation using a scan path in addition to the original operation of the circuit, so that the burden on the designer is increased. There is a problem that it takes. Further, since the design is performed manually, there is a risk that a circuit having a connection logic error, a circuit causing a malfunction when switching between the original operation and the scan operation, or the like may be designed.

The latter has a problem that a scan path cannot be inserted until the gate-level logic design of the entire logic circuit is completed, and the scan path is not reflected in the function description. There is also a problem that it is difficult for a designer to recognize this.

SUMMARY OF THE INVENTION An object of the present invention is to provide a scan path design method capable of inserting an error-free scan path description into a function description of a logic circuit without burdening a designer.

[0007]

In order to achieve the above object, the present invention analyzes a function description of a logic circuit in which a scan path description is not described, and includes a register name of a register described in the function description. A function description analyzing means for extracting register information; and a register name associated with each register name in the register information extracted by the function description analyzing means in accordance with a scan insertion specification for specifying a connection order of registers constituting a scan path. Register information editing means for adding information indicating a connection relationship with other registers of the register, and a register to which information indicating the connection relationship is added by the function description in which the scan path description is not described and the register information editing means Scan path description insertion means for inserting a scan path description into the function description based on the information. It is intended.

[0008]

The function description analyzing means extracts register information including the register name of the register described in the function description of the logic circuit in which the scan path description is not described.

The register information editing means adds information indicating a connection relationship between the register having the register name and another register in association with the register name in the register information extracted by the function description analyzing means in accordance with the scan insertion designation.

[0010] The scan path description inserting means inserts the scan path description into the function description in which the scan path description is not described based on the register information to which the information indicating the connection relationship with another register is added by the register information editing means. .

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, wherein a function description analyzing means 2 and a register information editing means 5 are provided.
, Scan path description insertion means 6 and logic synthesis means 8.

The function description analyzing means 2 parses the function description 1 in which the scan path description is not described and analyzes the function description 1.
And register information 3 including a clock name of a clock supplied to a register having the register name, a clock name supplied to a register having the register name, and information indicating an appearance order in the function description. The scan insertion designation 4 described therein is output. The scan insertion designation 4 may be inputted from a keyboard or the like without being described in the function description 1.

FIG. 2 is a diagram showing an example of the register information 3. As shown in the figure, each record of the register information 3 is composed of items of the order of appearance, register name, clock name, scan-in signal, and scan order in the function description.

Among the items, the items such as the order of appearance, the register name, and the clock name in the function description have already been set when output from the function description analysis means 2; The item value is added by the register information editing means 5. In the example of the register information 3 shown in FIG. 2, the order of appearance of the register names in the function description 1 is REG.
B, REGA (0: 4), REGX, REGC,..., And the register with the register name REGB has the clock name CL.
The clock of KX is the clock of the clock name CLKB in the register of the register name REGA (0: 4), and the clock name CLK is in the registers of the register names REGX and REGC.
This indicates that the clock A is supplied.

FIG. 3 is a diagram showing scan insertion designation 4 in all register insertion mode, FIG. 4 is a diagram showing scan insertion designation 4 in register name designation mode, and FIG. 5 is a diagram showing scan insertion designation 4 in clock name designation mode.

The scan insertion designation 4 in the all register insertion mode shown in FIG.
Instructs connection in the order of appearance.

The scan insertion specification 4 in the register name specification mode shown in FIG. 4 indicates that the registers in the function description 1 are connected in the order of the register names described in the scan insertion specification 4. In the example of FIG. 4, the registers in the function description 1 are defined as REGA (0: 4), REGC, REGB, R
EGX,... Are connected in this order.

The scan insertion specification 4 in the clock name specification mode shown in FIG. 5 indicates that the registers to which the clock is supplied are connected in the order of the clock names described therein. However, registers to which clocks with the same clock name are supplied are connected in the order of appearance in the function description 1. In the example shown in FIG. 5, first, the clock name CL
Function description 1 of the register to which the KA clock is supplied
Are connected in the order of appearance in the following, and clock names CLKB,
CLKX... Are supplied in order of appearance in the function description 1.

The register information editing means 5 adds a scan-in signal and a scan order item value to each record of the register information 3 in accordance with the scan insertion designation 4.

The scan path description insertion means 6 is a function description 1
A scan path description is added to the register description in the function description 1 based on the register information 3 to which the scan-in signal and the scan order have been added, and this is added to the function description with scan 7.
Output as

The logic synthesizing means 8 converts the function description with scan 7 into a circuit description 9 at the gate level.

FIG. 6 is a flowchart showing a processing example of the register information editing means 5, and FIG. 7 is a flowchart showing a processing example of the scan path description inserting means 6. The operation of the present embodiment will be described below with reference to the drawings. I do.

The function description analyzing means 2 analyzes the function description 1 for which the scan path is not designed, that is, the scan path description is not described, outputs the register information 3 and the scan insertion designation 4, and controls the register information editing. Pass to means 5.

When the control is passed to the register information editing means 5, as shown in the flowchart of FIG. 6, the scan insertion designation 4 is any of the all register insertion mode, the register name designation mode, and the clock name designation mode, ie, It is determined whether the scan insertion designation 4 is any of the formats shown in FIGS.
(Steps S61 and S62).

If it is determined that the mode is the all register insertion mode, the same item value as the appearance order in the function description in the same record is set to the scan order item of each record of the register information 3 shown in FIG. Then, the same item value as the register name in the next record is added to the item of the scan-in signal (step S63), and then control is passed to the scan path description inserting means 6.

Therefore, in the example of FIG. 2, the item values 1, 2, 3,... Are added to the items in the scan order of the records whose appearance order is 1, 2, 3,. Items have item values REG (0: 4), REGX, REGC,
... is added.

If it is determined that the mode is the record name designation mode, the records of the register information 3 shown in FIG. 2 are sorted in the order of the register names described in the scan insertion designation 4 (step S64). For example, when the scan insertion designation 4 is as shown in FIG. 4, each record of the register information 3 has the register name REGA (0: 4), R
Are sorted in the order of records having EGC, REGB, REGX,. If there is a record having a register name not described in the scan insertion specification 4 in the register information 3, the records are arranged in the order of appearance after the sorted records.

Thereafter, the register information editing means 5 stores the item values 1, 2, 3 in the scan order items of the first, second, third,..., N-th records of the sorted register information 3. , ..., n, the first, second,
,..., The (n−1) th record scan-in signal items are the second, third, fourth,.
Add the item value of the register name of the nth record
(Step S65). Here, the n-th record indicates the last record among the records having the register names described at the end of the scan insertion specification 4.

When the processing in step S65 is completed, the register information editing means 5 re-sorts the records of the register information 3 sorted in step S64 in the order of appearance in the function description (step S68). It is passed to the description insertion means 6.

If it is determined that the mode is the clock name designation mode, the records of the register information 3 shown in FIG. 2 are sorted in the order of the clock signal names described in the scan insertion designation 4 (step S66). . For example, when the scan insertion designation 4 is as shown in FIG. 5, each record of the register information 3 has clock names CLKA and CLK.
.. B, CLKX,... If there is a record having a clock name not described in the scan insertion designation 4 in the register information 3, those records are arranged in the order of appearance after the sorted records.

Thereafter, the register information editing means 5 stores the item values 1, 2, 3 in the scan order items of the first, second, third,..., N-th registers of the sourced register information 3. , ..., n, the first, second,
The item values of the register names of the second, third, fourth,..., Nth records are added to the items of the scan-in signal of the third,..., (N−1) th records ( Step S67). Here, the n-th record indicates the last record among the records having the clock name described at the end of the scan insertion designation 4.

When the processing in step S67 is completed, the register information editing means 5 re-sorts the records of the register information 3 sorted in step S66 in the order of appearance in the function description (step S67). It is passed to the description insertion means 6.

When the control is passed to the scan path description inserting means 6, the function description 1 is read as one sentence as shown in FIG.
(Step S71), it is determined whether or not the read one sentence is a register to be subjected to scan connection, that is, a register description corresponding to a register constituting a scan path (Step S71).
72). This judgment is based on one sentence read and register information 3
For example, when one sentence read is a register description and the record in the register information 3 having the register name described in the register description is set to the scan order. ,
It is determined that the register description corresponds to a register to be connected for scan connection.

Then, the determination result of step S72 is NO.
In the case of, the scan path description insertion means 6 outputs the read one sentence as the original image (step S73).

If the result of the determination in step S72 is YES
In the case of (1), the scan path description insertion means 6 adds the scan path description created based on the record in the register information 3 corresponding to the read register description to the read register description and outputs the result (step S74).

FIG. 8 shows the register description of the register having the register name REGX before the scan path description is added. The process of step S74 will be described below by taking as an example a case where this register description is read in step S71. Become like It should be noted that the register description in FIG. 8 indicates that when the master reset MRST is turned on, the register R
EGX value is set to “0” and master reset MRST is
In the case of the FF, when the clock CLKA rises, data is set in the register REGX, and otherwise, the content of the register REGX is held.

The register description shown in FIG.
Therefore, the scan path description inserting means 6 refers to the register information 3 shown in FIG.
The scan-in signal and the scan order in the record having the register name REGX are read.

Next, the scan path description insertion means 6 creates a scan path description indicating which register value is to be shifted to the register REGX during the scan operation based on the read scan-in signal. Now, for example, assuming that the scan insertion designation 4 is the all register insertion mode, the register name REGX of the register information 3 shown in FIG.
Since the scan-in signal in the record having the symbol "REGC" is REGC, the scan path description inserting means 6 creates a scan path description indicating that the value of the register REGC is to be registered in the register REGX.

Next, the scan path description inserting means 6 determines whether or not the scan order represents the first or last. If it is determined that the first or last does not represent the scan order, the previously created scan path description is added. It is added to the register description shown in FIG. If it is determined that it indicates the beginning or end, the scan path description insertion means 6 further stores the register RE.
A scan path description indicating that GX is connected to the scan-out terminal and the scan-in terminal is created, and added to the register description shown in FIG. 8 together with the previously created scan path description. In the case of this example, since the scan order in the record having the register name REGX of the register information 3 does not indicate the first or last, the scan path description inserting means 6 indicates that the value of the register REGC is to be shifted to the register REGX. Only the campus description will be added to the register information shown in FIG.

FIG. 9 shows a register description to which the scan path description has been added as described above. When the master reset MRST is turned on, the register RE is output.
Set the value of GX to “0” and set the scan mode control S
If the clock CLKA rises when the MC is ON, the value of the register REGC is shifted to the register REGX. If the clock CLKA rises when the scan mode control SMC is OFF, the data is set in the register REGX. Otherwise, Is the register REG
This indicates that the contents of X are retained.

The scan path description inserting means 6 determines in step S
When the processing of 73 or step S74 is completed, the next one sentence is read from the function description 1 (step S75), and it is determined whether or not all the sentences of the function description 1 have been read (step S76).

If it is determined that the data has been read, the control is passed to the logic synthesizing means 8. If it is determined that the data has not been read, the process returns to step S72.

By performing the above-described processing on all the sentences in the function description 1, the function description with scan 7 is created.

When the control is passed, the logic synthesizing means 8 converts the function description with scan 7 into a circuit description 9 at the gate level.

[0046]

As described above, according to the present invention, the function description analyzing means, the register information editing means and the scan path description inserting means are provided so that the scan path description can be automatically inserted into the function description of the logic circuit. Because it was
There is an effect that it is possible to insert an error-free scan path description into a function description of a logic circuit without putting a burden on a designer. Further, since the scan path description is inserted in the function description, there is an effect that the designer can easily recognize the contents of the scan path.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing an example of register information 3;

FIG. 3 is a diagram showing an example of a scan insertion designation 4;

FIG. 4 is a diagram showing another example of scan insertion designation 4;

FIG. 5 is a diagram showing another example of scan insertion designation 4;

FIG. 6 is a flowchart showing a processing example of a register information editing means 5;

FIG. 7 is a flowchart illustrating a processing example of a scan path description inserting unit 6;

FIG. 8 is a diagram illustrating an example of a function description before a scan path description is inserted.

FIG. 9 is a diagram illustrating an example of a function description after a scan path description has been inserted;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Function description 2 ... Function description analysis means 3 ... Register information 4 ... Scan insertion designation 5 ... Register information editing means 6 ... Scan path description insertion means 7 ... Function description with scan 8 ... Logic synthesis means 9 ... Gate level circuit description

Claims (3)

(57) [Claims] A function description analyzing unit that analyzes a function description of a logic circuit in which a scan path description is not described, and extracts register information including a register name of a register described in the function description; According to the scan insertion specification that specifies the connection order of the constituent registers, the function description analysis unit associates each register name in the register information extracted by the function description analysis unit with information indicating a connection relationship between the register having the register name and another register. A register information editing unit to be added; and a scan path description inserted into the function description based on the function description in which the scan path description is not described and the register information to which information indicating a connection relationship is added by the register information editing unit. And a scan path description inserting unit. 2. The scan path according to claim 1, wherein the scan insertion designation designates connection of registers in the order of appearance in the function description or connection of registers in the order of the designated register name. Design method. 3. The method according to claim 1, wherein the register information includes a clock name of a clock supplied to the register, and the scan insertion specification specifies connection of the register in the order of the specified clock name. Scan path design method.