JP2004055901A - Lay out method of semiconductor integrated circuit device and lay out apparatus used for it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce iteration and improve reliability in an automatic lay out method of a semiconductor integrated circuit device including an analog circuit. <P>SOLUTION: Lay out design satisfying analog constraints can be realized in advance by fetching analog constraints in automatic lay out design by replacing the analog constraints with data which can be fetched in lay out environment in a floor plan step on an LSI. Iteration caused by visual recognition by an operator and recognition mistake is reduced by executing recognition to constraints by constraints decision processing, and a development period is thereby reduced. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a layout method for a digital-analog mixed integrated circuit device and a layout device used for the method, and more particularly to a high-speed layout design including an analog circuit.
[0002]
[Prior art]
Hereinafter, a conventional automatic layout flow of an integrated circuit including an analog circuit will be described.
FIG. 4 shows a flowchart of a conventional automatic layout method for an integrated circuit including an analog circuit. In this method, as shown in FIG. 4, a one-chip floor plan including analog is created through analog cell creation (step A1) and analog block creation (step A2) (step A3). It is called from an analog constraint group that is an analog constraint as manual information (step A7). Then, it is determined whether or not the called analog constraint is satisfied (restriction determination step A4). Only when it is determined that the analog constraint is satisfied, analog manual wiring is performed (step A5). The final determination of the analog restriction is made (final restriction determination step A6). If it is determined in the final determination step that the constraint is satisfied, non-analog automatic placement and routing (step A8) is performed, and the layout is completed (step A9).
[0003]
On the other hand, if it is determined as NG in the constraint determination step A4, the process returns to the analog block creation step A2 again to create a floor plan (step A3). Alternatively, the process directly returns to creation of a floor plan (step A3).
[0004]
If it is determined as NG in the final constraint determination step A6, the process returns to the analog block creation step A2 again to create a floor plan (step A3).
[0005]
That is, in this method, first, an analog cell is created based on the analog specification (step A1). Next, analog cells are assembled as blocks according to characteristics and functions (step A2). Here, an analog layout is realized in consideration of an analog constraint (A7) as manual information in consideration of analog characteristics. The problem items that occur at this time are constraints that fully consider the analog characteristics, and include, for example, equal-length wiring, prohibition of wiring crossing, star wiring, and shield wiring. Here, the flow operation will be described focusing on two restrictions, that is, equal length wiring and wiring intersection prohibition. The operator examines the arrangement of analog blocks in consideration of the wiring length and the arrangement of external terminals in consideration of the wiring intersection prohibition target in a one-chip floor plan. In the case of equal-length wiring, the analog block is arranged while manually measuring the wiring length information inside the analog block and the wiring length on one chip (from the external terminals to the pins of the analog block) (step A2). ). Also, regarding the cross prohibition, the positions of the blocks and the external terminals are determined in consideration of the arrangement with the external terminals and the pin positions on the analog block.
[0006]
At this time, if the constraint cannot be satisfied on the one-chip floor plan and it is determined as NG in the constraint determination step A4, the floor plan is reviewed and analog blocks and analog cells are recreated again (step A2). , Step A1).
[0007]
Then, when the arrangement position is substantially determined, the analog manual wiring is actually performed manually (step A5). This manual wiring has several tens or hundreds of wires, and since it is a manual operation, mistakes and omissions as well as man-hours have occurred, and iterations have occurred.
[0008]
After the block arrangement and the wiring in the analog circuit are completed in this way, it is confirmed from the layout data whether the wiring length or the intersection prohibition constraint is actually satisfied (decision step A6).
[0009]
Then, when it is determined that the determination step A6 is NG, the analog constraint itself is reviewed.
[0010]
In the case of OK, automatic placement and routing other than analog is performed (step A8), and the layout is completed through processes such as design rule check and clock care.
[0011]
[Problems to be solved by the invention]
However, in the above method, the analog characteristics are very restrictive, and conventionally, there is no one-chip specification in the analog cell creation specification, the analog specification cannot be read into the layout tool, and a manual check and manual wiring are required. Is going. For this reason, it is often necessary to correct analog restrictions after manual wiring. Furthermore, iterations (returning back) such as re-creation of analog blocks have occurred, and the reworking process goes back to not only one step but also one step before. Had a significant effect.
[0012]
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a layout method and apparatus of a semiconductor integrated circuit device that can shorten a development period and improve reliability against analog restrictions.
[0013]
[Means for Solving the Problems]
In order to achieve this object, the layout method of the present invention uses the analog constraints as visual confirmation and manuals, and reads the data manually wired as data at the time of one-chip floor plan. This enables placement that satisfies the constraints and reduces iterations.
Also, when checking analog constraints, by extracting necessary information from the data and performing a judgment process, visual check work can be eliminated, the reliability of LSI design completion can be improved without omission, and the entire system can be improved. The development period can be shortened.
That is, in the method of the present invention, in the automatic layout of a semiconductor integrated circuit including an analog circuit, a step of creating an analog block based on analog constraints on circuit information of a semiconductor integrated circuit chip, and wiring length information and intersection information based on the circuit information. An extraction step of extracting prohibition information; a floor plan creation step of creating floor plan information from the analog block based on the extracted wiring length information and intersection inhibition information to satisfy the analog constraint; Automatically generating layout pattern information of one chip from the plan information.
[0014]
According to this method, since an analog block is created based on analog restrictions, efficient automatic layout can be performed without any iteration such as analog block re-creation. In addition, since the floor plan information is created from the analog block based on the wiring length information and the intersection prohibition information extracted from the circuit information so as to satisfy the analog constraint, a highly reliable layout can be implemented at high speed. Become.
[0015]
Preferably, after the automatic generation step, a comparison step of extracting external terminal distance information and intersection signal line information from the generated layout pattern information and comparing the extracted information with the analog constraint is included. And
According to such a configuration, it is possible to automatically and easily confirm the analog constraint, and further high-speed processing can be performed.
[0016]
More preferably, in the comparing step, the wiring length of the target signal line extracted from the generated actual layout data of the analog block and the distance information to the external terminal extracted from the generated wired one-chip layout data are determined. The method includes a step of calculating a total wiring length as input information and a step of comparing the calculated total wiring lengths with each other to determine whether or not the analog constraint is satisfied.
[0017]
Further, according to the present invention, in an automatic layout device for a semiconductor integrated circuit including an analog circuit, an analog block creating means for creating an analog block based on analog constraints on circuit information of a semiconductor integrated circuit chip, and wiring length information from the circuit information Extracting means for extracting crossing prohibition information and crossing prohibition information; floorplan generating means for generating floorplan information from the analog block based on the extracted wiring length information and crossing prohibition information so as to satisfy the analog constraint; Automatic generation means for automatically generating layout pattern information of one chip from the floor plan information; and the layout pattern generated by the automatic generation means based on the wiring length information and intersection prohibition information extracted by the extraction means. Judge to determine whether analog constraints are satisfied If, on the basis of the determination result, if it is necessary, characterized by comprising a feedback loop for feeding back to said automatic generation means.
[0018]
According to such an apparatus, automatic layout can be easily performed.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.
FIG. 1 shows a flowchart of a layout method according to the first embodiment of the present invention.
[0020]
This layout method is characterized in that floor plan information is created from analog blocks so as to satisfy analog restrictions based on wiring length information and intersection inhibition information extracted from circuit information.
[0021]
That is, as shown in FIG. 1, first, in the analog cell creating step S1, an analog block is created based on the analog specification S4 (step S2).
Then, a floor plan is created from the analog block in consideration of the wiring length information and the intersection prohibition information (step S3).
[0022]
Note that the wiring length information and the intersection prohibition information are obtained through the step S5 of extracting the wiring length of the signal line of the equal length wiring restriction from the analog block and the step S6 of extracting the wiring intersection prohibition information in the unified format from the analog specification. After being obtained and passing through the constraint determination processing step S9, it is input as a determination condition of the constraint determination step S7 for determining whether the analog constraint is satisfied.
[0023]
Further, the floor plan obtained in the floor plan creation step S3 is subjected to a determination as to whether or not the determination condition obtained in the constraint determination processing step S9 is satisfied (step S7).
[0024]
Then, the layout is completed through the automatic placement and routing step, S8.
[0025]
Note that the constraint determination processing step S9 is a step of comparing and determining the equal-length wiring with information extracted from the actual layout data on the intersection prohibition constraint. This step uses the wired layout data to convert the analog pins of the equal-length wiring target to the external terminals. Of the wiring length up to and a step S11 of extracting intersecting wiring among the analog signal lines from the wired layout data, and then input again to the constraint determination processing step S9 to satisfy the constraint condition. Then, the automatic layout design of the integrated circuit is completed (S12).
[0026]
The method will be described in detail below based on the above flowchart.
First, layout design in a digital / analog mixed LSI is started. Analog circuits may be registered in the standard library, but this time I will explain core development for layout design including the analog circuits.
[0027]
Analog characteristics and specifications are converted into data to create analog specifications (step S4), and a layout of analog cells is created so as to satisfy the specifications (step S1).
[0028]
Next, a layout of an analog block is created in consideration of the characteristics and specifications of the analog cells (step S2). Here, the analog constraint is included in the specification, and the analog block is designed to satisfy the constraint.
[0029]
At this time, the wiring length of the target signal line is extracted from the layout data when the analog block is created, taking into account the analog constraint of equal-length wiring (step S5). Further, from the analog specification generated in step S4, a wiring intersection prohibition target is extracted from an external terminal, a signal line name, and a pin name of a connection destination to perform data conversion to generate cross prohibition information (step S6).
[0030]
In the one-chip layout floor plan process (step S3), the layout is examined and implemented for analog. The floor plan is implemented by incorporating the wiring length data and the wiring intersection prohibition data. When generating the floor plan, the arrangement of the analog blocks is determined from the wiring length data, and the arrangement of the external terminals and the analog block pin positions are determined from the wiring crossing inhibition data. In this step, no wiring has yet been performed.
[0031]
In the arrangement state, an analog constraint of prohibiting intersection of equal-length wiring and wiring is determined (step S7). In the case of NG, fine correction of the arrangement position or correction of the pin position of the analog block is performed. If OK, the process proceeds to an automatic wiring process (step S8).
[0032]
Next, in the automatic placement and routing, the wiring length data and the intersection prohibition data are added to the technology file in the same manner as in normal logic, and wiring including analog is performed based on the data. At this time, a normal design rule check can also be performed for the analog constraint, and can be confirmed at a time. When the automatic placement and routing is completed, the external terminal distance information is extracted from the actual layout data for the equal-length wiring and the target for which wiring intersection is prohibited (step S10), and the intersection information is extracted (step S11). By inputting the data together with the wiring length data and the wiring intersection prohibition data into the constraint determination processing, the final check of the analog constraint in the final layout data is performed (step S9). This completes the layout.
[0033]
According to the present embodiment as described above, it has been necessary to extract information in advance that a great amount of backtracking and man-hours have been involved in analog cell or block creation and placement and position determination in a one-chip floor plan. By incorporating it into a one-chip layout design and performing design and confirmation under one tool environment, it is possible to improve the reliability of the iteration and design perfection in the upstream design, and to shorten the development period. is there.
[0034]
Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.
FIG. 2 shows a CAD apparatus as a layout apparatus according to a second embodiment of the present invention.
As shown in FIG. 2, the CAD device includes a storage device T1 for storing libraries and analog layout data in a layout design, a storage device T2 for analog constraint information, and a host computer T3. The host computer T3 includes a one-chip layout design processing unit T4 including the current analog constraint, and a one-chip layout design processing unit T4 includes a floor plan creation unit T5, a target wire length extraction unit T6, an intersection prohibition information extraction unit T7, It is composed of a placement and routing unit T8, an external terminal distance extraction unit T9, an intersection signal line list extraction unit T10, a constraint determination unit T11, and an input / output control unit T12.
These T5, T6, T7, T8, T9, T10, and T11 correspond to means for executing S3, S5, S6, S8, S10, S11, and S9 in FIG. These keys T5, T6, T7, T8, T9, T10, T11, and T12 are operated by a key operation device T13 for inputting commands and files, and the processing results are displayed on a display device T14.
[0035]
The operation of the CAD device configured as described above will be described below.
First, the host computer T13 is started, and the layout design based on support is started by the key operation device T13. At this time, the host computer T13 reads the information T6 of the target wiring length at the time of creating the analog block from the layout data storage device T1, and also reads the signal line name of the line intersection prohibition from the analog constraint storage device T2, and the one-chip floor plan T5. Generate
Next, after executing the automatic placement and routing T8, the host computer T13 extracts the wiring length T6 from the actual layout data and outputs the intersecting signal line names T10 as a list for confirmation processing. The external terminal distance information T9 and the intersection signal line list T10 are input and subjected to a determination process in a constraint determination device T11 for comparing with the analog constraint information including the wiring length extraction information T6 and the intersection prohibition information T7. The determination is made, and the result is output to the display device T14 through the input / output control unit T12.
[0036]
As described above, by providing analog constraint information and its determination processing on the one-chip layout in the host computer, the operation by one host computer can be performed, so that manual work and confirmation can be reduced. The period can be shortened.
[0037]
Hereinafter, as a third embodiment of the present invention, a layout method of the present invention will be described along the flow of data with reference to the drawings.
In FIG. 3, U1 is external terminal distance information, U2 is target wiring length information in an analog block, U3 is a list of crossing wirings in analog wiring extracted from actual layout data, and U4 is changed to a unified format from analog specifications. U5 is a wiring length calculation processing step for the target wiring, U6 is a data conversion processing step for sorting the order of each data, U7 and U8 are output data in which the order is sorted, and U9 is a signal of an equal length wiring. A line name group U10 is a step of comparing and judging equal length wiring and intersection prohibition constraints based on each input data, and U11 is a step of displaying a final result.
[0038]
The operation of the above-described flowchart will be described below.
First, in the case of the equal-length wiring, the wiring length data U2 of the equal-length wiring target signal line and the distance data U1 from the analog pin extracted from the wired one-chip layout data to the external terminal from the time of analog block creation are input. The total wiring length of the long wiring target is calculated (step U5).
[0039]
The calculated wiring lengths are compared with each other from the equal-length wiring signal line name group U9 to make a determination (step U10). Also, in the wiring crossing prohibition, the crossing prohibition data U4 and the list of intersecting signal line names U3 in the analog wiring extracted from the wired one-chip layout data are input and the arrangement order is sorted and data conversion is performed. (Step U6), and compares and searches the intersecting external terminal name signal line name, pin name U8, and the intersection prohibition information, the external terminal name signal line name and pin name U7 (Step U10). judge. Finally, OK is displayed (step U11), and the layout is completed.
[0040]
According to the present embodiment as described above, by performing a basic process of comparing or searching for the initial analog constraint and the actual layout data, it is possible to eliminate visual confirmation by hand and prevent omissions and mistakes. The development period can be shortened by reducing iterations.
In the above-described embodiment, a digital-analog mixed LSI has been described. However, the present invention is not limited to a digital-analog mixed LSI, and any semiconductor integrated circuit device including an analog circuit is effective.
[0041]
【The invention's effect】
As described above, according to the present invention, an analog constraint is used as data information, a floor plan is created based on the data information, and a layout design is performed, whereby work on one tool can be realized.
[0042]
Also, by providing a judgment processing step in constraint checking, it is possible to prevent omissions and mistakes in the visual checking work in a later step and to significantly reduce the number of steps.
Further, according to the layout apparatus of the present invention, it is possible to realize an automatic layout that can shorten the development period and improve the reliability of the checking operation.
[Brief description of the drawings]
FIG. 1 is a flowchart of a digital / analog mixed automatic layout method according to a first embodiment of the present invention; FIG. 2 is a diagram showing a CAD apparatus according to a second embodiment of the present invention; FIG. FIG. 4 is a flowchart of a constraint determination process according to the embodiment of the present invention. FIG. 4 is a flowchart of a conventional digital / analog mixed automatic layout method.
T1 Layout data storage device T2 Analog constraint storage device T13 Key operation device T4 Display device

Claims (4)

In an automatic layout of a semiconductor integrated circuit including an analog circuit, a step of creating an analog block based on analog constraints on circuit information of the semiconductor integrated circuit chip;
An extraction step of extracting wiring length information and intersection prohibition information from the circuit information,
A floor plan creation step of creating floor plan information from the analog block to satisfy the analog constraint, based on the extracted wiring length information and intersection prohibition information;
An automatic generation step of automatically generating layout pattern information of one chip from the floor plan information. After the automatic generation step,
2. The semiconductor integrated circuit according to claim 1, further comprising: a step of extracting external terminal distance information and intersection signal line information from the generated layout pattern information, and comparing the extracted information with the analog constraint. Device layout method. Further, in the comparing step, the wiring length of the target signal line extracted from the generated actual layout data of the analog block and distance information to an external terminal extracted from the generated one-chip layout data are input information. Calculating the total wiring length as
3. The layout method of a semiconductor integrated circuit device according to claim 2, further comprising: comparing the calculated total wiring lengths with each other to determine whether the analog constraint is satisfied. In an automatic layout device for a semiconductor integrated circuit including an analog circuit,
Analog block creating means for creating an analog block based on analog constraints for circuit information of the semiconductor integrated circuit chip;
Extracting means for extracting wiring length information and intersection prohibition information from the circuit information,
Floor plan creation means for creating floor plan information from the analog block based on the extracted wiring length information and intersection prohibition information so as to satisfy the analog constraint;
Automatic generation means for automatically generating layout pattern information of one chip from the floor plan information;
A determination unit configured to determine whether the layout pattern generated by the automatic generation unit satisfies an analog constraint, based on the wiring length information and the intersection prohibition information extracted by the extraction unit;
And a feedback loop that feeds back to the automatic generation means when necessary based on the determination result.

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