JPH05108745A - Method and device for generating test data - Google Patents

Abstract

PURPOSE:To generate the test data of a logic circuit on a printed circuit board by using the test data generated before for the simulation of the partial circuit on an LSI, etc. CONSTITUTION:A circuit information storage means stores the function of each circuit element of the logic circuit and connection relation between the input/output terminals of the circuit element. An input means 5 inputs the history of the test data of each input/ output terminal of the partial circuit. Besides, an arithmetic means 7 determines the possible input history of the circuit element or a mutual condition between the input histories from the history of each output of the circuit element. Then, a control means 8 obtains all such the possible input histories or such the mutual condition between the input histories of the circuit element to be connected to the preceding stage of the terminal as to give the history to each input terminal of the partial circuit by using the arithmetic means 7, and it continues this processing for obtaining these until it reaches the input terminal of the logic circuit, and the obtained input history of the input terminal of the logic circuit is made into the test data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test data generation method for generating test data of a logic circuit for simulation of the logic circuit. Efficient operation of logic simulation is required to shorten the circuit design.

[0002]

2. Description of the Related Art Conventionally, when generating test data for simulating a logic circuit on a printed circuit board in which an LSI is mounted on the printed board, an LSI designer must
The designer of the printed circuit board duplicated the test data of the LSI alone, and independently created the test data of the entire logic circuit on the printed circuit board including the LSI alone.

[0003]

However, according to the above-mentioned conventional test data generating method, the designer of the printed circuit board needs to know all the LSIs mounted on the printed circuit board.
With respect to, the test data of the logic circuit on the printed circuit board cannot be generated without understanding the operation of each internal circuit. Therefore, the burden on the designer of the printed circuit board is large, and regarding the LSI alone, the operation of the entire circuit including the circuit inside this LSI is again performed even though the LSI designer has already created the test data. Since the test data is generated after understanding, there is a problem that the process is duplicated and the work becomes inefficient as a whole.

According to the present invention, even if the designer of the printed circuit board does not understand the operation of each internal circuit of all the LSIs mounted on the printed circuit board, the logic circuit on the printed circuit board It is an object of the present invention to provide a test data generation method capable of generating test data.

[0005]

FIG. 1 is a diagram showing a basic procedure of a test data generating method of the present invention. In step 1 of FIG. 1, the history of test data of each terminal of the simulated partial circuit is input. In step 2, all possible input histories of circuit elements connected to the preceding stage of the above-mentioned input terminals, which give the history of the above-mentioned test data to each input terminal of the above-mentioned partial circuit, or Find the mutual conditions of the input history.

In step 3, the process of step 2 is continued until the input terminal of the logic circuit is reached. Then, in step 4, the input history of the input terminal of the logic circuit obtained in the third step 3 is used as the test data of the logic circuit. FIG. 2 shows a basic configuration of a test data generating device for a logic circuit including a simulated partial circuit according to the present invention. Figure 2
In the figure, 5 is a circuit information storage means, 6 is an input means, 7 is a calculation means, and 8 is a control means.

The circuit information storage means 5 stores the function of each circuit element of the logic circuit and the connection relationship between the input / output terminals of the circuit element. The input means 6 inputs the history of test data of each input terminal of the partial circuit. The calculation means 7 is
From the output history of each circuit element, the possible input history of the circuit element or the mutual conditions of the input history are obtained.

The control means 8 uses the calculation means 7 to
All possible input histories of the circuit elements connected to the preceding stage of the above terminals, or conditions for mutual input histories, which give the histories to the respective input terminals of the partial circuit, are obtained, and the processing is performed. , Until the input terminal of the logic circuit is reached, and the obtained input history of the input terminal of the logic circuit is used as the test data of the logic circuit.

[0009]

According to the present invention, when the test data to be input for the simulation of the entire logic circuit is created,
Backtrace is performed from the input terminal of the partial circuit based on the test data of the partial circuit for which the test data has already been obtained, and the output history (output value as a function of time) of the circuit element at the input destination is obtained. Obtaining the history of the input to be realized (input value as a function of time) or the condition between the input terminals and repeating this up to the input terminal of the logic circuit to automatically obtain the test data to operate the internal partial circuits. You can Therefore, it is possible to create test data for the entire logic circuit without paying attention to the operation of the partial circuit.

[0010]

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. FIG. 3 shows a control procedure in the embodiment of the present invention. In FIG. 3, in step 1, a simulation result of a partial circuit (for example, LSI) is input, and in step 12, the history of the value of the input terminal of the partial circuit is extracted from the simulation result of the partial circuit.

Next, in step 13, the input destination circuit element is searched for the input terminal. In step 14, it is judged whether or not this circuit element is an input terminal of the printed circuit board. If not, the process proceeds to step 15 and the change in the value of the output terminal of the circuit element and the input terminal value / condition are checked. The value / condition (as a function of time) at that input terminal is calculated from the conditions of the other input terminals involved. Then, in step 16, the value / condition obtained by the above calculation is stored in the storage unit (for example, RAM). And step 13
Return to.

If it is determined in step 14 that the input terminal of the printed circuit board is reached, in step 17, the values / conditions stored in the above-mentioned storage section are used as test data (input for the printed circuit board). ) Take out as. FIG. 4 shows an example of the configuration of a logic circuit to which the present invention is applied. In FIG. 4, a partial circuit 23 surrounded by a dotted line 23 is a simulated portion,
It is assumed that the test data is known.

In this case, the input terminal a of this partial circuit 23
And b, there is an AND circuit 21 and an OR circuit 2 in front of them, as shown in FIG.
2 are connected to each other, the partial circuit 23 of FIG.
Assuming that inputs a and b of ## EQU3 ## have changing histories as shown in FIG. 5, for example, inputs d and e of the AND circuit 21 are as shown in FIG. 5, respectively. Here, the inputs d and e of the AND circuit 21 are
In the case of the inputs f and g of this printed circuit board, respectively, these values become the test data from the input terminals f and g of the printed circuit board.

Further, FIG. 6 shows a configuration for obtaining test data of the logic circuit of FIG. In FIG. 6, 31 is a control unit, 32 is a calculation unit, 33 is a database unit, and 34 is a storage unit. The control unit 31, the calculation unit 32, and the circuit information database 33 correspond to the control unit 8, the calculation unit 7, and the circuit information storage unit 6 in FIG. 2, respectively. Further, the storage unit stores the history of the input value / condition of each circuit element at the stage of each circuit element of the back trace processing according to the present invention, as described earlier in the procedure of FIG. Storage unit 3 of FIG.
4 shows that the history of the points d, e, and c of the history of FIG. 5 is stored. As shown in FIG. 6, the circuit information database 33 of FIG. 6 also stores information about element names, element functions, input terminals, output terminals, and connection relationships of input / output terminals (not shown). ing. The control unit 31 can be realized by, for example, a microcomputer.

[0015]

As described above, according to the present invention,
Even if the designer of the printed circuit board does not understand the operation of each internal circuit of all the LSIs mounted on the printed circuit board, the test data for the simulation of the partial circuits such as already generated LSIs is used. As a result, the test data of the logic circuit on the printed circuit board can be generated.

[Brief description of drawings]

FIG. 1 is a diagram showing a test data generating method according to the present invention.

FIG. 2 is a diagram showing a test data generating device according to the present invention.

FIG. 3 is a diagram showing a control procedure in the embodiment of the present invention.

FIG. 4 is a diagram showing an example of a configuration of a logic circuit to which the present invention is applied.

5 is a diagram showing a signal history of each part of the logic circuit of FIG.

6 is a diagram showing a configuration for obtaining test data of the logic circuit of FIG.

[Explanation of symbols]

 21 ... AND circuit 22 ... OR circuit 23 ... Partial circuit 24 ... LSI 31 ... Control part 32 ... Calculation part 33 ... Circuit information database 34 ... Storage part

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display location G06F 11/26 310 9072-5B

Claims (2)

[Claims] 1. A method of generating test data for a logic circuit including a simulated partial circuit, comprising: a first step (1) of inputting test data history of each input terminal of the partial circuit; A second step (2) of obtaining all possible input histories of circuit elements connected to the preceding stage of the above-mentioned terminals so as to give the history to the input terminals or mutual conditions of the input histories; A third step (3) of continuing the processing of the second step (2) until reaching the input terminal of the logic circuit, wherein the logic obtained by the third step (3) And a fourth step (4) in which the input history of the input terminal of the circuit is used as the test data of the logic circuit. 2. A test information generation device for a logic circuit including a simulated partial circuit, circuit information storage means for storing the function of each circuit element of the logic circuit and the connection relationship between input / output terminals of the circuit element. (5), an input means (6) for inputting a history of test data of each input terminal of the partial circuit, and a possible input history of the circuit element from the output history of each of the circuit elements, or an input history mutual And a circuit element connected to the preceding stage of the above-mentioned terminal that gives the history to each input terminal of the partial circuit by using the calculating means (7). , All possible input histories, or conditions for mutual input histories,
A control means (8) which continues until it reaches the input terminal of the logic circuit, and which uses the obtained input history of the input terminal of the logic circuit as test data of the logic circuit. Data generator.