JPH06332974A - Logic simulation method - Google Patents

Abstract

PURPOSE:To simultaneously process the logic simulations based on suppositions that respective elements have arbitrary kinds of delay and to easily find the malfunction of the logic circuit due to the unevenness of delay. CONSTITUTION:In the logic simulation method which simulates the logic circuit in accordance with information of events, discrimination numbers 108 of classifications of delay are provided as information of events, and the same number of output values 133 and delay values 134 of elements as classifications of delay are provided as information of elements with respect to each output terminal; and at the time of execution of simulation, a new event is generated in accordance with propagation of events and the signal value change with respect to the output value and the element delay value corresponding to the discrimination number of the classification of delay of each event.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic simulation method for simulating the operation of a logic circuit on a computer, and more particularly to a method for simulating logic elements by assigning a plurality of types of delays.

[0002]

2. Description of the Related Art The event method is known as a logic simulation method for simulating a logic circuit with a computer. In the event method, the change in the signal value of a logic element is called an event,
Processing is performed by evaluating this event in order of the time when the signal value change propagates. In the conventional event method, as information of an event, as shown in FIG. 2A, a time at which a signal propagates, an identifier of element information at which the signal propagates, an identification number of an output terminal at which the signal propagates, and a signal value at which the signal propagates. To have.
As shown in FIG. 2B, the information of the logic element also includes the identification number of the element type, the element unique name, the number of input terminals, a list of connection destination pointers and output terminal numbers for each input terminal, the number of output terminals, each It has a list of connection destinations for each output terminal, a list of connection destination pointers, output values, and delay values of elements.

Further, as shown in FIG. 3, the time at which the signal propagates to the output terminal of the element is the time XT + which is the time XT at which the signal change propagates to the input terminal, plus the delay time D peculiar to each element.
Given by D. The delay time peculiar to this element takes a value within a certain range due to variations in manufacturing. Therefore, in order to perform a more accurate logic simulation, the minimum value, the maximum value, or the standard value of the delay time is set for each element, and the logic simulation is performed to determine whether the logic circuit operates correctly regardless of the delay time variation. Verify whether or not.

For this purpose, for example, Japanese Patent Laid-Open No.
Japanese Patent Laid-Open No. 105232 describes a method of simultaneously processing two types of delay times, a minimum delay and a maximum delay. In this method, the event with the minimum delay and the event with the maximum delay are independently held, and at each time, the event with the minimum delay and the event with the maximum delay propagating at that time are respectively evaluated. According to this method, both the maximum delay and the minimum delay are processed at the same time, so that not only the work of starting the logic simulation is simplified, but also the comparison between the logic simulation results of the maximum delay and the minimum delay can be performed at any time. .

[0005]

In the conventional method, a data structure for storing events according to the type of delay (for example, minimum delay, maximum delay, standard delay) and event evaluation for each type of delay are programmed. It had to be built in beforehand.

Further, when the processing for evaluating an event is performed in parallel by dedicated hardware, a plurality of events propagating at each time are to be processed in parallel. However, when attempting to implement the conventional method on such hardware as it is, it is necessary to evaluate the event with the maximum delay and the event with the minimum delay independently, so the number of events to be processed in parallel at one time. However, there is a problem that the effect of parallel processing is reduced.

An object of the present invention is to provide a logic simulation method capable of coping with an arbitrary number of delay types and simultaneously processing events due to a plurality of types of delays simultaneously.

It is another object of the present invention to provide a method of simultaneously processing logical simulations using a plurality of types of delays and a plurality of types of test vectors (sometimes called test data or test patterns) at the same time.

[0009]

In order to solve the above problems, a delay type identification number is added to conventional event information. Further, it is assumed that the conventional output value information and delay value information of element information are held for each output terminal by the number of types of delay. Then, at each time of the logic simulation, with respect to the element output value and the element delay value corresponding to the identification number of the delay type of each event, the event propagation and the generation of a new event due to the signal value change are performed.

Further, in order to compare the results of the logic simulation for each type of delay, according to the identification information of the element output terminal of the observation target and the observation period information which are designated in advance,
At the corresponding simulation time, it is determined whether the output values of the elements corresponding to all the delay types of the output of the observation target element are all equal, and the result is output.

Further, in order to evaluate the test vector for all delay types, an event having an identification number of all delay types is generated for a given test vector.

Alternatively, in order to process a plurality of test vectors at the same time by using this method, events having different delay type numbers are simultaneously generated for a given plurality of test vectors.

[0013]

By adding the identification number of the delay type to the event information, it is not necessary to hold the event information for each delay type. In addition, the output value of the element information and the delay value information are held for each output terminal by the number of delay types, so that the event value corresponding to the delay type number stored in the event information By propagating the information and generating a new event using the delay value corresponding to the delay type number, it is not necessary to evaluate the event independently for each type of delay. as a result,
Events at the same time can be evaluated collectively at the same time regardless of the type of delay, and efficient processing can be performed even in parallel processing.

Further, by comparing the output values of the elements corresponding to all delay types according to the identification information of the element output terminals of the observation target and the observation period information which are designated in advance,
It becomes easy to find a malfunction of the circuit due to variation in element delay.

Furthermore, by causing an event having identification numbers of all delay types for a given test vector, the test vector can be evaluated for all delay types.

Alternatively, it is possible to simultaneously process a plurality of test vectors by simultaneously generating events having different delay type numbers for a plurality of given test vectors. According to this method, by setting a common delay time that does not depend on the delay type number for each element, it is possible to collectively process simulations by a plurality of completely independent test vectors.

[0017]

Embodiments of the present invention will be described below with reference to FIGS. 1 and 4 to 28. First, a method of allocating a plurality of types of delays to each element and simultaneously processing logic simulations based on a plurality of types of delays for one test vector at the same time using FIGS. 1 and 4 to 8 ( Hereinafter, an example of (multiple delay logic simulation) will be described. Next, with reference to FIG. 9, an embodiment of a method for collectively processing logic simulations for a plurality of test vectors simultaneously (hereinafter referred to as a multiple test logic simulation method) will be described. Further, the operation of the multi-delay logic simulation will be described with reference to FIGS.

In the present embodiment, three values of 0, 1 and an indefinite value X are handled as logical values, and a logic simulation model assuming a delay time is adopted for each element. Further, in this embodiment, a portion not directly related to the present invention, for example, a process of analyzing a structure of a logic circuit necessary for logic simulation and creating a data structure necessary for simulation, and outputting the result of the simulation in a format understandable to the user. The description of the processing is omitted, and only the execution part of the logic simulation will be described.

Further, in the description of the present embodiment, the first element of data having a plurality of elements is the 0th element, the next element is the first element, and so on. The first.

FIG. 1 is an explanatory diagram of a data structure for realizing a multi-delay logic simulation. FIG. 1A is a data structure for storing event information. Reference numeral 101 is a data structure called a time wheel that has been conventionally used in logic simulation by the event method. The time wheel classifies and holds events according to the signal propagation time. Each event information 102 is connected by a link pointer 103 and can be sequentially read.

The event information is composed of five pieces of information 104-108. The information of one event is the information that “the output terminal of a certain element changes to a certain value at a certain time”. The signal propagation time 104 is the time at which the event propagates, the signal propagation element 105 is the identifier of the element through which the event propagates, the propagation output 106 is the identifier of the output terminal through which the event propagates, and the propagation signal value 107 is the signal at the element output through which the event propagates. The value and the delay type number 108 are the numbers of the types of delays targeted by the event.

FIG. 1B shows a data structure for storing information on logic elements. Reference numeral 111 represents information of one logic element having a plurality of input terminals and a plurality of output terminals. At the time of logic simulation, 111 data structures corresponding to the number of logic elements are prepared. In FIG. 1B, an element type identification number 112 is an element type identifier, an element unique name 113 is an element unique name represented by the element 111, and the number of input terminals 114.
Is the number of input terminals of the element, 115 is a pointer that points to the storage area of the input terminal information list, 116 is the number of output terminals of the element, and 117 is a pointer that points to the storage area of the output terminal information list.

The storage area of the input terminal information list is composed of the input connection destination pointer 121 and the output number 122, and the number 123 of these elements is equal to the number 114 of input terminals. The input connection destination pointer 121 is a pointer pointing to the beginning of element information connected to the tip of the input terminal of the element 111, and an output number 122.
Is the number of the output terminal of the element connected before the input terminal.

The storage area of the output terminal information list is the number of output connection destinations 124, the pointer 125 that points to the head of the output destination pointer area, and the pointer 126 that points to the head of the area for storing the output value and delay value for each delay type. The number of elements 127 is equal to the number of output terminals 116. The output connection destination connection number 124 is the number of elements connected to each output terminal. Output destination pointer area 13 pointed to by the pointer 125
1 is composed of a pointer pointing to the head of the area for storing the element information of the output connection destination, and the number of elements 132 thereof is equal to the number of output connection destinations 124. An area for storing the output value and the delay value for each delay type pointed to by the pointer 126 is composed of the output signal value 133 and the delay time value 134 for each output terminal,
The number of elements 135 is equal to the number of delay types. The elements are stored in numerical order of delay type.

FIG. 4 is an explanatory diagram of a logic simulation process for implementing the present invention. The process of FIG. 4 is started after the elements of the logic circuit to be simulated and the connection information are created in advance in the format 111 of FIG. In the initial state, no event information is stored in the time wheel that stores the event information of FIG.

First, at 401, the simulation time XT is initialized. The loop of 402 is processing 403-40
7 is repeated until the simulation time XT reaches the end time. The test vector addition process 403 is a process of adding a test vector given at the time of simulation as an event. The process of adding the test vector differs between the multiple delay logic simulation and the multiple test logic simulation.

FIG. 5 shows a test vector addition process in the multiple delay logic simulation, and FIG. 9 shows a test vector addition process in the multiple test logic simulation.

The event propagating process 404 is a process of propagating an event to each element according to the event information at time XT held in the time wheel. Details of the event propagation processing are shown in FIG. The element output value evaluation processing 405 is to output a new output based on a new input signal value for an element connected to an output terminal of an element in which an event is propagated, that is, an output signal value is changed, that is, an input signal is changed. The signal value is obtained, and when the new output signal value is different from the output signal value up to that point, the change is added to the time wheel as an event. Details of the element output value evaluation processing are shown in FIG. The output value comparison processing 406 refers to the output values of all the delay types with respect to the output terminal of the designated element at regular time intervals, checks whether or not they match, and outputs the result. This processing is shown in FIG.
Details are shown in. At 407, the simulation time XT is updated to the next time.

FIG. 5 is a diagram for explaining the test vector addition processing 403. Test vector information 5 in FIG.
00 has shown the example of the data structure which stores a test vector. This data structure is composed of a reference pointer P501 for referring to one element of the test vector and a table 502 for storing the test vector. The table 502 shows the time 5 at which the test vector is propagated to the input of the circuit.
03, an input identification number 504 of a propagating input, and a signal value 505 of propagating.

In this embodiment, as shown in the example of FIG. 10, the input of the circuit is considered as an output terminal of a virtual element (virtual input element), and element information in the format 111 of FIG. 1 is prepared for input. . This virtual input element has no input terminal, only an output terminal, and only one in the circuit. In this embodiment, the test vector is processed as an event that changes the output of the virtual input element. The table 502 stores the signal change information of the test vector in order of time.

Test vector addition process 4 in FIG. 5B
In 03, in the loop of 511, as long as the time 503 of the table 502 is equal to the current time XT and the reference pointer P points within the range of the table 502, 51
Processes 2 to 514 are performed. In the loop 512, the processing of 513 is performed for one element of the test vector pointed to by the reference pointer P by the number of types of delay. In 513, the time 503 of the element pointed to by P is the signal propagation time 104, the pointer to the virtual input element is the signal propagation element 105, the input number 504 of the element pointed by P is the propagation output 106, and the propagation value 5 of the element pointed by P is 5.
05 is the propagation signal value 107 and the counter value of the loop 512
(0 to the number of types of delay-1) is the delay type number 1
An event of 08 is generated and registered in the time wheel. At 514, the reference pointer is updated to a value pointing to the next element.

FIG. 6 shows the event propagation process 4 in FIG.
It is explanatory drawing of the detail of 04. FIG. 6A is an explanatory diagram of a data structure of the output destination connection element information 600 created by the event propagation processing. In the event propagation processing, the event stored in the time wheel is propagated to the element, and pointers pointing to the element connected to the output terminal of the element to which the event is propagated are listed in the table shown in FIG.

FIG. 6A is composed of a reference pointer Q601 and an output destination connection element table 602. The table 602 includes an output destination connection pointer 603, which is a pointer that points to the beginning of element information, and a delay type number 604.

FIG. 6B is an explanatory diagram of the procedure of event propagation processing. First, at 611, the reference pointer Q is set to the table 6
Set to point to the beginning of 02. Loop 612 repeats for all events propagating at the current simulation time XT stored in the time wheel.
At 613, the event E is taken out from the time wheel. 6
14, the number indicated by the propagation output 106 of E for the element X indicated by the signal propagation element 105 of E (assumed to be the EOth)
The output value of the output terminal at the position of the number indicated by the E delay type number 108 is set as the E propagation signal value 107. Loop 6
15 is 6 as many as the number of connection destinations of the EOth output terminal of the element X
The processing of 16,617 is repeated. In 616, the element of the table 602 pointed to by the reference pointer Q is the jth of the EOth output terminal of the element X (j is the loop counter of the loop 615, and the number of output connection destinations of 0 to the EOth output terminal of the element X − The output connection destination pointer 131 (value up to 1) is stored as the output connection destination pointer 603, and the delay type number of E is stored as the delay type number 604. At 617, the reference pointer Q is updated to a value pointing to the next element.

FIG. 7 shows the element evaluation processing 405 in FIG.
3 is an explanatory diagram of details of FIG. In the processing procedure shown in the figure, first in 701, a table 602 for storing the output destination connection information of FIG.
A pointer R that points to is initialized to point to the beginning of the table 602. In the loop 702, the pointer R is the table 6
The range of elements of 02, that is, the processes of 703 to 707 are repeated by the number registered in the event propagation process 404. The loop 703 is 6 of the output connection destination pointer of the element pointed to by R.
704 to 706 are repeated by the number of output terminals of the element Y indicated by 03.

In 704, the element connected to the input terminal of the element Y, that is, the element indicated by the connection destination pointer 121, the output terminal connected to the element Y, that is, the output point of the output number 122th output element of the element Y, indicated by R. From the output value of the delay type number 604th (RDth) of the element and the element type identification number 112 of the element Y, a new output value V of each output terminal of the element Y is obtained.
Find k (k is the loop counter of loop 703).

At 705, the new output value V obtained at 704
If k and the RDth output value of each output terminal of the element Y are not equal, the processing of 706 is performed. At 706, at the current simulation time XT, the RD of the kth output of the element Y is
The value obtained by adding the th delay value 134 to the signal propagation time 104,
An event is added to the time wheel with a pointer value pointing to the head of the area for storing the information of the element Y as a signal propagation element 105, k as a propagation output 106, Vk as a propagation signal value 107, and RD as a delay type number 108.

FIG. 8 is an explanatory diagram of the output value comparison processing 406.

FIG. 8A is a diagram for explaining the data structure for storing information 808 on the element to be observed and its output terminal and information 807 on the period for observing them. The observation start time XS801 stores the simulation time to start the observation, and the observation cycle XP802 stores the observation cycle. A pointer S803 is a pointer that refers to an element of a table 806 that stores information on an element to be observed and its output terminal. The table 806 is a pointer 804 that refers to the element information 111 of the observation target and the output terminal number 8 of the observation target element.
Let 05 be the element.

FIG. 8B is an explanatory view of the procedure of the output value comparison processing. In 811, the observation start time XS and the observation period XP
The processing of 812 to 822 is performed only when the time designated by, that is, the current simulation time XT is larger than XS, and the difference between XT and XS and the remainder of XP are zero. In step 812, the pointer S803 is set to the table 8
Initialize to point to the first element of 06. In the loop of 813, while S refers to the elements of the table 806 (the number of times equal to the number of elements of the table 806) 814 to 814
22 is repeated.

At 814, the counters C0, C1 and CX are set to 0.
Initialize to. The loop of 815 is the processing of 816 to 822 by the number of delay types for the output terminal number 805th (SOth) output terminal of the element pointed to by S, of the element Z pointed by the element pointer 804 of the element pointed to by S. repeat. In 816, when the m-th output value (m is a loop counter of the loop 815) of the SO-th output terminal of the element Z is 0, 1 or an indefinite value X, the counter C is output.
Increment 0, C1, CX (817 to 8)
19). At 820, if a plurality of counters among the counters C0, C1, and CX are not 0 at the same time, that is, if there is a mismatch in the outputs, 821 is performed. Time X at 821
At T, it outputs that there is a mismatch in the SOth output of element Z. At 822, the pointer S is updated to a value indicating the next element.

FIG. 9 is an explanatory diagram of the test vector addition processing 403 in the multiple test logic simulation. In this process, multiple types of test vectors are handled simultaneously. FIG. 9A shows an example of the data structure for storing the test vector. This data structure is the same as FIG. 5A except that the vector type 906 is added to the table 902. The vector type 906 stores a number for identifying which test vector the element belongs to. The table 902 stores the signal change information of the test vector chronologically regardless of the type of the test vector.

In the processing of FIG. 9B, in the loop of 511, as far as the element of which time 503 is equal to the current simulation time XT in the table 902 and the reference pointer P points within the range of the table 902, 913, 514.
Process. In 913, the time 503 of the element pointed to by P
Is a signal propagation time 104, a pointer to a virtual input element is a signal propagation element 105, an input number 504 of an element pointed by P is a propagation output 106, a propagation value 505 of an element pointed by P is a propagation signal value 107, and an element pointed by P is An event having the vector type number 906 as the delay type number 108 is generated and registered in the time wheel. At 514, the reference pointer is updated to the next element. Figure 9 shows the multiple test logic simulation.
The parts other than the test vector addition processing shown in FIG. 6 are the same as those of the embodiment of the multi-delay logic simulation shown in FIGS. 1, 4 and 6 to 8.

The operation of the embodiment of the present invention described with reference to FIGS. 4 to 8 will be described with reference to FIGS. FIG. 10 is a diagram showing an example of a logic circuit used for description. FIG. 10A shows an actual logic circuit, and FIG. 10B shows a circuit when the simulation is executed.

In FIG. 10A, 1001 to 1003 are input terminals of the circuit, 1004 is an element having a proper name of G1, and its type is AND, and two types of delay times 3 and 5. 1005 is an output signal of the element 1004, 1
006 is an element having a proper name of G2, and its type has OR, and two types of delay times 2 and 4. 1007 is an output signal of the element 1006. Circuit input terminal 100
1, 1002 are connected to the input terminals of the element 1004. The output signal 1005 of 1004 is connected to the input terminal of the element 1006. The input terminal 1003 of the circuit is the element 100
It is connected to the other input terminal of 6. Element 1006
The output signal 1007 of is not connected anywhere.

Although the virtual input element 1010 is added to FIG. 10B as described above, the structure of other circuits is the same as that of FIG. 10A. The unique name of the virtual input element 1010 is G0. The element 1014 has two input terminals 0 and 1, and each of the virtual input element 1010 has 0 input terminal.
No. 1 output terminal and No. 1 output terminal are connected via signal lines 1011 and 1012. Element 1016 is also 0
No. 1 and No. 1 input terminals, each of which is an element 101
The No. 4 output terminal and the No. 2 output terminal of the virtual input element 1010 are connected via signal lines 1015 and 1013. The signal line 1017 connected to the 0th output terminal of the element 1016 is not connected anywhere.

FIG. 11 shows the circuit of FIG.
It is an example expressed based on the data structure shown in FIG. Figure 1
Since the circuit of 0 is composed of three elements including the virtual input element, three data structures of the type 111 are required.

Reference numeral 1101 represents a virtual input element.
The top address for storing the information is set to 0. 110
2 is a number for identifying the element type and stores a value (here, 0) corresponding to the virtual input element. 1103 stores G0 which is a unique name of the element. 1104 represents the number of input terminals of the virtual input element. Since there is no input terminal in the virtual input terminal, 1104 is 0, and the pointer 1105 to the pointer list of the connection destination of the input does not point anywhere. 1106 stores the number of output terminals of the virtual input element, which is 3.

Reference numeral 1107 stores a pointer to the connection destination pointer list 1109 for the output of the virtual input element. 110
9 has three elements equal to the number of 1106, one element being three fields, 1113, 1114, 11
It consists of fifteen.

The number of elements connected to the output is stored in 1113. Since each output of the virtual input element has one output destination, all three values of 1113 are 1. 1114
Stores a list of pointers (start addresses) to areas for storing information of the elements connected to the output. Since the 0th output of the virtual input element is connected to the element G1, the head address 6 for storing the information is stored in 1116. Similarly 11
Also, 20 is stored in 6 and 1124 is stored in 12. In 1115, the output value of each output terminal and the delay time are stored for each delay type. In this example, two types of delay are handled, so 1117,1
Each of 121 and 1125 has two elements.

Each element is 1118, 1119 (or 1
122, 1123, or 1126, 1127) and 1118 (1122, 1126)
The output value is stored in and the delay time is stored in 1119 (1123, 1127). Here, since the output value of the virtual input element, that is, the initial value of the input terminal of the circuit is set to 0, 1118,
The values of 1122 and 1126 are all 0. Further, since there is no input terminal in the virtual input element, there is no delay time from input to output. Here, 1119, 1123,
The delay value of 1127 is temporarily set to 0.

Reference numeral 1131 represents the element G1. 11
32 stores 11 representing the element type of AND. 1133
A unique name G1 of the element is stored in. 1134 stores 2 which is the number of input terminals of the element. 1135 is an area 113 for storing a list of pointers to connection destinations of element inputs
The pointer to 8 is stored. 1138 has elements equal to the number of input terminals of the element. One element is 1141,11
It consists of two fields of 42. Reference numeral 1141 is a pointer that points to an area for storing information on the element of the connection destination. Since both inputs of G1 are connected to the virtual input element, the leading address 0 is stored. 1142 stores the output terminal number of the element to which the input is connected.

Since the input of G1 is connected to the 0th output terminal and the 1st output terminal of the virtual input element, 0 and 1 are input to 1142.
To store. 1136 stores the number 1 of output terminals of the element G1. In 1137, the pointer to the connection destination pointer list 1139 of the output of the element G1 is stored. 1139 has a number of elements equal to the number 1 of output terminals. 1143 stores the number 1 of elements to which the output is connected. 1144 stores the start address of the area for storing the information of the element connected to the output. The head address 12 of the element G2 connected to the output of the element G1 is stored in 1144. 1145 stores a pointer that points to an area 1147 that stores an output value and a delay value.
1147 has an element equal to the number 2 of delay types. The output value 1148 stores the initial value 0. The delay value 1149 stores the delay times 3 and 5 of the element G1.

Reference numeral 1161 represents the element G2. 11
62 stores 21 representing the element type of OR. A unique name G2 of the element is stored in 1163. In 1164, 2 which is the number of input terminals of the element is stored. 1165 is an area 1168 for storing a list of pointers to connection destinations of element inputs
Stores a pointer to. 1168 has elements equal to the number of input terminals of the element. Reference numeral 1171 is a pointer that points to an area for storing information of the element of the connection destination, and the input of G2 is the element G.
Since it is connected to 1 and the virtual input element, its head addresses 6 and 0 are stored. 1172 stores the output terminal number of the element to which the input is connected. Since the input of G2 is connected to the 0th output terminal of G1 and the 2nd output terminal of the virtual input element, 1
0 and 2 are stored in 172. 1166 stores the number of output terminals of the element G2, that is, 1. A pointer to the connection destination pointer list 1169 of the output of the element G2 is stored in 1167. 1169 has the number of output terminals, that is, the number of elements equal to 1. 1173 stores the number 0 of output connection destination elements. Since 1174 has no element connected to G2, nothing is stored. 1175 stores a pointer pointing to an area 1177 for storing an output value and a delay value. 1177
Has an element equal to the number 2 of delay types. Output value 117
8 stores the initial value 0. The delay value 1179 stores the delay times 2 and 4 of the element G2.

FIG. 12 is an explanatory diagram of an example of a test vector given at the time of simulation. The test vector 1200 in FIG. 10A is the input terminals 1001, 100 of the circuit.
2,1003. 1001 changes from 0 to 1 at time 2, and 1002 changes from 0 to 1 at time 5.
Changes to. 1003 does not change. When the information of this test vector is stored in the data structure of FIG.
It becomes like (b). 1201 is test vector storage information 502, and 502 is 503, 1203 is 504, 1204.
Respectively correspond to 505. At times 1202, times 2 and 5 at which the signal changes are stored. An input terminal number, that is, output terminal numbers 0 and 1 of virtual input elements corresponding to 1001 and 1002 are stored in 1203. A value to be propagated, that is, 1 is stored in 1204.

FIG. 13 shows an example of the observation cycle and observation element information used in the output value comparison processing shown in FIG. Observation start time XS1301 is time 12, observation period XP1302 is 2
It is 0. Also, the element to be observed is the pointer value 6 (130
The element G1 of 4) has an output terminal with the number 0 (1305) and the pointer value 12 (1304) has an output terminal of the number 0 (1305) of the element G2.

14 to 27, the progress of the simulation will be described in time sequence. Further, the simulation is performed until time 15 which is the range shown in FIG.

According to the processing of FIG. 4, the simulation is started with the time XT set to 0. 403 to 406 in FIG.
Does nothing if there is no test vector or event propagating at time XT. At 407, the time XT is advanced by one. Since nothing is registered in the time wheel at the initial stage, the loop 402 in FIG. 4 idles until the time XT, which is the time at which the first test vector propagates, becomes 2.

At time 2, the first element of the test vector information 1201 in FIG. 12B is the target of the test vector addition processing 403 in FIG. By adding the test vector shown in FIG. 5, two events equal to the number of types of delay are created from one test vector element,
Added to the time wheel. FIG. 14 shows the event added in the process 403 at time 2. The event registered at 513 in FIG. 5 is the time 2 (1
202) is the signal propagation time (1404, 1414), and the start address 0 of the virtual input element is the signal propagation element (1405, 1).
415), the input number 1203 of the test vector element is the propagation output (1406, 1416), the propagation value 1204 of the test vector element is the propagation signal value (1407, 1417),
Numbers 0 and 1 are the delay type numbers (1408, 1409). Since the event whose time is 2 is registered in the time wheel, the event propagation processing 404 of FIG. 4 is performed.

In the event propagation processing shown in FIG. 6, the two events at time 2 shown in FIG. 14 are targeted. In the process 613 of FIG. 6, one event is extracted, and in 614, the signal value is propagated to the output of the element. Event 14 in the processing of 614
In the case of 02, the element having the value 0 of 1405 as the head address, that is, the 0th output terminal of the value 1406 of the virtual input element 1101, the output corresponding to the 0th delay type of the value 1408. Value, that is, 11 in FIG.
Change the first element of 18 to 1 which is the value of 1407.
Subsequently, in the processing of 615 of FIG. 6, a list of elements connected to the 0th output terminal is stored in the output destination connection element information 602.
Since there is one element connected to the 0th output and its head address is 6, the output destination connection pointer 603 of the output destination connection element information is 6. The delay type number 604 is 0.
The same process is performed for the event 1412.

As a result, as for the information of the virtual input element, the output value 1518 of the 0th output terminal changes to 1 as shown in FIG.

As shown in FIG. 16, the output destination connection element information has an output destination connection pointer value of 6 and a delay type number of 0.
Two elements of 1 and 1 are stored. Subsequently, the element output evaluation processing at time 2 and 405 in FIG. 4 are performed.

In the element output evaluation processing shown in FIG. 7, the processing of 703 to 707 is repeated for the number of elements of the output destination connection element information. For each output terminal of the element pointed to by the output destination connection pointer of the output destination connection element information, a new output value Vk is calculated based on the input signal value of the element and the type of the element (step 70).
4).

In the case of the first element 1602 in FIG. 16, the output destination connection pointer value 6 is 1131 (element G1) in FIG.
Corresponding to. The number of input terminals of 1131 is 2 (1134)
Then, the connection destinations are the output number 0 terminal of the element pointer value 0 and the output number 1 terminal of the element pointer value 0 (1138).
1141 and 1142). Therefore, regarding the 0th output terminal and the 1st output terminal of the information of 1101 (virtual input element) whose element pointer value is 0, the delay type number (1604) th (0th) of the first element 1602 Refer to the output value. The output value is 0 at time 2 as shown in FIG.
The 0th output value of the 1st output terminal is 1, and the 0th output value of the 1st output terminal is 0. Further, the element type identification number 11 of the element pointed to by the output destination connection pointer of the first element 1602
(1132) That is, when the logical product operation is performed on the input values 0 and 1 from the logical product AND, the new output value Vk becomes 0. 7
0 which is Vk at 05 and the current output value, that is 0 of 1131
0, which is the 0th output value (0th of 1148) of the No. output terminal, is compared. In this case, both values are equal, so 7
Do not do 06.

Similar processing is performed for the second element 1602 in FIG. Also in this case, Vk is 0, the current output value is 0, and 706 is not performed. As a result, no new event is registered in the element output evaluation processing at time 2.

In the output value comparison process 406 in FIG. 4, the current time is compared with XS and XP in 811 as shown in FIG. As shown in FIG. 13, the XS value 12 is the current time.
Since it is larger than (XT) 2, processing after 812 is not performed.
Up to this point, the processing of 403 to 406 at time 2 ends, and the time XT becomes 3 at 407.

At time 3 and time 4, there is no test vector or event to propagate, so nothing is done.

At time 5, the test vector information 12
The second element of 01 is the target of the test vector addition processing 403. Similar to the process at time 2, the two events shown in FIG. 17 are registered in the time wheel. In the event propagation processing 404, the first output terminal of the virtual input element is shown in FIG.
Two events are propagated. The element information updated as a result is shown in FIG. The part 1822 of FIG. 18 is updated and changes from 0 to 1. Further, two pieces of output destination connecting element information shown in FIG. 19 are created. The content of this information is time 2
It is exactly the same as the output destination connection element information in FIG.

Subsequently, the element output evaluation processing at time 5,
405 of FIG. 4 is performed. This processing is also performed in the same manner as at time 2, but at time 5, the delay type number (1904) th (0th) output value of the first element 1902 is referred to.

As for the output value, as shown in FIG. 18, the 0th output value of the 0th output terminal is 1, and the 0th output value of the 1st output terminal is also 1. About input values 1 and 1 11 (113
2) That is, when the logical product AND operation is performed, the new output value Vk becomes 1, which is different from the current output value 0, and the event registration processing is performed at 706.

FIG. 20 shows information on events registered. At the current time 5 (XT), 19th of the k-th output terminal
Delay type number (1904) th of the first element of 02
Signal propagation time 2 is 8 with 3 added, which is the (0th) delay value
The value 6 of the output destination connection pointer indicated by 004, 1903 is targeted for the signal propagation element 2005, the output terminal of No. 0, so 0 is propagated output 2006, and the new output value Vk (value is 1) is propagated signal value 2007, 1904. The delay type number indicated by is the delay type number 2008. The propagation time is the delay type number (1904) th (1st) delay value of the second element of 1902, which is the same as the next event, but 5
Becomes 10, and the delay type number also becomes 1. Similarly to the case of time 2, the output value comparison processing at time 5 and 406 of FIG. 4 are not executed because the condition of 811 of FIG. 8 is not satisfied.

At time 6 and time 7, there is no test vector or event to propagate, so nothing is done.

At time 8, test vector addition processing is not performed because there is no corresponding test vector information. 20 of FIG. 20 registered at time 5 in the event propagation processing
Propagate 02 event. Event 2002 is an event in which the output value of the 0th delay number of the 0th output terminal of the element (G1) whose head address is 6 is 1.

FIG. 21 shows the element information updated by the event 2002. The portion 2148 in the figure is the update portion. Further, the output destination connection information 2202 shown in FIG. 22 is created. 2203 stores the head address 12 of the element (G2) connected to the 0th output terminal of G1. 2204
Stores the delay type number 0 of the event 2002. The element output evaluation processing at time 8, processing 405 in FIG. 4 is performed for the element (G2) of the head address 12. 11 of FIG.
From the information of 68, the two input terminals of the element with the starting address 12 must be connected to the 0th output of the element with the starting address 6 (G1) and the 2nd output of the element with the starting address 0 (virtual input element). I understand. Referring to the output value of the 0th delay type number stored in 2204 of those outputs, the 0th output value of G1 is 1 (FIG. 21), and the 2nd output value of the virtual input element is It is 0. Further, since the element type identification number of G2 is 21, that is, the logical sum OR, Vk is 1 and 0.
Becomes the logical sum of 1.

At time 0, 0 of output terminal 0 of G2
Since the second output is 0 and does not match Vk, the event 2302 shown in FIG. 23 is generated. Event 2302 is
The current time 8 is added with the 0th delay time 2 of the 0th output terminal of G2, 10 is the propagation value 2304, the start address 12 of the element information of G2 is the propagation element 2305, the output terminal number 0.
A propagation output 2306, a Vk value of 1 is a propagation signal value 2307,
The delay type number of 2204 is the same as the delay type number 2
308. The output value comparison process at time 8 is also not executed because the condition 811 in FIG. 8 is not satisfied.

At time 9, there is no test vector or event to propagate, so nothing is done.

At time 10, the event created at time 5, event 2012 and the event created at time 2302
Propagates. As a result, the portions 2448 and 2478 in FIG. 24 are updated. Further, output destination connection information 2 shown in FIG.
502 is created. This is created corresponding to the event 2012, and the output destination connection pointer value 2503 is G
2 is the start address 12 of the element information, and the delay type number 2504 is the delay type number 201 of the event 2012.
It is 1, which is equal to 8. The output destination connection information corresponding to the event 2302 is not created because nothing is connected to the output of the element G2 targeted by the event 2302. In the element output value evaluation processing G2 corresponding to the output destination connection information 2502
The first new output value Vk of the 0th output terminal is calculated. This value is obtained as 1 from the input values 1 and 0 and the element type number 21 (logical sum OR).

Since Vk is different from the current output value 0,
The event 2602 shown in 6 is created. Event 26
02 propagates 14 by adding the first delay value 4 of the 0th output terminal of G2 to the current time 10 and propagates the start address 12 of the element information at G2, the propagation element 2605, and the output terminal number 0. The output 2606 and the Vk value 1 are used as the delay type numbers 2608 of the propagation signal values 2607 and 2504 as they are. The output value comparison process at time 10 is also not executed because the condition 811 in FIG. 8 is not satisfied.

At time 11, since there is no test vector or event to propagate, nothing is done.

At time 12, neither the propagating test vector nor the event exists, but the output value comparison process is performed because the condition 811 in FIG. 8 is satisfied. At 812, the pointer S is initialized to point to the head element of the observation element information (1306 in FIG. 13 in the example). In the loop 813, the processing of 814 to 822 is repeated for all the elements of the observation element information. The first element of 1306 compares the output value of the element whose start address (1304) of the element information is 6, that is, the 0th output terminal (1305) of G1 with respect to all the delay types of the output terminal. From 2447 in FIG. 24,
No. 0 output value of G1 at time 12 is No. 0 delay, 1
It can be seen that the delay numbers are 1 and the values are the same (after time 10, there is no event propagation, so the output value of the element has not changed). On the other hand, the element next to 1306 is the element whose start address (1304) of the element information is 12, that is, the 0th output terminal (1305) of G2. In this case, from 2477 of FIG. 24, 0 of G2 at time 12 is obtained.
It can be seen that the 0th output value is different from the 0th delay being 1, and the 1st delay being different from 0. If the values are different, 820 in FIG.
Since the condition of is satisfied, the process of 821 is performed. In 821, at time 12, the fact that there is a mismatch in the output of the 0th element G2 is output.

At time 13, since there is no propagating test vector or event, nothing is done.

At time 14, the event created at time 10, 2602 in FIG. 26, propagates. As a result, the portion 2778 in FIG. 27 is updated. But event 2602
Since nothing is connected to the output of the target element G2, output destination connection information is not created, and element output evaluation processing is not performed. The output value comparison process is not performed because the condition 811 is not satisfied.

At time 15, there is no propagating test vector or event, so nothing is done. At time 15
Since it is the simulation end time, the loop of 402 in FIG. 4 is ended, and the simulation processing shown in FIG. 4 is ended.

The result of the above simulation is shown in FIG. The output value of delay number 0 of output terminal 0 of G1 changes to 1 at time 8 in response to the input change at time 5,
The output value of delay number 1 of output terminal 0 of G1 changes to 1 at time 10 corresponding to the input change at time 5. Also, the output value of the delay number 0 of the output terminal 0 of G2 is the time 8
Changes to 1 at time 10 in response to the input change of
The output value of delay number 1 of output terminal 0 of No. 2 changes to 1 at time 14 corresponding to the input change at time 10. As a result of the output value comparison processing at time 12 (2801), G
The output value of 1 is the same for both, but (2802) G
The output value of 2 is different from 1 and 0 (2803), and the result is reported to the user of the simulation.

According to the present embodiment, multiple delay simulations in which a plurality of types of delays are assigned to one element are performed simultaneously, and there is a discrepancy in the output values for each type of delay with respect to the observation time and the observation element output designated in advance. It becomes possible to find out what to do.

Further, the multiple test logic simulation of the embodiment of FIG. 9 makes it possible to process a plurality of test patterns at the same time.

In the present embodiment, a loop in the test vector addition processing 403, the event propagation processing 404, the element output value evaluation processing 405, and the output value comparison processing 406, 51
Since 1,612, 702, and 813 are independently processed in each loop, the loops can be expanded and parallel processing can be performed in a vector computer or the like.

[0088]

According to the present invention, it is possible to simultaneously process a logic simulation assuming an arbitrary type of delay for each element, and it is possible to easily find a malfunction of a logic circuit due to delay variation. ． Conventionally, it was necessary to execute a logical simulation every time the type of delay was changed, but in the present invention, a plurality of types of delay can be collectively simulated, so that the time and effort for starting the simulation can be saved.

Further, according to the present invention, it is possible to simultaneously perform a logical simulation on a plurality of test vectors simultaneously, and in this case as well, it is possible to save the trouble of starting the simulation.

Further, by simultaneously processing the logical simulations with a plurality of delays, the number of events that can be processed in parallel at the same time increases, so that the speedup by parallel processing is faster than repeating the logical simulation with a single delay. The effect of becomes large.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a conventional data structure for logic simulation.

FIG. 3 is an explanatory diagram of a delay model of an element.

FIG. 4 is an explanatory diagram of a logic simulation process according to the embodiment of this invention.

FIG. 5 is an explanatory diagram of test vector addition processing according to the third embodiment of this invention.

FIG. 6 is an explanatory diagram of event propagation processing.

FIG. 7 is an explanatory diagram of element output evaluation processing.

FIG. 8 is an explanatory diagram of output value comparison processing according to the second embodiment of this invention.

FIG. 9 is an explanatory diagram of test vector addition processing according to the fourth embodiment of this invention.

FIG. 10 is a logic circuit diagram for explaining the operation of the embodiment of the present invention.

11 is an explanatory diagram of element information of the circuit of FIG.

FIG. 12 is an explanatory diagram of an example of a test vector.

FIG. 13 is an explanatory diagram of an example of an observation cycle and observation element information.

FIG. 14 is an explanatory diagram of event information added at time 2.

FIG. 15 is an explanatory diagram of element information changed at time 2.

FIG. 16 is an explanatory diagram of output destination connection information created at time 2.

FIG. 17 is an explanatory diagram of event information added at time 5.

FIG. 18 is an explanatory diagram of element information changed at time 5.

FIG. 19 is an explanatory diagram of output destination connection information created at time 5.

FIG. 20 is an explanatory diagram of event information created at time 5.

FIG. 21 is an explanatory diagram of element information changed at time 8.

FIG. 22 is an explanatory diagram of output destination connection information created at time 8.

FIG. 23 is an explanatory diagram of event information created at time 8.

FIG. 24 is an explanatory diagram of element information changed at time 10.

FIG. 25 is an explanatory diagram of output destination connection information created at time 10.

FIG. 26 is an explanatory diagram of event information created at time 10.

FIG. 27 is an explanatory diagram of element information changed at time 14.

FIG. 28 is an explanatory diagram of a simulation result.

[Explanation of symbols]

101 ... Time wheel, 102 ... Event, 103 ...
Link pointer, 123, 127, 132, 135 ... Number of elements.

Claims (5)

[Claims] 1. Event information includes a signal propagation time, an identifier of element information in which the signal propagates, an identification number of an output terminal in which the signal propagates, and a value of the signal in which the signal propagates. ID number, device unique name, number of input terminals, list of connection destination pointers and output terminal numbers for each input terminal, number of output terminals, number of connection destinations for each output terminal and list of connection destination pointers. In the logic simulation method of simulating a logic circuit according to the information, as the information of the event, the identification number of the delay type,
As the element information, each output terminal has the same number of output values as the number of delay types and element delay values, and the output value and element delay value corresponding to the identification number of each event delay type when the simulation is executed. Regarding the above, a logical simulation method characterized by performing the propagation of an event and the generation of a new event associated with a signal value change. 2. The device according to claim 1, which has information for identifying an element to be observed and an observation output terminal of the element and observation period information, and all of the designated observation output terminals at a simulation time according to the observation period information. A logic simulation method that determines whether all output values are the same with respect to the type of delay of, and outputs the result. 3. The logic simulation method according to claim 1, wherein an event having identification numbers of all delay types is generated corresponding to a given test vector. 4. The logic simulation method according to claim 1, wherein an event having identification numbers of different delay types is generated corresponding to a plurality of given test vectors. 5. A logic simulator for performing the logic simulation method according to claim 1 on a parallel computer having a plurality of arithmetic mechanisms.