JP2855603B2 - Work station simulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a workstation simulator for verifying a logic circuit pattern created based on a specification at a mounting board level when an integrated circuit is created. [Prior Art] In order to develop a mounting board composed of a plurality of integrated circuits (hereinafter referred to as ICs), as shown in FIG.
When developing an IC (C) that incorporates (A) and (B) and obtains the expected value based on the specifications of the mounting board 2, a logic circuit pattern that meets the specifications is designed and a workstation simulator is used. Take in 4. In order to verify such a logical pattern, a workstation is brought into contact with the input and output terminals of an IC (C) to be developed on the mounting board 2, and then an input signal is applied to the mounting board 2. Thus, the logic pattern in the workstation simulator 4 substitutes for the IC (C), an operation based on the logic pattern is executed, and the result is output to the mounting board 2. In this way, by comparing the output data output from the mounting board 2 with the expected value based on the specification,
The verification of the logic circuit was performed on the mounting board. [Problems to be Solved by the Present Invention] However, the processing speed of the ICs (A) and IC (B) of the mounting board 2 is as high as nano-order, whereas the virtual IC
The processing speed of the workstation simulator 4 as a substitute for (C) is a low speed of the order of msec, and it takes a lot of time to verify various input patterns on a mounting board. That is, in the workstation simulator 4,
Since the logic calculation program based on the logic pattern is executed and the logic is calculated, it takes much longer than the actual IC, and especially in the case of VLSI, unrealistic time is required. , There was a huge problem in efficiency. The present invention has been made in view of the above situation, and in a workstation simulator for verifying a logic circuit pattern at a mounting board level, logical operation processing outputs are sequentially stored in a memory based on reset IN and reset OUT signals. A work which has an operation output data memory means for storing and operates a virtual logic circuit based on the operation output data, so that a logic circuit pattern including a mounting board and a virtual logic circuit can be verified at high speed. A station simulator is provided. [Means for Solving the Problems] The present invention relates to a workstation simulator for performing verification of a virtual logic circuit pattern at a mounting board level, and includes various test circuit patterns A, B, and C stored in a logical operation device 14. .. Are input to the mounting IC of the mounting board 2 and the calculation output data obtained by running the calculation program based on the mounting board 2 is sequentially stored in the calculation output data memory 16. An output data memory means for sequentially calling data stored in the operation output data memory 16 to execute an operation process based on the virtual logic circuit pattern, and obtaining the obtained virtual operation output data and the expected memory stored in the logical operation device 14 in advance. Verification means for verifying the logic gate by comparing with the value output data. This is a featured workstation simulator. EXAMPLES Hereinafter, the present invention will be described in detail with reference to the drawings. As shown in FIG. 1, the workstation simulator of the present invention comprises an input / output device 22, a logical operation device 14, an operation output data memory 16, a logic level signal → mounting voltage signal converter 10, a mounting voltage signal → logic level signal. It is composed of a conversion device 12 and the like. The input / output device 22 includes a display, a keyboard, and a disk drive, and inputs an expected value, processing means, and the like, and outputs and displays a logical pattern. The logical operation device 14 executes a logical operation program for various input patterns based on a logical circuit pattern, and obtains logical output data. The operation output data memory 16 according to the present invention stores data operated by the logical operation device sequentially for each process of the program. Note that the logic level signal → mounting voltage signal conversion device 10 and the mounting voltage signal → logic level signal conversion device 12 are configured by performing an eye relation with a photocoupler or using an open collector device. In addition, the mounting board 2 according to the present example includes an IC (A) and an IC (B)
And a virtual IC (C) to be developed in the future (indicated by a dotted line). Next, a specific operation will be described with reference to FIGS. First, an IC to satisfy the input and output test pattern data of the expected value of the mounting board 2 required by the specification
In order to design (C), a logic pattern is designed by a desired method in a workstation simulator. The logical pattern of the virtual IC (C) designed in this way is taken into the logical operation device 14 in the workstation simulator by S1, as shown in FIG. In addition, the expected value input pattern according to the specification by S2,
And the output pattern by means of a disk etc.
Thus, it is input to the memory in the logical expression operation device 14. Then, if necessary, in S3, for example, the memory address a of the logic pattern of the IC (C) input to the memory in the logical operation device 14, the input pattern of the expected value according to the specification, and the memory of the output pattern Address b is a = 0,
Reset to b = 0, a = a + 1, b = b + 1 and return to the origin. Here, an arithmetic output data memory means for sequentially storing the logical arithmetic processing outputs from S4 to S11 in a memory will be described. First, the logical formula arithmetic unit 14 resets the reset IN signal I by S4.
Is output to the mounting board 2 as a reset IN signal I 'via the logic level signal → mounting voltage signal converter 10. Thereafter, input and output of expected values of the mounting board 2 which are input to the input terminals (eight in this example) of the mounting board which are also stored in advance in the logical operation device 14 are often used to satisfy the test pattern data. Of the 4th test pattern
The input data signal P of 10011000 which is the first test pattern A shown in the figure is input to the mounting board side by S5. As a result, the IC built on the mounting board 2
(A) In the IC (B), the circuit is processed by S6. Then, the data signal T input to the IC (C) to be developed, which is created in the logical operation device 14 and is to be developed.
In step S6, the processed data signal T 'which has been subjected to the circuit processing by the IC (A) and IC (B) on the mounting board 2 is converted into H by the photocoupler of the mounting voltage signal → logic level signal converter 12 in S7. The logic level signal is converted from (high) and L (low) levels as logic levels of 0 and 1 data, and is input to the logic operation unit 14 together with the clock signal OUT1 at S8. As a result, based on the data signal T, which is input data from the mounting board, the appropriately assigned A1 of the logic program of the IC (C) stored in the logical operation unit 14
A1000 are sequentially processed in S9, and the operation output data thus calculated is stored in the operation output data memory 16 in S10 in order at addresses A1 to A1000. In this way, the calculation is repeated until many test patterns A, B, C,... Input to the mounting board 2 are completed in S11, and the results are stored in all the memories 16. Here, the calculation processing programs are divided into A1 to A1000, which are arbitrarily divided in order to make it easy to see the wrong part when verifying a gate error later. Next, the verification means will be described with reference to FIG. First, by pressing the verification start switch from the keyboard of the input / output device 22, the input signals of the mounting board test pattern in the logical operation device 14 are changed to patterns A, B, C,.
・ Successively input by S1. In contrast, IC (A) and IC (B)
The execution processing by the IC (C) by calling the calculated output data from the calculation output data memory 16 is performed in S2. Since the operation output data stored in the operation output data memory 16 is the calculation processing result data stored as described above, it is not necessary to execute the operation program in the verification by this verification means. This enables high-speed processing at the level. As shown in FIG. 1, virtual processing output from the mounting board 2 in S3 by the execution processing by the IC (C) by calling the calculation output data calculated from the calculation output data memory 16 in S2, as shown in FIG. A signal corresponding to a virtual operation output data signal U '(indicated by a dotted line) including an IC (C), and a virtual operation output data signal U ( A signal corresponding to (dotted line display) is output in the logical operation device 14. Next, in S4, the virtual output data signal U in S3 in which the mounting board 2 is operated in this way is compared with the expected value stored in advance in the logical operation device 14 using the output test pattern according to the specification. , Expected value = virtual output data signal U
If it is OK, it means that there is nothing wrong with the gate END
Becomes However, here, if expected value = virtual output data signal U
If not, it means that there is an error in the gate, so immediately stop the processing of the mounting board 2 in S5, project the logical pattern of the stopped location on the display of the input / output device by S6, and move the screen back and forth. The error correction is performed in S7 by a desired method. [Effects] The present invention is as described above.By having operation output data memory means for sequentially storing logical operation processing data in a memory, verification simulation can be performed at the speed of a mounting board level. In addition, by using a photocoupler for the interface between the mounting board and the workstation simulator, it is possible to prevent circuit breakdown due to malfunction.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an overall system according to the present invention;
FIG. 2 is a flowchart showing memory storage of operation processing data, FIG. 3 is a flowchart showing verification, and FIG. 4 is an explanatory diagram showing storage in a memory. 1 mounting board substrate 2 mounting board 4 workstation simulator 10 logic level signal → mounting voltage signal conversion device 12 mounting voltage signal → logic level signal conversion device 14 logical operation device 16 … Calculation output data memory 22 …… I / O device

Continuation of the front page (56) References JP-A-61-129587 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G06F 17/50

Claims (1)

(57) [Claims] In a workstation simulator for verifying a virtual logic circuit pattern at the mounting board level, a test pattern data signal based on various test circuit patterns A, B, C,... An operation output data memory means for inputting to the mounting IC and sequentially storing operation output data obtained by running an operation program based on the mounting board 2 in the operation output data memory 16; The logical data verification is performed by sequentially calling the obtained data and executing the arithmetic processing by the virtual logical circuit pattern, and comparing the obtained virtual arithmetic output data with the expected value output data stored in advance in the logical arithmetic device 14. Workstation simulator having verification means for performing . 2. 2. The workstation simulator according to claim 1, wherein the mounting board 2 and the workstation simulator 4 are connected by an optical interface such as a photocoupler.