JPH01226077A - Automatic correction method for delay library - Google Patents

Abstract

PURPOSE:To automatically correct a delay library by using various programs for correcting the delay library. CONSTITUTION:Plural processing programs such as a logic circuit conversion program, an element value/shape value calculating program and an automatic circuit data generating program and a delay value calculating program are used. After storing prescribed correcting information at least in a circuit library life 13 and a layout library file 14 out of a logical library file 12, the files 13, 14, a model parameter file 15, and a test pattern file 11 through expert designer's operation, formation of a circuit simulator input data, the formation of analysis information of circuit simulator input data based on a circuit simulator, the formation of delay value information corresponding to the prescribed correcting information, and the storage of the delay value information in a delay library file 25 are automatically executed. Since manual operation is unnecessary on the way of processing and the delay library can be automatically corrected, an operation miss can be removed and the TAT of design can be sharply abbreviated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for automatically modifying a delayed library, which can automatically modify a delayed library by using various programs for modifying the delayed library. .

[Prior Art] Conventionally, when creating a delay library, a circuit library, a layout library, and a model parameter library were created by each specialized designer.

That is, a circuit designer creates a circuit connection description based on the logical connection description stored in the logic library and stores it in a circuit library file, and a layout designer creates a circuit element from a layout based on the logical connection description. Element values and pattern shape values are calculated and this information is stored in a layout library file. Furthermore, the process engineer calculates model parameters from the measured values by parameter fitting and stores them in a model parameter library file.

Using the circuit library file, layout library file, and model parameter library file obtained in this way, a circuit simulator input data file is manually created and the circuit simulator is started. Then, from the resulting rising waveform and falling waveform, the rising delay value and falling delay value are manually read, respectively, and these pieces of information are stored in a delay library file.

Here, if you want to modify the contents of the delay library file due to a change in design items, the circuit library file,
Predetermined modification information is stored in the layout library file, model parameter library file, and logical library file if necessary. After this,
In the same way, manually create an input data file for the circuit simulator, start the circuit simulator, and then use the rising delay value and falling delay value (both corrected values).
and store these modified information in respective delayed library files.

[Problems to be Solved by the Invention] However, the above-mentioned conventional technology has the following problems.

That is, when modifying the contents of the delay library file as desired, create an input data file for the circuit simulator, and calculate the rising delay value and falling delay value from the rising waveform and falling waveform obtained by starting the circuit simulator. Each reading is performed manually. For this reason, operational errors are likely to occur, and the design T.
It is difficult to shorten AT (Turn Around Time).

The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide a method for automatically correcting a delayed library that can shorten the TAT by using various programs for correcting the delayed library.

[Means for solving the problem] The method for automatically correcting a delayed library according to the present invention includes (a)
(b) storing predetermined modification information in at least the circuit library file and the layout file among the logic library file, circuit library file, layout library file, model parameter file, and test pattern file; (c) using a processing program to create circuit simulator input data based on descriptive information of each of the six types of files; (c) activating a circuit simulator using the circuit simulator input data as input;
(d) using a delay value calculation program to create delay value information corresponding to the predetermined correction information based on the analysis information of the circuit simulator and the description information of the test pattern file; and storing this delay value information in a delay library file.

[Operation] According to the present invention configured as described above, by using a plurality of processing programs and delay value calculation programs, a logic library file, a circuit library file, and a layout library file.

After predetermined correction information is stored in at least the circuit library file and the layout library file among the model parameter file and the test pattern file through the operations of each specialized designer, the circuit simulator input data creation 2 Creation of analysis information for the circuit simulator input data by the circuit simulator, creation of delay value information corresponding to the predetermined modification information, and storage of this delay value information in a delay library file are automatically performed.

For this reason, the delay library can be automatically corrected without the need for manual intervention during processing, so that operational errors can be eliminated and the design TAT can be significantly shortened.

[Example] Hereinafter, an example of the present invention will be specifically described with reference to the accompanying drawings.

FIG. 1 is a flowchart illustrating each processing step of the embodiment, and P1 to P6 indicate each step of this flowchart.

First, in Pl, a test pattern library file (A) 11. Logical library file (B)12. Circuit library file (c)
13. A layout library file (D) 14 and a model parameter library file (E) 15 are respectively created. Note that the delay value has a plurality of specific values defined by a certain rule.

In this case, in the circuit library file (c) 13, the contents of the circuit connection description are modified in accordance with the defined delay value for modification.

Furthermore, in the logical library file (B) 12,
The contents of the logical connection description that correspond one-to-one to the contents of the circuit connection description corrected in the circuit library file (c) 13 have been corrected. Note that this modification in the logical library file (B) 12 is not a substantial change in its contents. Similarly, in the layout library (D) 14, description contents corresponding to the contents of the modified circuit connection description, such as element values such as R and C, and pattern lengths (
L) 2 Shape values such as width (W) have been modified.

The test pattern file (A) 11 stores logical signals for determining whether the logical connection description of the logical library file (B) 12 is normal. Also,
In the model parameter library file (E) 15,
Information obtained in advance from process information, ie, various device parameters for describing device operations, etc., is stored. The description content of this model parameter library file (E) 15 will not be modified unless the manufacturing process is changed.

At P2, the logical connection description from the logic library file (B) 12 is extracted by the logic/circuit modification program 16, and this extracted information is converted based on the circuit connection description of the circuit library file (c) 13. The further converted information is stored in the circuit connection file (F
)18.

In addition, in P3, the element value/shape value calculation program 17 generates information that corresponds one-to-one with the logical connection description in the logic library file (B) 12, such as element values such as diffused resistance and diffused capacitance, and the pattern length of the MOS transistor ( L)
9. Shape values such as width (W) are extracted, and this information is stored in the element value/shape value file (G) 19. In addition,
Of course, these steps P2 and P3 can be processed in parallel.

Next, in P4, each predetermined information stored in the circuit connection file (F) 18 and the element value/shape value file (G) 19, the model parameter library (E) 15
The circuit data automatic generation program 20 is started by inputting the information obtained in advance from the process information in the process information and the information of the test pattern file (A) 11 corresponding to the logical connection description of the logical library file (B) 12, respectively. As a result, predetermined circuit data, ie, circuit simulator input data, is stored in the circuit simulator input data file (H) 21.

Next, in P5, the circuit simulator 22 is started by outputting the predetermined information of the circuit simulator input data file (H) 21, and the analysis result is stored in the analysis result file (1) 23.

Furthermore, in P6, the delay value calculation program 24 is started to calculate a desired delay value (corrected value) by inputting each information of the analysis result file (1) 23 and the test pattern file (A) 11, and this calculation The delay value thus obtained is registered in the delay library file (J) 25 corresponding to the logical library file (B) 12.

[Effects of the Invention] As described above, according to the present invention, in order to modify a delay library, multiple processes such as a logic/circuit conversion program, an element value/shape value calculation program, and a circuit data automatic generation program are performed. Since the program and delay value calculation program are used, logic library files, circuit library files, and layout library files.

After predetermined correction information is stored in at least the circuit library file and the layout library file among the model parameter file and the test pattern file through the operations of each specialized designer, the predetermined correction information is stored by the various programs. Delay information (correction value) corresponding to the information is automatically created and further stored in the delay library file.

For this reason, the delay library can be automatically corrected without the need for manual intervention during processing, so that operational errors can be eliminated and the design TAT can be significantly shortened.

Furthermore, since modification information corresponding to delay values defined by certain rules can be used, various processes for modifying the delay library can be easily executed.

[Brief explanation of the drawing]

FIG. 1 is a flowchart showing one embodiment of the present invention.

Claims (1)

[Claims] (1) (a) Storing predetermined modification information in at least the circuit library file and the layout library file among the logical library file, circuit library file, layout library file, model parameter file, and test pattern file, respectively; b) After this, using multiple processing programs, the above 6
(d) creating input data for a circuit simulator based on descriptive information of each type of file; (c) starting a circuit simulator using the input data for the circuit simulator as input; and (d) ) A delay value calculation program is used to create delay value information corresponding to the predetermined correction information based on the analysis information of the circuit simulator and the description information of the test pattern file, and this delay value information is stored in a delay library file. A method for automatically correcting a delayed library, the method comprising: