JPH1063699A - Semiconductor design verify rule file automatic generator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable the generation of a rule file even for any person excepting for rule file preparation specialists by inputting the characters of data required for generating the rule file for verifying the design rules of semiconductor layout design, and translating the inputted data into the grammar of rule file. SOLUTION: The data of layer L1, width W and value 0.8μm, for example, are inputted to an automatic translation program 7 as a factor (the layer name of a graphic A), factor (width/gap) 4 and factor (verification value) 5 of a template file 1. At the automatic translation program 7, the grammar for verifying the width of the graphic is selected, the layer name 2 and verification value 5 of the graphic A are applied as its parameters and translated into the rule of design rule check, and a rule file 8 is outputted. Thus, the template is defined for inputting the design rule to be used for the design rule check of layout, the rule is inputted according to this template, and a computer is let automatically generate the rule file.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a CAD (Computer).
Aided Design)
Design rule check for layout design (hereinafter DRC)
) For generating a rule file.

[0002]

2. Description of the Related Art FIG. 9 is a block diagram showing a conventional method of creating a rule file for performing a design rule check (DRC) of a layout design from a semiconductor layout design verification rule file (hereinafter, referred to as a rule file). In the figure, reference numeral 71 denotes a specification of a design rule, 72 denotes a grammar of a DRC rule, and 73 denotes a rule file.

FIG. 10 is a block diagram showing a conventional method of creating a rule file for performing a comparison between a circuit diagram and a layout diagram (layout versus schematic, hereinafter referred to as LVS) in a rule file.
In the figure, 81 is a symbol specification of a circuit diagram, 82 is a layer configuration specification in a device layout diagram, 83
Is a grammar of LVS rules, and 84 is a rule file.

As shown in FIGS. 9 and 10, when a conventional rule file creation method is used, a complex grammar such as a design rule check (DRC) grammar or a layout verses schematic (LVS) grammar is used. You have to write the rules with full effort. 9 and 10, how complex the grammar is,
The design rule check (DRC) will be described.

First, (1) a function (command) specific to layout verification must be used. As an example, to check whether the interval between two figures drawn on layer 1 is x or more, check (Layer 1, separa
option <x, “Output message at the time of error”)
.. Described as Equation 1. For the “separation” part,
The description changes depending on the width, margin, overlap, width of the concave portion, and the like.
Next, in the case of (2) handling a composite figure, the "layer 1" part of the above-described equation 1 is used as a variable, and a graphic operation is performed. The graphic calculation method is also a function unique to layout verification. For example, to calculate the sum of figure A and figure B, FigOr (layer name of figure A, layer name of figure B)
It is described. Similarly, differences in shapes, overlapping portions of shapes,
Also, a specific function is used to obtain a figure enlarged or reduced by a certain amount. Furthermore, (3) the case of handling a conditional figure is the same as (2). For example, (a) Figure A
Is a layer 1 and does not overlap the figure of layer 2; (b) a figure A is a layer 1 and partially or entirely overlaps a figure of layer 2;
Is the layer 1 and is included in the figure of the layer 2,
Etc., always use a specific function.

As described above, the method of describing the rules of the design rule check (DRC) is a combination of the graphic operation and the check. In order to apply it to a general IC layout design, it is necessary to describe the rules making full use of these. The disadvantage is that it becomes very complicated.

[0007]

Since the conventional rule file is created as described above, it must be created by a limited number of specialized engineers, and the above grammar is not well understood. When a semiconductor device designer performs a design rule check (DRC) or a layout versus schematic (LVS), it is possible to use a rule file created by a rule file creation expert engineer. At the same time, it was extremely difficult to make it myself. In general, the contents of a rule file differ depending on the process of manufacturing a semiconductor device. However, a general semiconductor device designer performs a design rule check (until a rule file creation specialist creates a rule file). DRC) or Layout Versus Schematic (LVS) cannot be implemented,
The design quality has been reduced.

[0008]

According to the present invention, there is provided an automatic semiconductor design verification rule file generating apparatus for inputting data necessary for generating a rule file for verifying a design rule of a semiconductor layout design. It is characterized in that it has a conversion means for translating the input data into the grammar of the rule file.

In the semiconductor design verification rule file automatic generation apparatus according to the present invention, the data includes a layer name of the verification target graphic stored in the template file, a width of the verification target graphic, an interval of the verification target graphic,
And these verification values.

[0010] In addition, the semiconductor design verification rule file automatic generation device of the present invention provides a rule file for performing a design rule verification of a semiconductor layout design.
It is characterized by having input means for graphically inputting necessary data and conversion means for translating the input data into the grammar of the rule file.

In the semiconductor design verification rule file automatic generation device according to the present invention, the data includes a layer name of the verification target graphic stored in the layout drawing, a width defining the verification target graphic, and an interval of the verification target graphic. , And line segments indicating these verification values.

In addition, the semiconductor design verification rule file automatic generation apparatus of the present invention inputs necessary data of a layout diagram and a circuit diagram into a figure in order to generate a rule file for comparing and verifying a layout diagram and a circuit diagram in a semiconductor design. And a conversion means for translating the input data into the grammar of the rule file.

Further, in the semiconductor design verification rule file automatic generation device according to the present invention, the data includes a device graphic stored in a layout diagram and a circuit symbol of a device stored in the circuit diagram. Things.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an apparatus for automatically generating a rule file for performing a design rule check (DRC) according to the present invention. In the figure, 1 is a template file, and 2 to 6 are elements included in 1. 2 is the layer name of the figure A to be verified, 3 is the layer name of the figure B when verifying the relationship with another figure, 4 is selection of whether the verification item is the width or the interval of the figure, 5 Indicates a verification value, and 6 indicates other conditions. 7 is DRC
A program for automatically generating a rule file 8 is a generated rule file.

FIG. 2 shows an example of entry of the template in FIG. In the figure, 11 is a template, 12 is a verification item number, 13 is a layer name of a graphic A to be verified,
14 is a layer name of the figure B when verifying the relation with another figure, 15 is a selection of whether the verification item is a width or an interval of the figure, 16 is a verification value, 17 is other conditions, and 18 is a condition. One verification item example, 19 and 20 are another verification item example.

Next, the operation will be described. The layer name 13 of FIG. 2 and the layer name 14 of FIG.
Column indicates the target layer name, width or interval 15 indicates the width or interval of the portion to be verified, and verification value 16 indicates the verification value (the minimum value of the normal design rule), condition 1
Other conditions are input in the column of No. 7.

For example, in the example of the verification item 18 in FIG.
This indicates that the minimum value of the width of the layer L1 is 0.8 μm. This example will be described with reference to the block diagram of FIG. 1. Data of the layer L1, the width W, and the verification value of 0.8 μm are input to the automatic conversion program 7 as elements 2, 4, and 5 of the template file 1. In the automatic conversion program 7,
A grammar for verifying the width of the figure is selected, and a layer name 2 and a verification value 5 of the figure A are given as parameters thereof, translated into design rule check (DRC) rules, and a rule file 8 is output.

FIG. 3 is a flowchart showing the flow of processing for automatically generating a rule file according to the present invention.
T1 (reads the coordinates of the designated part), step ST2 (recognizes the graphic layer), step ST3 (whether graphic calculation is necessary), step ST4 (outputs a graphic calculation description), step ST5 (recognizes the type of check) ) And step ST6 (output the description of the graphic check).
As for the graphic calculation, the same calculation as that described in the above-described conventional technique is performed.

In the example of the 19 verification items shown in FIG.
1 indicates that the minimum distance between layer 1 and layer L2 is 1.0 μm. These data are input to the automatic conversion program 7 as elements 2, 3, 4, and 5 of the template file 1 in FIG. 1 in the same manner as in the above example. A layer name 2 of FIG. A, a layer name 3 of FIG. B and a verification value 5 are given as parameters, translated into DRC rules, and a rule file 8 is output.

An example in which a condition is added to the verification target graphic will be described. In the example of 20 verification items in FIG. 2,
If the width of the layer L1 is 2 μm or more in the example of the above 19, it indicates that a condition that the minimum distance between the layer L1 and the layer L2 is 1.5 μm is added. These data are the elements 2, 3 of the template file 1 in FIG.
The automatic conversion program 7 selects the grammar for verifying the width of the figure and the grammar corresponding to the condition 6 as 4, 5, and 6,
The DRC rules are translated by giving the layer name 2 of the graphic A, the layer name 3 of the graphic B, the verification value 5, and the width of the layer L1 of the condition 6 as parameters, and the rule file 8 is output. Note that the verification item 20 is output so as to be prioritized over the verification item 19.

As described above, in the automatic rule file generation apparatus according to the first embodiment, the data of the layer L1, the width W, and the value of 0.8 μm are automatically converted into the elements 2, 4, and 5 of the template file 1 by the automatic conversion program. 7, the automatic conversion program 7 selects a grammar for verifying the width of the figure, and assigns the layer name 2 and the verification value 5 of the figure A as its parameters to check the design rule (DR).
C) is translated into a rule, and a rule file 8 is output.

As described above, the first embodiment defines a template for inputting a design rule to be used for a layout design rule check, inputs a rule in accordance with the template, and causes a computer to automatically generate a rule file. It is. According to the first embodiment, a rule file for design rule check can be automatically generated by inputting necessary information in characters.

Embodiment 2 FIG. Next, a second embodiment of the present invention will be described with reference to FIG. In the first embodiment, the contents of the rule are input in characters. In the second embodiment, a rule file is generated by inputting a figure. FIG. 4 shows the DR in the present invention.
It is a block diagram showing an automatic generation device of a rule file for implementing C. In the drawing, reference numeral 21 denotes a layout diagram, and reference numeral 22 denotes a graphic A to be verified in the layout diagram 21,
Is a figure B to be verified, and 24 is a line segment C that defines a portion to be verified. The graphics 22 and 23 have a layer name 25 as a parameter, and the line segment 24 has a width or interval verification item 26, a verification value 27, and other conditions 28 as parameters. 29 is a rule file automatic generation program for inputting a layer name 25, a verification item 26, a verification value 27, and other conditions 28 and outputting a DRC rule file, and 30 is a generated rule file.

FIG. 5 is an example of the layout diagram created in FIG. In the figure, 31 is a figure drawn on the layer L1, 32 is a figure drawn on the layer L2, 33 is a figure drawn on the layer L1, and 34 is a figure drawn on the layer L2. 35 is a line segment that specifies that the width of the graphic 31 is to be verified, 36 is a line segment that specifies that the space between the graphic 31 and the graphic 32 is to be verified, and 37 is that that the space between the graphic 33 and the graphic 34 is to be verified. Line segment

Next, the operation will be described. In the block diagram of FIG. 4, a figure as shown in FIG. For example, when the width of the figure drawn on the layer L1 is to be verified, the figure 31 is drawn on the layer L1. that time,
The width of the graphic 31 is set to the verification value (minimum value). Then, to specify that the width of the graphic 31 is to be verified, the line segment 3
Enter 5. Also, the figure 31 and the figure 32 of the layer L2
The figure 32 is drawn so that the interval of the pattern becomes a verification value (minimum value), and a line segment 36 is input to specify that this interval is to be verified. Further, as an example in which a condition is applied to the figure drawn on the layer L1, if the width of the figure 33 drawn on the layer L1 is a certain numerical value or more, the figure 33 and the layer L
In the case where the interval between the figures 34 drawn in 2 is different from the interval between the figures 31 and 32, the figure 33 is drawn with the width of the condition and the interval between the figures 33 and 34 is set to the minimum value in that case. , And draw a figure 34. Then, a line segment 37 is input to specify that this interval is to be verified, and a line segment 38 is input to specify that verification is performed under these conditions. Reference numeral 38 denotes a line segment that defines a condition for the width.

The layout diagram 21 created in this way
The information included in the information, ie, the layer name 25 of each figure, the verification item 26 of the width or interval, the verification value 27, and the condition 28 are input, and the automatic generation program 29 selects a grammar for verifying the width of the figure, and Segment 3 with
It translates into DRC rules corresponding to 5 to 37, and outputs a rule file 30.

As described above, in the rule file automatic generation apparatus according to the second embodiment, the layout file 2
The information included in 1, ie, the layer name 25 of each figure, the verification item 26 of the width or interval, the verification value 27, and the condition 28 are input, and the automatic generation program 29 selects a grammar for verifying the width of the figure, The information is translated as parameters into DRC rules corresponding to the line segments 35 to 37, and the rule file 30 is output.

As described above, in the second embodiment, the CA
A graphic is drawn with D, and a computer automatically generates a rule file for design rule check based on the information of the graphic and the supplementary information. According to the second embodiment, a rule file can be automatically generated by inputting necessary information as a graphic.

Embodiment 3 Next, a third embodiment of the present invention will be described with reference to FIG. In the semiconductor layout design verification, in addition to the design rule check (DRC) described in the first and second embodiments, there is a layout versus schematic (LVS). In the third embodiment,
An example of application to LVS will be described. FIG. 6 shows the LV according to the present invention.
FIG. 3 is a block diagram showing a rule file creation device for implementing S. In FIG. 6, 41 is a layout diagram,
42 is a device figure drawn in the layout diagram 41, 43
Is a circuit diagram, and 44 is a symbol placed on the circuit diagram 43. Reference numeral 45 denotes a rule file automatic generation program for outputting an LVS rule file by using the layout diagram 41 and the circuit diagram 43 as input, and reference numeral 46 denotes an output rule file. FIG. 7 is an example of the layout diagram 41 of FIG. 6, and 51 is a layout diagram of the resistor. FIG. 8 is an example of the circuit diagram 43 of FIG. 6, and 61 indicates a symbol of a resistor.

Next, the operation will be described. First, a device 42 for element recognition is drawn on a layout diagram 41. For example, in the case of a resistor, it is created like the resistor 51 in FIG. Next, a symbol 44 corresponding to the device 42 is shown in the circuit diagram 43.
Put. In the case of a resistor, it is placed like a symbol 61 in FIG. The rule file automatic generation program 45 receives the layout diagram 41 and the circuit diagram 43 as input, and
1 is translated into the grammar of the rule file. Similarly, based on parameters such as the symbol name of the symbol 44 placed on the circuit diagram 43, the information of the symbol 44 is translated into the grammar of the rule file, and the rule file 46 is output.

As described above, in the rule file automatic generation device according to the third embodiment, the layout diagram 4
1 is translated into the grammar of the rule file, and a symbol 4 is similarly created based on parameters such as the symbol name of the symbol 44 placed on the circuit diagram 43.
4 is translated into the grammar of the rule file, and the rule file 46 is output.

As described above, in the third embodiment, a figure and a symbol of a circuit diagram are drawn, and a computer automatically generates a layout file of a layout versus schematic (LVS) based on supplementary information. It is. According to the third embodiment, a rule file can be automatically generated by inputting necessary information of a layout diagram and a circuit diagram as a graphic.

[0033]

As described above, according to the present invention, a rule file for design rule check can be automatically generated by inputting necessary information in characters. Further, according to the present invention, a rule file can be automatically generated by inputting necessary information as a graphic. Furthermore, according to the present invention, a rule file can be automatically generated by inputting necessary information of a circuit diagram and a layout diagram as a graphic. Therefore, since a normal LSI designer or process developer creates a rule file by himself, layout design verification can be performed on a schedule independent of a rule file creation expert engineer, thereby shortening the LSI or process development period. Can be expected. In addition, compared to the case where the optimum rule file cannot be obtained due to the conventional schedule and the like, and the layout design verification cannot be perfectly executed, the design quality can be expected to be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a semiconductor layout design verification rule file automatic generation device according to a first embodiment of the present invention;

FIG. 2 is a diagram showing an example of input to a template according to the first embodiment of the present invention.

FIG. 3 is a flowchart of automatic rule file generation according to the present invention.

FIG. 4 is a block diagram showing a semiconductor layout design verification rule file automatic generation device according to a second embodiment of the present invention;

FIG. 5 is a diagram showing an example of creating a layout diagram according to the second embodiment of the present invention.

FIG. 6 is a block diagram showing a semiconductor layout design verification rule file automatic generation device according to a third embodiment of the present invention.

FIG. 7 is a diagram showing an example of creating a layout diagram according to the third embodiment of the present invention;

FIG. 8 is a diagram showing an example of creating a circuit diagram according to the third embodiment of the present invention.

FIG. 9 is a block diagram showing a conventional DRC rule file creation method.

FIG. 10 is a block diagram showing a conventional LVS rule file creation method.

[Explanation of symbols]

1 Template file, 2, 3 Figure layer name, 4
Figure width / spacing, 5 verification values, 7 rule file automatic conversion program, 8 rule files, 11 templates, 13, 14 figure layer names, 15 figure widths / spacings,
16 verification value, 21 layout diagram, 22, 23 verification target graphic, 24 line segment defining verification target graphic, 25
Layer name, 26 width / interval, 27 verification value, 29 rule file automatic generation program, 30 rule file, 41 layout diagram, 42 device figure, 43
Circuit diagram, 44 symbols, 45 rule file automatic generation program, 46 rule files.

Claims (6)

[Claims] An input means for inputting necessary data by characters to generate a rule file for verifying design rules of a semiconductor layout design, and a conversion means for translating the input data into a grammar of the rule file. An automatic semiconductor design verification rule file generation apparatus characterized by the following. 2. The data according to claim 1, wherein the data includes a layer name of the graphic to be verified stored in the template file, a width of the graphic to be verified, an interval between the graphic to be verified, and verification values thereof. A semiconductor design verification rule file automatic generation device according to [1]. 3. An input means for inputting necessary data in a graphic form and a conversion means for translating the input data into a grammar of the rule file for generating a rule file for verifying a design rule of a semiconductor layout design. An automatic semiconductor design verification rule file generation apparatus characterized by the following. 4. The method according to claim 1, wherein the data includes a layer name of the graphic to be verified stored in the layout diagram, a width defining the graphic to be verified, an interval between the graphic to be verified, and a line segment indicating these verification values. 4. The automatic semiconductor design verification rule file generation device according to claim 3, wherein: 5. An input means for graphically inputting necessary data of a layout diagram and a circuit diagram in order to generate a rule file for comparing and verifying a layout diagram and a circuit diagram in a semiconductor design, and inputting the input data into the rule file. An automatic semiconductor design verification rule file generation apparatus, comprising a conversion means for translating into a grammar. 6. The automatic semiconductor design verification rule file generation apparatus according to claim 5, wherein the data includes a device graphic stored in a layout diagram and a circuit symbol of a device stored in the circuit diagram. .