JPH05314215A - Layout pattern generator - Google Patents

Abstract

PURPOSE:To provide a layout pattern generator which can automatically extract the position information of a ROM rectangle corresponding to a ROM address. CONSTITUTION:This generator is provided with a logical simulation execution part 25 for automatically preparing a signal line table corresponding to the ROM address based on logic circuit diagram data, layout verification execution part 26 for automatically preparing the coordinate table of the signal line based on layout pattern diagram data and ROM position information extraction part 27 for extracting the coordinate table of the ROM rectangle corresponding to the ROM address from the executed results of the logical simulation execution part 25 and the layout verification execution part 26. Therefore, data input work efficiency is improved and the generator with high design quality can be provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a mask ROM built-in type L.
The present invention relates to a layout pattern generator that creates a layout pattern for writing a ROM code in SI.

[0002]

2. Description of the Related Art FIG. 7 is a block diagram showing the structure of a conventional layout pattern generator. In the figure, 1 is a keyboard, 2 is a keyboard control unit for controlling the keyboard, and 3 and 4 are ROM coordinate data and ROM address position as ROM position information created by a designer while looking at a layout pattern diagram and a logic circuit diagram. Information (RO
ROM rectangle position information corresponding to the M address), both of which are input from the keyboard after creation. Reference numeral 5 is a ROM code data reading section for reading ROM code data from EPROM using the PROM programmer device 6, and 7 is a ROM
A ROM layout pattern creating unit that creates a ROM layout pattern corresponding to the read ROM code data based on the position information, and 8 stores the ROM position information, the ROM code data, and the ROM layout pattern in the data storage unit 9. A data control unit 11 for outputting to the screen display unit 10 is a display.

Next, the operation will be described. First, the basic operation of the ROM block in the LSI which is the background of the conventional technique will be described with reference to FIG. FIG. 8 shows a model of the logic circuit of the ROM block portion in the LSI. Here, it is assumed that 64 ROM rectangles for each 1 bit are arranged. A0
A4 of the address signal line 12 consisting of 8 bits of A7
~ A7 is the X decoder 13, A0 to A3 is the Y decoder 1
4 is output. Based on the input signal, the X decoder 13 selects the select signal line 15 (X
Select one from 0 to X7). Similarly, the Y decoder 14 selects the select signal line 16 (Y0 to Y0) in the Y coordinate direction.
Select one of Y7). The ROM rectangle 17 is laid out at the intersection of the selected select signal line in the X coordinate direction and the select signal line in the Y coordinate direction.

Next, the operation of the conventional layout pattern generator will be described with reference to the flowchart of FIG. First, a designer creates layout information of a ROM rectangle based on the layout pattern diagram, and reads various ROM coordinate data as a result from the keyboard 1 (S
1). As shown in FIG. 10, the ROM coordinate data has R
Coordinate value 18 of the lower left apex of the OM area, ROM rectangle length 1
9 and width 20, ROM rectangle number 21 in X direction and RO in Y direction
The number of M rectangles is 22, and the arrangement interval of ROM rectangles in the X direction is 2
3 and a ROM rectangular arrangement interval 24 in the Y direction. Then, the ROM address position information shown in FIG. 11 is read from the keyboard 1 based on the logic circuit diagram (S2). This ROM address position information is a combination of 8 bits of the address signal lines A0 to A7 corresponding to the ROM address, and is created by the designer while looking at the logic circuit diagram. On the other hand, P
ROM code data in the EPROM is read from the ROM programmer device 6 (S3). Next, based on the ROM address position information, the values of the read ROM code data are rearranged so as to correspond to the positions of the ROM rectangles in the layout pattern (hereinafter, rearranged "0", "1" R
The OM code data is called truth value data) (S4). FIG. 12 shows an example of truth value data. Finally, the value of all truth value data is checked, and if it is "1", the coordinates of the ROM rectangle in the layout pattern corresponding to the data are obtained from the ROM address position information and the ROM coordinate data, and the layout of the ROM rectangle is at that position. Create a pattern. If the value of the truth value data is "0", the ROM rectangular layout pattern is not created (S5). FIG. 13 shows an example of a ROM rectangular layout pattern created from the truth value data shown in FIG.

[0005]

Since the conventional layout pattern generator is constructed as described above, the RO
Various ROM coordinate data and ROM address position information, which are M position information, must be created by the designer in advance while looking at the layout pattern diagram and the logic circuit diagram, and the created various data can be entered numerically from the keyboard. I had to. This work requires a lot of time, and there is a problem such as an error in checking the coordinates and the positional relationship and an input error.

The present invention has been made to solve the above problems, and an object thereof is to obtain a layout pattern generator capable of automatically extracting ROM position information.

[0007]

A layout pattern generator according to the present invention is an RO based on logic circuit diagram data.
A logic simulation execution unit that automatically creates a signal line table corresponding to an M address, a layout verification execution unit that automatically creates a signal line coordinate table based on layout pattern diagram data, and the logic simulation execution unit and layout verification execution unit described above. From the execution result with
A ROM position information extraction unit that automatically extracts position information is provided.

[0008]

The ROM position information extraction unit automatically extracts the ROM position information from the execution results of the logic simulation execution unit and the layout verification execution unit according to the present invention.

[0009]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, reference numerals 1, 2, 5 to 11 are the same as or equivalent to those of the conventional apparatus. Reference numeral 25 is a logic simulation execution unit that automatically creates a signal line table corresponding to the ROM address based on the logic circuit diagram data, and 26 is a layout verification execution unit that automatically creates a signal line coordinate table based on the layout pattern diagram data. , 27 are ROM position information extraction units for extracting ROM position information (coordinate table corresponding to ROM addresses) from the execution results of the logic circuit simulation execution unit 25 and the layout verification execution unit 26.

Next, the operation will be described with reference to the flowchart of FIG. First, the logic circuit diagram data, the layout pattern data, and the test pattern data, which are the input data of the logic simulation execution unit 25 and the layout verification execution unit 26, are read (T1, T
2, T3). Also, when creating layout patterns, ROM
The ROM rectangle size for determining the rectangle size is read from the keyboard (T4). On the other hand, ROM code data is read from the PROM programmer device (T5). Next, the test pattern data and the logic circuit diagram data are input to execute the logic simulation (T6). Also, layout verification is executed by inputting layout pattern data and logic circuit diagram data (T
7). In the layout verification, the wiring of the layout pattern data and the device recognition, the comparison check with the LSI design standard, the comparison check of the logical connection between the layout pattern and the logic circuit diagram data, etc. are simultaneously performed.

A ROM rectangular coordinate table on the select signal line is created from the result of the layout verification (T
8). FIG. 3 shows a ROM rectangular coordinate table on the select signal line of the X decoder, and FIG. 4 shows a ROM rectangular coordinate table on the select signal line of the Y decoder. From the execution result of the logic simulation, a select signal line table corresponding to the ROM address as shown in FIG. 5 is created (T
9). Next, R on the select signal line shown in FIGS.
A ROM rectangular coordinate table corresponding to a ROM address as shown in FIG. 6 is created from the OM rectangular coordinate table and the select signal line table shown in FIG. 5 (T1).
0). That is, this becomes the ROM position information. Based on the ROM position information extracted by the above operation, PRO
The ROM code data read from the M programmer device is rearranged so as to correspond to the position of the ROM rectangle, and truth value data is created (T11). Finally, as in the conventional method, all the truth value data are examined, and when the value of the truth value data is "1", a ROM rectangular layout pattern is created.
The ROM rectangle has the coordinates of the ROM rectangle indicated by the ROM position information as the center coordinates, and R read from the keyboard.
It has an OM rectangular size (width and length).

[0012]

As described above, according to the present invention, the RO
Since the M position information can be automatically extracted, the work efficiency is improved, and the device with high design quality can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a layout pattern generator according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing an operation according to the first embodiment of the present invention.

3 is a diagram showing a coordinate table of a ROM rectangle on a select signal line of the X decoder, which is created by the layout verification execution unit of FIG. 1;

4 is a diagram showing a coordinate table of a ROM rectangle on a select signal line of a Y decoder created by the layout verification execution unit of FIG.

5 is a diagram showing a select signal line table corresponding to a ROM address created by the logic simulation of FIG.

FIG. 6 is a diagram showing a coordinate table of a ROM rectangle corresponding to a ROM address created from FIGS. 4 and 5;

FIG. 7 is a block diagram showing a conventional layout pattern generator.

FIG. 8 is a diagram showing a model of a logic circuit of a ROM block which is the background of the conventional technique.

FIG. 9 is a flowchart showing an operation of a conventional layout pattern generation device.

10 is a diagram showing ROM coordinate data read by a ROM coordinate data reading unit in FIG. 7.

11 is a diagram showing ROM address position information read by a ROM address position information reading unit of FIG. 7.

FIG. 12 is a diagram showing truth value data created by the layout pattern generator.

FIG. 13: RO created by a layout pattern generator
It is a figure which shows M layout pattern.

[Explanation of symbols]

 1 Keyboard 3 ROM Coordinate Data Reading Unit 4 ROM Address Position Information Reading Unit 5 ROM Code Data Reading Unit 7 ROM Layout Pattern Creation Unit 25 Logic Simulation Execution Unit 26 Layout Verification Execution Unit 27 ROM Position Information Extraction Unit

Claims (1)

[Claims] 1. R input data using ROM position information (coordinate table corresponding to ROM address) created based on a layout pattern diagram and a logic circuit diagram as basic data.
In a layout pattern generator that creates a ROM layout pattern at a ROM position corresponding to OM code data, a logic simulation execution unit that automatically creates a signal line table corresponding to a ROM address based on the logic circuit diagram data, layout pattern diagram data A layout verification execution unit that automatically creates a coordinate table of signal lines based on the above, and a ROM position information extraction unit that automatically extracts the ROM position information from the execution results of the logic simulation execution unit and the layout verification execution unit. A layout pattern generator characterized by the above.