JPH0553853A - Test pattern generating system - Google Patents

Abstract

PURPOSE:To enable pre-assign with a signal name to a circuit data base generated by logical synthesization in a short time and to prevent designation error from being generated. CONSTITUTION:A logical synthesizing means 1 generates a circuit data base 6 by the logical synthesization from a function description 5, and a logic element extracting means 2 retrieves a signal name 7 of a designated logic circuit from the circuit data base 6 and extracts a corresponding logic element name and the code of the signal name. Next, a pattern generating condition applying means 3 executes the pre-assign with a value corresponding to the extracted logic element name and code according to the designated signal name 7 and a presign value 8. Then, an ATPG(Algorithmic Test Pattern Generation) means 4 generates a test pattern 9 by using the circuit data base 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test pattern creating method for a logic circuit, and more particularly to a test pattern creating method for a logic synthesized circuit.

[0002]

2. Description of the Related Art Conventionally, in a test pattern creating method for a logic circuit, for example, a circuit designer inputs a database based on a circuit diagram and a netlist created by writing a logic description to create a test pattern. Was there. At this time, when pre-assigning to the element of the logic circuit, the circuit designer has designated the element name in the logic description.

Further, when pre-assigning to a logic circuit automatically created from a functional description by logic synthesis, a logic description corresponding to a signal name of the functional description is manually created from the automatically created circuit diagram. I searched for the element name and specified it by the logical element name.

[0004]

In the above-described conventional method, when pre-assigning a circuit created from a functional description by logic synthesis, the correspondence between the signal name of the functional description and the element name is manually determined. Therefore, there is a drawback in that it takes time to specify the logic element name, and a specification error occurs.

[0005]

The present invention is a method for creating a test pattern for a logic circuit, in which a signal name of the specified logic circuit is searched from a circuit database created by logic synthesis from a functional description, A logic element extracting means for extracting the logic element name and the code of the signal name, and a value corresponding to the extracted logic element name and the code of the signal name from the specified signal name and pre-assign value And a pattern generation condition loading means for performing pre-assignment.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, the logic synthesis means 1 has a function description 5
Is an existing method for creating the circuit database 6 by inputting. Regarding the signal name of the circuit database 6, the signal name, the logic element name and the code are stored in association with each other. Next, the logic element extraction means 2 uses the designated signal name 7
Based on the above, the same signal name as the signal name 7 is searched from the circuit database, and the logic element name and code corresponding to the signal name are extracted. At this time, if there is a signal name with the same signal name but opposite sign, the logic element name of the signal name with opposite sign is also extracted together with the sign. When the sign of the logic element name extracted by the logic element extracting means 2 is positive, the pattern generating condition adding means 3 sets the specified pre-assign value 8 in the circuit database 6 as the pattern generating condition together with the logic element name. If the sign is negative, the inverse of the specified pre-assign value 8 (“0” when “1”, “1” when “0”) is used as the pre-assign value. It is set in the circuit database 6 together with the logic element name. ATPG means 4
Is the Algorithmic Test Pattern
Generation, that is, a means for automatically generating a test pattern, which uses the circuit database 6 to create a test pattern 9 by a test pattern generation method based on a known D algorithm or the like.

There are external input pins, scan flip-flops, etc. that can be pre-assigned.
An external input pin was used for the description of this example.

FIG. 2 is a diagram showing an example of an integrated circuit (logical circuit) to which the present invention is applied.

Next, a procedure for creating a test pattern when pre-assignment as shown in FIG. 4 is performed using the integrated circuit of FIG. 2 will be described.

First, the logic element extraction means 2 searches the circuit database 6 for the same signal name as the designated signal name 7 "AAA" using the diagram showing the correspondence of FIG.
NI "and the sign" + "are extracted, and subsequently, in the pattern generation condition adding means 3, since the sign of the extracted pin name" INI "is" positive ", the specified pre-assigned value 9 The value "1" is set as a pattern generation condition in the circuit database 6. Then, the ATPG means 4 inputs the circuit database 6 and creates a test pattern 9.

Further, a test pattern generation procedure for the integrated circuit (logic circuit) of FIG. 2 when the pre-assignment as shown in FIG. 5 is designated will be described.

First, the logic element extraction means 2 searches the circuit database 6 for the same signal name as the designated signal name 7 "CCC" using the correspondence table shown in FIG.
3 "," IN7 "and the signs" + ","-". Subsequently, in the pattern generation condition adding means 3, since the sign of the extracted pin name" IN3 "is" positive ", "0", which is the inverse value of the designated preassigned value 9 of "1", is set in the circuit database 6 as a pattern generation condition, and the ATPG means 4 inputs the circuit database 6 to test pattern 9. To create.

[0014]

As described above, according to the present invention, when pre-assigning a circuit created from a functional description by logic synthesis, the signal can be specified by the signal name of the functional description and the same signal name but a different sign. Since the input pin of the signal name can be pre-assigned at the same time, there is an effect that the designation can be completed in a short time and the designation error can be eliminated.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing an example of an integrated circuit (logical circuit) applied to this embodiment.

FIG. 3 is a diagram showing a database of the logic circuit (logic circuit) shown in FIG.

FIG. 4 is a diagram showing an example of pre-sign designation.

FIG. 5 is a diagram showing an example of pre-sign designation.

[Explanation of symbols]

 1 Logic Synthesis 2 Logic Element Extraction Means 3 Pattern Generation Condition Adding Means 4 ATPG Means 5 Functional Description 6 Circuit Database 7 Signal Name 8 Presigned Value 9 Tester Pattern

Claims (1)

[Claims] 1. A method of creating a test pattern of a logic circuit, wherein a signal name of the specified logic circuit is searched from a circuit database created by logic synthesis from a functional description,
A logic element extracting means for extracting the corresponding logic element name and the code of the signal name, and a value corresponding to the extracted logic element name and the code of the signal name from the designated signal name and preassigned value And a pattern generation condition loading means for pre-assigning the test pattern creation method.