JP2000215217A - Device and method for logical synthesis - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a logical synthesis method capable of shortening the design time while holding an optimum circuit delay even when a logical description executed at the end of logical synthesis is changed. SOLUTION: In the logical synthesis method for executing logical synthesis again from a logical description changed when logical synthesis completed based on a prescribed logical description, a changed position is extracted by comparing the contents of uncorrected logical description to be logical description obtained before a change with that of corrected logical description to be logical description obtained after the change, a non-corrected network list is generated by deleting a network list corresponding to the changed position from the uncorrected network list to be a logical synthesis result logically synthesized by the uncorrected logical description and a changed position network list to be the logical synthesis result of only the changed position is generated by executing logical synthesis based on difference information indicating the changed position. Then the contents of the non-corrected network list and the changed position network list are synthesized to generate an updated network list corresponding to the logical synthesis result of the corrected logical description.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic circuit design method, and more particularly, to a logic synthesis method for performing logic synthesis using a logic description language and an apparatus therefor.

[0002]

2. Description of the Related Art FIG. 4 is a diagram showing a processing procedure of an automatic circuit design method, and is a flowchart for creating a netlist from a logic description language by a logic synthesis device.

In FIG. 4, when a designer creates a logic description using a logic description language, the logic synthesizer creates a netlist based on the created logic description (step S41). At this time, the logic synthesizer performs logic synthesis so as to satisfy a predetermined circuit delay according to the contents of the constraint file in which the standard value of the circuit delay intended by the designer is recorded. All gates (components) used in the logically synthesized netlist are respectively given unique instance names.

Next, the logic synthesizer implements a floor plan for determining the arrangement of each gate in the netlist.
(Step S42). In the floor plan, arrangement information is created for each gate in the netlist, in which the instance name and the corresponding position coordinates are paired. Then, a circuit delay, which is a delay time of the gate itself, and a media delay, which is a delay time due to the wiring length, are calculated based on the netlist and the arrangement information (step S43). It is verified whether the value is equal to or less than the value (step S4).
4).

If the circuit delay and the media delay are not smaller than the standard values intended by the designer, the circuit layout and circuit configuration are examined in detail from the delay verification results (step S45).

It is considered that the circuit delay is deteriorated because a gate having a large delay is used or the number of gate stages is large. Further, as a cause of the deterioration of the media delay, it is considered that the wiring length between the gates arranged according to the floor plan is long.

In the former case, the process returns to step 41 to reconsider the contents of the constraint file, and the subsequent processes are performed again. In the latter case, the floorplan is performed again so that the arrangement information is corrected and the wiring length between the gates is not increased. With the above processing, a circuit in which the circuit delay is suppressed within the standard value is created.

[0008]

In the above-described conventional logic synthesis method, if the logic description is changed after the netlist is created, the instance name changes in order to execute the logic synthesis again. At that time, since the conventional placement information cannot be used in the floor plan executed thereafter, the placement information needs to be changed, and the performance of the circuit delay designed with the optimum delay time before the change of the logic description cannot be maintained. Problems arise.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and provides an optimum circuit delay even when the logic description is changed at the end of logic synthesis. It is an object of the present invention to provide a logic synthesis method in which the design time is reduced while maintaining the above.

[0010]

In order to achieve the above object, a logic synthesis method according to the present invention performs logic synthesis again from a changed logic description after completion of logic synthesis performed based on a predetermined logic description. And comparing the contents of a pre-modification logical description, which is a pre-change logical description, and a post-modification logical description, that is, a post-modification logical description, and extracting a changed portion. From the uncorrected netlist that is the result of the logic synthesis in, to generate an uncorrected netlist by deleting the netlist corresponding to the changed portion,
Performing logic synthesis based on the difference information indicating the changed portion, generating a changed portion netlist that is a result of logic synthesis of only the changed portion, and synthesizing the contents of the uncorrected netlist and the changed portion netlist. A method of generating an updated netlist corresponding to a result of logic synthesis of the corrected logic description.

At this time, it is checked whether or not the instance name used in the uncorrected netlist and the instance name used in the changed portion netlist are duplicated. The duplicate instance name in the change point netlist may be changed to an unused instance name, and a constraint file in which a standard value of a circuit delay intended by a designer is provided in advance, and the standard value is used. The change portion netlist may be created to satisfy the user.

Further, the logic synthesizing apparatus of the present invention is a logic synthesizing apparatus for performing a logic synthesis again from a changed logic description after a logic synthesis performed based on a predetermined logic description is completed. Difference extracting means for comparing the contents of a pre-correction logical description, which is a logical description, and a post-modification logical description, which is a post-change logical description, to extract a changed portion, and a result of logical synthesis using the pre-correction logical description. From the pre-correction netlist, a modified portion specifying means for generating an unmodified netlist in which the netlist corresponding to the modified portion has been deleted, and perform logic synthesis based on the difference information indicating the modified portion,
A changed part logic synthesizing means for generating a changed part netlist which is a result of logic synthesis of only the changed part, and synthesizing the contents of the unmodified netlist and the changed part netlist, and a logical synthesis result of the corrected logic description Netlist generating means for generating an updated netlist corresponding to
It is a structure which has.

At this time, the net list generating means includes:
An instance name used in the uncensored netlist,
And, it is checked whether there is no duplicate in the instance name used in the changed part netlist, and if there is a duplicate in the instance name, the duplicate instance name in the changed part netlist is replaced with an unused instance name. It may be changed, and a constraint file in which a standard value of a circuit delay intended by a designer is recorded in advance, and the changed portion logic synthesizing means sets the changed portion netlist so as to satisfy the specified value. May be generated.

The above-described logic synthesizing method and logic synthesizing apparatus generate an uncorrected netlist in which a netlist corresponding to a changed portion is deleted from a netlist before correction, which is a result of logic synthesis based on a logical description before correction. Then, perform logic synthesis based on the difference information indicating the changed portion, generate a changed portion netlist that is a result of logic synthesis of only the changed portion, synthesize the unmodified netlist and the changed portion netlist, and correct the content. By generating an updated netlist corresponding to the logical synthesis result of the post-logical description, in a place where the logical description does not change, the logical synthesis is not performed again. Is saved. In addition, the position information before the change of the logical description can be used for a portion where the instance name is not changed.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an example of the configuration of a logic synthesis apparatus according to the present invention.

In FIG. 1, the pre-modification logical description is a pre-change logical description, and the post-modification logical description is a post-change logical description. The netlist before correction is a netlist logically synthesized from the logical description before correction, and the constraint file 4 is a file in which standard values of circuit delay are recorded.

The difference extracting means 1 compares the pre-correction logical description with the post-correction logical description to extract a changed portion, and outputs the changed portion as difference information. The difference information file 2 is a file in which a difference (change portion) between the before-correction logical description and the after-correction logical description output from the difference extracting means 1 is recorded.

The changed part specifying means 3 is a differential information file 2
The configuration corresponding to the changed part in the netlist before correction is deleted based on the difference information recorded in the netlist and the uncorrected netlist is output. The changed part logic synthesizing means 5 performs logic synthesis only on the changed part based on the corrected logical description, the difference information and the contents of the constraint file 4, and outputs the changed part netlist.

The net list generating means 6 combines the contents of the unmodified net list and the changed part net list, and outputs an updated net list which is a net list corresponding to the logical synthesis result of the corrected logical description.

In such a configuration, the operation of the logic synthesizing device of the present invention will be described next with reference to FIGS.

FIG. 2 is a list showing an example of the pre-modification logical description and the post-modification logical description shown in FIG. FIG. 3 is a block diagram showing an example of the netlist before correction and the netlist after update shown in FIG. G001 to G003 described in each component in FIG. 3 indicate instance names.

After the pre-modification netlist is created by the pre-modification logical description and the logical description is changed and the post-modification logical description is input, the logic synthesizer compares the pre-modification logical description and the post-modification logical description with each other. It is taken into the extracting means 1.
Here, it is assumed that the pre-modification logical description is described as shown in FIG.

In the logical description before correction shown in FIG. 2A, the signal "B" is output as the logical sum of the signal "E" and the signal "F", and the signal "A" is output as the signal "B" and the signal "F". C "and the signal" D ". The netlist obtained by logically synthesizing these logical descriptions is shown in FIG.
(A).

Here, it is assumed that the logical description is changed from the logical description shown in FIG. 2A as shown in FIG. 2B, and a modified logical description is created.

At this time, the difference extracting means 1 detects that the logical description of the signal “A” has been changed, and records the difference information in the difference information file 2.

The changed portion specifying means 3 refers to the difference information file 2 and deletes the configuration relating to the connection and the gate from the signal “C” and the signal “D” to the signal “A” in the netlist before correction and changes the netlist. If there is no, the data including the instance name is output as it is as an unmodified netlist.

Next, the changed part logic synthesizing means 5 takes in the corrected logical description and the difference information, and performs a logic synthesis of only the changed part to generate a changed part net list. At this time, the changed part logic synthesizing unit 5 refers to the constraint file 4 in which the circuit delay standard value before the correction is recorded, and performs the logic synthesis while reflecting the delay constraint if the logic description has a changed delay constraint. .

The net list generating means 6 takes in the uncorrected net list and the changed part net list, and synthesizes the respective net lists. At this time, the netlist generation means 6 does not change the instance name of the unmodified netlist at all. Further, the instance name of the changed part netlist and the instance name of the unmodified netlist are checked to determine whether there is any duplication. If the instance name of the changed portion netlist and the instance name of the unmodified netlist overlap, the duplication is avoided by changing the duplicate instance name at the changed portion to an unused instance name.

By performing such processing, FIG.
An updated netlist as shown in FIG. 3B can be obtained for the modified logical description shown in FIG. In addition,
As shown in FIG. 3B, the instance name given to each component of the changed portion netlist may be the same as the name used in the netlist logically synthesized from the logical description before correction.

Therefore, according to the present invention, in a place where the logical description is not changed, since the logical synthesis is not performed again, the net list and the instance name as the result of the logical synthesis before the change are stored. In addition, since the position information before the logical description change can be used for a portion where the instance name does not change, the gate is placed again at the same position when executing the floor plan, and the circuit delay performance at the time of the wiring before the correction is almost reduced. The logic is kept with the optimal circuit delay.

Further, since the logic synthesis is performed only at the changed portion, the time required for the logic synthesis is shortened, and the design time is shortened.

[0033]

Since the present invention is configured as described above, the following effects can be obtained.

An uncorrected netlist in which the netlist corresponding to the changed portion is deleted from the netlist before the correction, which is the result of the logical synthesis based on the logical description before the correction, is generated based on the difference information indicating the changed portion. To generate a changed part netlist that is the result of logic synthesis of only the changed part, synthesize the contents of the unmodified netlist and the changed part netlist, and update the updated net corresponding to the logical synthesis result of the corrected logical description. By generating the list, in a place where there is no change in the logic description, since the logic synthesis is not performed again, the net list and the instance name as the result of the logic synthesis before the change are stored. In addition, the position information before the change of the logical description can be used for a portion where the instance name is not changed.

Therefore, the gate is arranged again at the same position when the floor plan is executed, the circuit delay performance at the time of wiring before correction is substantially maintained, and the logic is synthesized with an optimum circuit delay.

Further, since the logic synthesis is performed only at the changed portion, the time required for the logic synthesis is reduced, and the design time is shortened.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration example of a logic synthesis device according to the present invention.

FIG. 2 is a list showing an example of a pre-modification logical description and a post-modification logical description shown in FIG. 1;

FIG. 3 is a block diagram showing an example of a netlist before correction and a netlist after update shown in FIG. 1;

FIG. 4 is a diagram showing a processing procedure of a circuit automatic design method;
5 is a flowchart for creating a netlist from a logic description language by a logic synthesis device.

[Description of Signs] 1 Difference extraction means 2 Difference information file 3 Change location specifying means 4 Constraint file 5 Change location logic synthesis means 6 Netlist generation means

Claims (6)

[Claims] 1. A logic synthesis method for performing logic synthesis again from a logic description changed after completion of logic synthesis performed based on a predetermined logic description, wherein the logic description before the change is a logic description before the change. The contents of the logical description and the modified logical description, which is the modified logical description, are compared to extract the changed part. Generating an uncorrected netlist from which the corresponding netlist has been deleted; performing logic synthesis based on the difference information indicating the changed portion; generating a changed portion netlist that is a logic synthesis result of only the changed portion; A logic synthesizing method for synthesizing the contents of a corrected netlist and the changed part netlist to generate an updated netlist corresponding to a logical synthesis result of the corrected logical description. 2. An instance name used in the unmodified netlist and an instance name used in the changed portion netlist are checked for duplication. If there is a duplication in the instance name, the change is made. The ethical synthesis method according to claim 1, wherein the duplicate instance name in the local netlist is changed to an unused instance name. 3. A change file netlist is prepared in advance with a constraint file in which a standard value of a circuit delay intended by a designer is recorded, and the changed portion netlist is satisfied so as to satisfy the standard value. Logic synthesis method. 4. A logical synthesizing apparatus for performing logical synthesis again from a logical description changed after completion of logical synthesis performed based on a predetermined logical description, wherein the logical description before modification is a logical description before the change. And a difference extracting means for comparing the contents of the post-modification logical description, which is the post-modification logical description, to extract a changed portion; A modified portion specifying means for generating an unmodified netlist in which a netlist corresponding to the modified portion is deleted; and performing a logic synthesis based on difference information indicating the modified portion, and a modified portion net which is a result of logic synthesis of only the modified portion. A modified part logic synthesizing means for generating a list; combining the contents of the uncorrected net list and the modified part net list; A net list generating means for generating the updated netlist, the logic synthesis device having a. 5. The netlist generating means includes: an instance name used in the unmodified netlist;
And confirm whether there is no duplicate in the instance name used in the changed part netlist, and if there is a duplicate in the instance name, replace the duplicate instance name in the changed part netlist with an unused instance name. 5. The ethical synthesis device according to claim 4, wherein the device is changed. 6. A constraint file in which a standard value of a circuit delay intended by a designer is recorded in advance, and said changed part logic synthesizing means converts said changed part netlist so as to satisfy said standard value. The logic synthesis device according to claim 4, wherein the logic synthesis device generates the data.