JP2001084283A - System and method for logic circuit automatic synthesizing - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily enable a synthesized logic circuit to correspond to original HDL and to easily recognize/correct a synthesized result by displaying intermediate signals, that respective pieces of parts information of HDL have in the logic circuit when parts information from parts information of the logic circuit, which are described by hardware description language HDL, are outputted as the logic circuit which is optimized by logically synthesizing them. SOLUTION: A compiling part 4 reads HDL 1 and generates an inner data base with boundary information 2 on an intermediate signal in HDL 1. An optimization part 5 optimizes the initial logic circuit of an AND/OR level in the inner data base with boundary information 2, while boundary information is held. A technology mapping part 6 holds the initial logic circuit as boundary information and allocates it to a function block within a semiconductor library 3. A timing optimizing part 7 optimizes delays with respect to the logic circuit 10 of a technology level in the inner data base with boundary information 2, in a state where boundary information is held.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for automatically synthesizing a logic circuit, and more particularly to a hardware description language (Hardware Description Language).
are Descriptive Language:
The present invention relates to a logic circuit automatic synthesis system and a logic circuit automatic synthesis method for automatically synthesizing a logic circuit from HDL).

[0002]

2. Description of the Related Art As a conventional automatic synthesis method of a logic circuit, L.L. Bulldozer by Stok et al .: Logic Synthesis for ASICs (Bool Doze
r: Logic Synthesis for ASI
Cs) 1996.7, IBM, J.A. RES. Level
operation, pp. 407-430 (hereinafter referred to as Reference Document 1).

[0003] Such a prior art is disclosed, for example, in Japanese Patent Application Laid-Open No. 11-73449 (the above-mentioned prior art). In other words, the above-described prior art is intended to make it easy to know which part in the logic circuit after synthesis the intermediate signal in the hardware description language (HDL) is, Boundary information of the part corresponding to the intermediate signal in the hardware description language is always held in the logic circuit in the middle of logic synthesis, and the automatic synthesis method of the logic circuit outputs a correspondence table between the intermediate signal and the synthesized logic circuit. is there. Here, even in the case of an intermediate signal in the hardware description language, better optimization is performed by partially leaving no boundary information.

[0004] In such a conventional automatic synthesis method of a logic circuit, a hardware description language is analyzed and AND / OR is performed.
A compiling unit for creating an internal database with boundary information by converting the data into an initial logic circuit of a level and holding boundary information of a portion corresponding to the intermediate signal in the hardware description language; and an AND in the internal database with boundary information A technology-independent optimization unit that holds the initial logic circuit at the / OR level as the boundary information and performs technology-independent optimization, and an AND / OR level optimized by the technology-independent optimization unit. A technology mapping unit that holds an initial logic circuit as the boundary information and allocates each function block in the semiconductor library to convert it to a technology level logic circuit; and a technology level logic circuit obtained by the technology mapping unit. Hold the file Outputs a timing optimization unit that optimizes using methods such as out adjustment, fan-in / reordering, decomposition in consideration of timing, and inverter change, and a technology-level logic circuit optimized by this timing optimization unit And a correspondence table output for outputting a correspondence table representing correspondence between intermediate signals in the hardware description language and the logic circuit with reference to a logic circuit of a technology level in the internal database with boundary information. Is disclosed.

In the above-mentioned prior art automatic synthesis method of a logic circuit, a hardware description language is analyzed and converted into an initial logic circuit of an AND / OR level, and a boundary of a portion corresponding to an intermediate signal in the hardware description language is analyzed. A compiling unit that creates an internal database with boundary information by retaining information; a constant propagation unit that partially deletes the boundary information in the internal database with boundary information; and a reference count from the internal database with boundary information. A technology that holds a reference count checker for deleting boundary information equal to or less than N (positive integer) and an initial logic circuit at an AND / OR level in the internal database with boundary information as the boundary information and performs technology-independent optimization. Independent optimizer and AND / O optimized by this technology independent optimizer A technology mapping unit that holds the function information in the semiconductor library by retaining the boundary information in the initial logic circuit of the level and assigns each function block in the semiconductor library to a logic circuit of the technology level; A timing optimization unit that optimizes using methods such as fan-out adjustment, fan-in / reordering, timing-based decomposition, and inverter change while retaining information, and a timing optimization unit that optimizes A logic circuit output unit that outputs a technology-level logic circuit; and a correspondence that indicates a correspondence between an intermediate signal in the hardware description language and the logic circuit with reference to the technology-level logic circuit in the internal database with boundary information. Table output pair It has a front output portion is also disclosed that it may be.

Further, in the above-described automatic synthesis method of a logic circuit, the compiling unit analyzes a hardware description language and converts the hardware description language into an initial logic circuit of an AND / OR level. And a boundary information generation section for searching for a node with a signal name in the initial logic circuit at the AND / OR level, replacing the boundary information of the node with the signal name with the immediately preceding node, and removing the node with the signal name. Is also disclosed.

Such a prior art discloses an effect that even if an intermediate signal in HDL, it is possible to determine which part in a logic circuit corresponds to a synthesis result. Even in the case of an intermediate signal in HDL, in order to give priority to the performance of optimization, partially retain the boundary information of the other intermediate signals and output only the boundary information of other intermediate signals to the correspondence table. There is also disclosed an effect that can be performed. Further, it discloses that an automatic synthesis method of a logic circuit can be easily implemented in a computer.

FIG. 4 is a block diagram showing an outline of the conventional logic circuit automatic synthesis method. This figure is not described in the above-mentioned document, but is a summary of the contents.
The above-mentioned prior art logic circuit automatic synthesis method uses the HDL 101
, The internal database 102, and the semiconductor library 10
3, a compiling unit 104, and a technology-independent optimization unit (Technology-independent)
optimization 105 and a technology mapping unit (Technology mappin).
g), a timing optimization unit 107, a logic circuit output unit 108, and a logic circuit 111.

In such a conventional logic circuit automatic synthesis method, the compiling unit 104 reads the HDL 101, converts it into a logic circuit 111, and stores it in the internal database 102.

Subsequently, the technology independent optimization unit 10
5 is a constant propagation (Constant pro) to the logic circuit 111 stored in the internal database 102.
page), Redundancy elimination (Redundancy)
removal, global flow (Global)
flow), transduction (Transduc)
tion), flattening (Flattening), cube factoring (Cubefactoring),
Cube expand / reduce
duce), kernel extraction (Kernel facto)
ring) or other optimization method of the logic circuit 111.

Subsequently, the technology mapping unit 106
Assigns the optimized logic circuit 111 to each function block in the given semiconductor library 103.

Subsequently, the timing optimizing unit 107 adjusts the fan-out (Fan-out) in consideration of the result.
correction), fan-in reordering, and decomposition in consideration of timing (Decomposition)
on), inverter change (Inverter moti)
on) and the like. Finally, the logic circuit output unit 108 outputs the final result as the logic circuit 111.

[0013]

However, the above prior art has the following problems. The first problem is that the HDL 101 and the logic circuit 1
11 does not completely match.
The reason is that information of the HDL 101 is lost due to various optimizations. For example, the intermediate signal S in FIG. 13 (a) in Reference 1 is:
On the HDL 101, S = (A and C) or (A a
nd D) or (B and C) or (B and
Although D), as a result of the optimization called transduction, it is changed to S ′ = C or D (see FIG. 13 (b) in Reference 1). Here, the intermediate signal is a signal described on the HDL 101 and means a signal other than the input / output of the circuit and the output of the flip-flop (the same applies hereinafter).

On the other hand, in order to establish a correspondence between the HDL 101 and the logic circuit 111, a method that does not use an algorithm such as transduction is conceivable. A problem that the performance (area / delay) becomes too bad. Such a problem similarly occurs in a method other than the transduction.

[0015] The second problem is that there is no method for knowing which part in the logic circuit 111 the intermediate signal in the HDL 101 hits.

The present invention has been made in view of such a problem, and an object of the present invention is to make it very easy to associate a synthesized logic circuit with the original HDL and to confirm the synthesis result. An object of the present invention is to provide a logic circuit automatic synthesis system and a logic circuit automatic synthesis method that can be easily and manually corrected.

[0017]

The gist of the invention described in claim 1 is that the correspondence between the synthesized logic circuit and the original hardware description language can be made very easily, and the synthesized result can be confirmed or corrected manually. And a logic circuit automatic synthesis system which can very easily perform the logic synthesis of the component information from the component information of the logic circuit described in the hardware description language. Means for outputting as a logic circuit, and means for displaying an intermediate signal of each piece of component information of the hardware description language in the output logic circuit when outputting the optimized logic circuit. It exists in the automatic logic circuit synthesis system. The gist of the invention described in claim 2 is that the logic circuit after the logic synthesis has means for storing an intermediate signal name in the original hardware description language as a net name. In the automatic logic circuit synthesis system described in (1). The gist of the invention according to claim 3 is that a compiling unit that inputs the hardware description language and creates an internal database with boundary information of an intermediate signal, and stores boundary information in the internal database with boundary information; A technology-independent optimizing unit for optimizing the logic circuit; and the logic circuit optimized by the technology-independent optimizing unit is held as the boundary information and assigned to each function block in the semiconductor library. Technology mapping unit, and timing of optimizing the result of the technology mapping unit using techniques such as fan-out adjustment, fan-in / reordering, decomposition taking into account timing, and inverter change while retaining the boundary information. An optimization unit and the internal database with boundary information. A net name setting unit that saves the boundary information in the network as a net name of the internal database with the boundary information, and a logic circuit output unit that outputs the optimized logic circuit. 2. The automatic logic circuit synthesis system according to item 2. Further, the gist of the invention described in claim 4 is that it is very easy to associate the synthesized logic circuit with the original hardware description language, and it is very easy to check the synthesis result and manually correct it. A logic circuit automatic synthesizing method that can be easily performed, comprising: logic-synthesizing the component information from component information of the logic circuit described in the hardware description language, and outputting the component information as the optimized logic circuit. Displaying an intermediate signal of each component information of the hardware description language in the output logic circuit at the time of output of the optimized logic circuit. Exists. The gist of the invention described in claim 5 is that the logic circuit after the logic synthesis has a step of storing an intermediate signal name in the original hardware description language as a net name. In the automatic logic circuit synthesis method described above. The gist of the invention according to claim 6 is that a compile step of inputting the hardware description language and creating an internal database with boundary information of an intermediate signal, and holding boundary information in the internal database with boundary information, A technology-independent optimization step of optimizing the logic circuit; and holding the optimized logic circuit as the boundary information by the technology-independent optimization step and assigning the logic circuit to each function block in a semiconductor library. Technology mapping step, fan-out adjustment while holding the boundary information,
Using a technique such as fan-in / reordering, decomposition in consideration of timing, inverter change, etc., a timing optimization step of optimizing the result of the technology mapping step, and the boundary information in the internal database with the boundary information. 6. The automatic logic circuit according to claim 4, further comprising: a net name setting step of storing the net name in the internal database with boundary information, and a logic circuit output step of outputting the optimized logic circuit. There is a synthesis method.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first feature of the embodiment described below is that a logic component is synthesized from component information of a logic circuit described in a hardware description language (HDL) to optimize the logic. When outputting as a circuit, an intermediate signal of each component information of the HDL is displayed in the output logic circuit.

A second feature is that an intermediate signal name in an original hardware description language is stored as a net name in a logic circuit after logic synthesis.

A third feature is that a compiling section for inputting HDL and creating an internal database with boundary information of intermediate signals, and a technology for holding boundary information in the internal database with boundary information and optimizing a logic circuit Independent optimization unit, technology mapping unit that holds the logic circuit optimized by the technology independent optimization unit as boundary information and assigns it to each function block in the semiconductor library, and the result of the technology mapping unit A timing optimization unit that optimizes using methods such as fan-out adjustment, fan-in / reordering, timing-based decomposition and inverter change while retaining boundary information, and boundary information in an internal database with boundary information Internal Database with Boundary Information Considering Data By providing a net name setting unit for saving the net name and a logic circuit output unit for outputting the optimized logic circuit, the intermediate signal in the original HDL can be saved in the output logic circuit. Is to become. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a functional block diagram illustrating an automatic logic circuit synthesis system 20 according to an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes an HDL (Hardwea).
rDescriptive Language: hardware description language), 2 is an internal database with boundary information, 3 is a semiconductor library, 4 is a compiling unit, 5 is a technology independent optimization unit, 6 is a technology mapping unit, 7 is a timing optimization unit, 8 is a timing optimization unit. Is the net name setting section,
9 is a logic circuit output unit, 10 is a logic circuit, and 20 is a logic circuit automatic synthesis system.

Referring to FIG. 1, an automatic logic circuit synthesis system 20 according to the present embodiment includes an HDL 1, an internal database 2 with boundary information, a semiconductor library 3, a compiling unit 4, a technology independent optimizing unit 5, a technology mapping unit. 6, a timing optimization section 7, a net name setting section 8, a logic circuit output section 9, and a logic circuit 10.

The compiling unit 4 analyzes the HDL1 and
By converting the data into an initial logic circuit of ND / OR level and holding the boundary information of the portion corresponding to the intermediate signal in the hardware description language, the internal database 2 with boundary information
Is configured to create.

The technology-independent optimizing unit 5 is configured to perform the technology-independent optimization by holding the boundary information for the initial logic circuit at the AND / OR level in the internal database 2 with boundary information. ing.

The technology mapping unit 6 performs AND / optimization performed by the technology-independent optimization unit 5 described above.
The boundary information is held in the initial logic circuit at the OR level, and each function block in the semiconductor library 3 is assigned to convert the function block into the logic circuit 10 at the technology level.

The timing optimizing unit 7 converts the technology-level logic circuit 10 obtained by the technology mapping unit 6 into a fan-out adjustment, fan-in / reordering, and timing-consideration while retaining the boundary information. The configuration is such that optimization is performed using a method such as changing the position and the inverter.

The net name setting section 8 refers to the logic circuit 10 in the internal database 2 with the boundary information and the boundary information corresponding to the intermediate signal, and obtains a part that can associate the intermediate signal in the HDL 1 with the logic circuit 10. HDL Net Name
1 is formed from the intermediate signal.

The logic circuit output unit 9 is configured to output a technology-level logic circuit 10 optimized by the timing optimization unit 7.

Next, the operation of the automatic logic circuit synthesis system 20 (the automatic logic circuit synthesis method) will be described. FIG. 2 is a diagram for explaining the operation of the compiling unit 4 of FIG. 1, and FIG. 3 is an example of an initial logic circuit generated and output by the compiling unit 4 of FIG. 2 and 3, A and B are intermediate signals, T
1, T2, T3, and T4 indicate input signals.

Referring to FIG. 2, the compiling section 4 of this embodiment first reads HDL1 and reads HDL1.
An internal database 2 with boundary information for the intermediate signal in the middle is created. For example, as shown in FIG. 2, A = (T
HDL defined as 1 + T2) × T3, B = A + T4
Each of the intermediate signal A and the intermediate signal B is not an input terminal, an output terminal of a circuit, or a sequential circuit element such as a flip-flop, but an intermediate signal which is internally referred to in another logical expression. On the other hand, in the conventional automatic synthesis method of the logic circuit, the HDL1
It is difficult to determine which part each of the intermediate signal A and the intermediate signal B is.

More specifically, the compiling unit 4 of the present embodiment stores the AND / OR logic of the HDL 1 including the intermediate signal A and the intermediate signal B shown in FIG. An initial logic circuit as shown in FIG. As can be seen from FIG.
The structure of DL1 is generated as it is as an initial logic circuit. Further, the intermediate signal A and the intermediate signal B in the HDL 1
Are also present as signal-named nodes 11a and 11b. These signal-named nodes 11a and 11b have no logical meaning, and their portions are HD
It merely shows which intermediate signal in L1. This is called boundary information.

In response, the technology-independent optimizing unit 5 performs AND / O in the internal database 2 with boundary information.
For R-level initial logic circuits, constant propagation, redundancy elimination, global flow, transduction, flattening,
Optimization such as cube factoring, cube enlargement / reduction, and kernel extraction is performed while retaining boundary information.

In response, the technology mapping unit 6
Is AND / OR in the internal database 2 with boundary information.
The initial logic circuit of the level is held as boundary information and assigned to a function block in the semiconductor library 3. As a result, the initial logic circuit at the AND / OR level in the internal database 2 with boundary information is converted to the logic circuit 10 at the technology level. FIG. 2 shows an example of the logic circuit 10.

In response to this, the timing optimizing unit 7 performs fan-out adjustment, fan-in reordering, and timing while maintaining the boundary information for the technology-level logic circuit 10 in the internal database 2 with boundary information. Perform delay optimization such as decomposition, mapping, inverter change, etc. taking into account.

In response, the net name setting unit 8 converts the boundary information into a net name of the logic circuit 10. In particular,
The nodes with signal names 11a and 11b are deleted, and the HDL1 intermediate signal name of the boundary information stored in the nodes with signal names 11a and 11b is set as the net name in the net of that part.

In response, the logic circuit output unit 9 outputs the optimized logic circuit in the internal database 2 with boundary information as the logic circuit 10.

Thus, as can be seen from the example of the logic circuit 10 shown in FIG. 2, the names of the intermediate signals A and B are left as net names in the logic circuit 10.

As described above, according to the present embodiment, the following effects can be obtained. First, the first effect is that the correspondence between the synthesized logic circuit 10 and the original HDL 1 can be very easily obtained. The reason is that the optimization is performed while keeping the correspondence of HDL1, and the information of the intermediate signals A and B of HDL1 is stored in the net name of the finally synthesized logic circuit 10.

The second effect is that it is very easy to confirm the result of synthesis and to correct it manually. The reason is that the synthesized logic circuit 10
This is because the correspondence with DL1 can be easily obtained.

Lastly, the technical differences between the present invention and the above-mentioned prior art will be described. In the above-described related art, a correspondence table that supplements the contents of a logic circuit that is automatically synthesized based on HDL information is output, and the correspondence table describes an intermediate signal. Further, the configuration is such that the correspondence with the HDL is output to a file separate from a logic circuit called a correspondence table.

On the other hand, according to the present invention, when synthesizing the component information from the component information of the logic circuit described in HDL and outputting it as an optimized logic circuit, the intermediate signal of each component information of HDL is output to the output device. It is characterized in that it is displayed in a logic circuit. Further, the present invention provides an intermediate signal (particularly, a portion having boundary information) of each component information of HDL.
Is changed so that the correspondence with the HDL can be understood using the net name in the output logic circuit. As a result, in the new method, the correspondence is included in the net name in the logic circuit, and the correspondence can be understood very simply by looking at the logic circuit. Therefore, there is an effect that analysis and correction of the circuit can be performed more easily than before. On the other hand, in the above-described conventional technology, it is necessary to always go to the correspondence table in order to take the correspondence. As described above, it is considered that the present invention is different in configuration and effect from the prior art.

It should be noted that the present invention is not limited to the above embodiment, and it is apparent that the above embodiment can be appropriately modified within the scope of the technical idea of the present invention. Further, the number, position, shape, and the like of the constituent members are not limited to the above-described embodiment, and can be set to numbers, positions, shapes, and the like suitable for carrying out the present invention. In each drawing, the same components are denoted by the same reference numerals.

[0043]

Since the present invention is configured as described above, the following effects can be obtained. First, the first effect is that the correspondence between the synthesized logic circuit and the original HDL can be very easily achieved. The reason is that the optimization is performed while keeping the HDL correspondence, and the information of the HDL intermediate signal is stored in the net name of the finally synthesized logic circuit.

The second effect is that it is very easy to confirm the result of the synthesis and to correct it manually. The reason is that the synthesized logic circuit is the original HDL
This is because correspondence can be easily taken.

[Brief description of the drawings]

FIG. 1 is a functional block diagram illustrating an automatic logic circuit synthesis system according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining the operation of a compiling unit in FIG. 1;

FIG. 3 is an example of an initial logic circuit generated and output by a compiling unit in FIG. 2;

FIG. 4 is a block diagram showing an outline of a conventional logic circuit automatic synthesis method.

[Explanation of symbols]

1. HDL (Hardware Descriptive)
e Language: hardware description language) 2 ... internal database with boundary information 3 ... semiconductor library 4 ... compiling unit 5 ... technology independent optimization unit 6 ... technology mapping unit 7 ... timing optimization unit 8 ... net name setting unit 9 ... Logic circuit output unit 10: Logic circuit 11a, 11b: Node with signal name 20: Logic circuit automatic synthesis system A, B: Intermediate signal T1, T2, T3, T4: Input signal

Claims (6)

[Claims] 1. A logic circuit in which a synthesized logic circuit can be easily associated with an original hardware description language, and a synthesis result can be very easily checked and corrected manually. Means for automatically synthesizing the component information from component information of the logic circuit described in the hardware description language and outputting the component information as the optimized logic circuit; and A logic circuit automatic synthesizing system comprising means for displaying an intermediate signal of each piece of component information of the hardware description language in the output logic circuit at the time of output. 2. The automatic logic circuit synthesis system according to claim 1, wherein the logic circuit after the logic synthesis has means for storing an intermediate signal name in an original hardware description language as a net name. . 3. A compiling unit for inputting the hardware description language to create an internal database with boundary information of an intermediate signal, and holding the boundary information in the internal database with boundary information and optimizing the logic circuit. A technology-independent optimizing unit; a technology mapping unit that holds the logic circuit optimized by the technology-independent optimizing unit as the boundary information and allocates the logic circuit to each function block in a semiconductor library; A timing optimization unit that optimizes the result of the technology mapping unit by using a technique such as fan-out adjustment, fan-in / reordering, decomposition-based composition, inverter change, etc. The boundary information in the attached internal database 3. The automatic logic circuit according to claim 1, further comprising: a net name setting unit that saves the net name of the internal database with the boundary information, and a logic circuit output unit that outputs the optimized logic circuit. Synthetic system. 4. A logic circuit in which the synthesized logic circuit and the original hardware description language can be associated with each other very easily, and the result of synthesis can be checked and corrected manually. An automatic synthesis method, comprising: logic-synthesizing component information from component information of a logic circuit described in the hardware description language, and outputting the component information as the optimized logic circuit; A step of displaying an intermediate signal of each piece of component information of the hardware description language in the output logic circuit at the time of output of the logic circuit. 5. The automatic logic circuit synthesis method according to claim 4, further comprising a step of storing an intermediate signal name in the original hardware description language as a net name in the logic circuit after the logic synthesis. . 6. A compiling step of inputting the hardware description language to create an internal database with boundary information of an intermediate signal, and holding the boundary information in the internal database with boundary information and optimizing the logic circuit. A technology-independent optimization step, a technology mapping step of retaining the optimized logic circuit by the technology-independent optimization step as the boundary information and assigning the logic circuit to each function block in a semiconductor library; and A timing optimization step of optimizing the result of the technology mapping step by using a technique such as fan-out adjustment, fan-in / reordering, decomposition taking into account timing, inverter change, etc., while maintaining the boundary information. In the internal database 6. The method according to claim 4, further comprising a net name setting step of storing the boundary information in a net name of the internal database with boundary information, and a logic circuit output step of outputting the optimized logic circuit. Logic circuit automatic synthesis method.