JPH09251061A - Test pattern generator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the using memory capacity used for a test pattern generator by shortening the processing time of generating the pattern. SOLUTION: A GL fault list 105 and RTL fault list 112 are input by a difference extractor 113, the difference is extracted to form a differential fault list 114, a test pattern is generated by a GL test pattern generator 106 based on the list 114, and a test pattern is generated by an RTL test pattern generator 115 based on the list 112. These patterns are used as test patterns used to detect the fault of the logic circuit. Thus, the process of the generator 106 is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test pattern generation device, and more particularly to a device that generates a test pattern for detecting a failure in a logic circuit.

[0002]

2. Description of the Related Art A device using a gate level hardware description language (HDL) description is known as a device for automatically generating a test pattern for checking a failure of a logic circuit (D-algorithm, PODEM). , FA
N etc.). There is also a method in which a part of the gate-level description is replaced with a high-level cell registered as a library in advance, and a test pattern generation process is performed by using a truth table in the library.

Here, a block diagram of a conventional test pattern generation device is shown in FIG. This test pattern generator is
A logic synthesis unit 2 which inputs a predetermined RT level HDL (RTL) 1 to perform logic synthesis and outputs a gate level HDL description (GL) 3 and a location where a test should be performed by inputting GL 3 are extracted. The GL 3 is provided with a GL fault extractor 4 that creates a fault list 5 and a test pattern generator 6 that generates a test pattern 7 for detecting a given fault using the GL fault list 5. Generate a test pattern.

As described above, in the conventional test pattern generation device, the test pattern is generated by using the gate level HDL description.

[0005]

However, with the recent progress in microfabrication technology, large-scale and complex logic circuits have been designed, and a test pattern generator using a gate level requires a huge amount of processing time. In addition, the amount of memory used becomes enormous, which is becoming a problem.

As a method of solving this, a part of the description of the gate level HDL is replaced with a cell of a higher level (for example, an adder or the like) to shorten the processing time, and
It is possible to reduce the amount of memory used. But,
With this method, only high-level cells registered in the library in advance can be used, so the number of high-level cells that can be replaced is limited,
I can't expect much effect.

The present invention has been made in view of the above circumstances, and an object of the present invention is to shorten the processing time of test pattern generation and reduce the amount of memory used in the test pattern generation apparatus. Is.

[0008]

In order to achieve the above object, a feature of the present invention is that in an apparatus for generating a test pattern used for detecting a failure of a logic circuit, an RT level describing the logic circuit is provided. A logic synthesizer for inputting an HDL description to perform logic synthesis and outputting a gate level HDL description, and a gate level HDL description outputted by the logic synthesizer for extracting a portion to be tested, The GL fault extractor that creates the GL fault list and the RT level HDL description that describes the logic circuit are input, and the RT level HDL is selected from among the points to be tested.
Extract the locations where a failure list can be created in the description, and use RTL
An RTL failure extraction unit that creates a failure list, a difference extraction unit that inputs the GL failure list and the RTL failure list, extracts the differences between them, and creates a differential failure list, and a difference extraction unit that creates the failure list. A GL test pattern generation unit that generates a test pattern based on the differential fault list, and an RTL test pattern generation unit that generates a test pattern based on the RTL fault list created by the RTL fault extraction unit, The test patterns generated by the GL test pattern generation unit and the RTL test pattern generation unit are used as test patterns used for detecting a failure in the logic circuit.

It is generally said that, when an RT level HDL description is converted into an equivalent gate level HDL description, the converted gate level HDL description amount is about 10 times the amount of the RTL description before conversion. The number of connections will also increase accordingly. Therefore, the test pattern generation process using the gate-level HDL description requires a large amount of memory to be used and a considerable amount of processing time.

In the present invention, the RT level HD is used as much as possible.
By generating the test pattern using the L description, the amount of memory used can be reduced by reducing the processing in the GL test pattern generation unit, and the processing time can be shortened.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a test pattern generation device according to the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a test pattern generation device according to this embodiment. This test pattern generation apparatus is an RT-level HDL description (RTL) 1 that describes a predetermined logic circuit.
01 is input to perform logic synthesis and a gate-level HDL description (GL) 103 is output, and the GL 103 output from the logic synthesis unit 102 is input to extract a portion to be tested, The GL fault extraction unit 104 that creates the GL fault list 105 and the RT-level HDL description 101 are input to extract a portion to be tested,
RTL failure extractor 1 for creating RTL failure list 112
11, GL failure list 105 and RTL failure list 1
12 is input, a difference extraction unit 113 that extracts the differences and creates a difference fault list 114, a GL test pattern generation unit 106 that generates a test pattern based on the difference fault list 114, and an RTL fault list 112. RTL test pattern generation unit 1 for generating a test pattern based on
15, a test pattern 107 generated by the GL test pattern generation unit 106 and a test pattern 116 generated by the RTL test pattern generation unit 115 are used for detecting a failure of the predetermined logic circuit. I am trying to.

Here, the logic synthesizing unit 102 converts the RT level HDL description representing the function of the logic circuit into an HDL description representing the actual structure of the logic circuit. Generally, if an RT level HDL description is converted into an equivalent gate level HDL description, the converted gate level H
It is said that the amount of DL description is about 10 times the amount of RTL description before conversion. The number of connections will also increase accordingly. Therefore, the test pattern generation process using the RT level HDL description uses less memory than the test pattern generation process using the gate level HDL description.
In addition, the processing time can be shortened. Further, the logic synthesis unit 102 may create data representing the correspondence relationship between the RT level HDL description and the gate level HDL description. This is, for example, when one or more statements in the RT level description and one or more statements in the gate level HDL description represent the same function, a correspondence relationship between a set of these two statements. Create data that represents. By providing this data to the difference extraction unit, the difference can be extracted more efficiently.

The GL fault extractor 104 uses a gate-level HDL description to indicate a fault list 105 of a predetermined logic circuit.
Create The GL failure extraction unit 104 may be implemented using a known technique.

The RTL failure extraction unit 111 creates a failure list as much as possible using the RT level HDL description.
Therefore, a part of the failure list of a predetermined logic circuit is registered in the RTL failure list 112.

The difference extraction unit 113 uses the GL failure list 10
Of the failure lists registered in 5, RTL failure list 1
The fault list excluding the fault list registered in 12 is registered as the differential fault list. Therefore, this differential fault list 114 is compared with the GL fault list 105 by RT
It is reduced by the same failure list as the L failure list 112.

The GL test pattern generator 106 is used to generate a test pattern for only those registered in the differential fault list 114. Therefore, since the gate level description of all logic circuits is not used, the processing time and the amount of memory used can be further reduced.

The RTL test pattern generation unit 115
Test pattern generation for detecting a given fault is performed using the level HDL description.

As described above, the GL test pattern 107 and R generated by the GL test pattern generation unit 106 are generated.
The RTL test pattern 116 generated by the TL test pattern generation unit 115 can be used to generate a test pattern 117 for the entire logic circuit used to detect a failure in the logic circuit.

Next, the operation of the test pattern generation device according to the present invention will be described using a specific example. First, RT
It is assumed that the level HDL description RD is converted into the gate level HDL description GD by the logic synthesis unit 102. At this time, the RD portion is associated with the GD portion having a function equivalent to that. In FIG. 2, RD parts Bi and GD
The part Bi has the same function.

In the RTL failure extraction section 111, each Bi =
A fault list having the input / output stuck-at fault and the functional fault of (i = 0, ..., N) as elements of the fault list is created. Further, in the GL failure extraction unit 104, each Bi (i = 0, ...,
A fault list in which the stuck-at fault of the connection of n) is an element of the fault list is created.

Generally, there is no one-to-one correspondence between RT level failures and gate level failures. Therefore, the RT level failure alone may not be sufficient. In such a case, gate level test pattern generation is required.

Subsequently, in the difference extracting unit 113, the generated test pattern is subjected to a failure simulation on the RT level failure list using the RT level HDL description, so that the RT level which can be detected is detected. Perform processing to remove the failure from the failure list.

Then, the GL test pattern generation unit 106 performs the following processing for each Bi (i = 0, ..., N).

1. R for the obtained test pattern
Bi that can be detected as a result of T-level failure simulation
2. Let RF be the set of faults and GF be the set of gate-level faults of Bi. RT level HD for the obtained test pattern
2. Perform a simulation using the L description to obtain the input / output values of Bi. 3. For each RF failure, perform a failure simulation using the description of the RT level Bi part. For each failure of GF, a failure simulation is performed using the description of the part of Bi at the gate level. 3
If it matches the result of the RT level fault simulation for Bi performed in the above step, it is removed from the gate level fault list. For example, an RT level HDL including a description of a 4-bit adder
The description will be given as an example. The 4-bit adder part of the RTL description is as shown in FIG. 4, and the description of the 4-bit adder part of the gate level is expressed in a circuit diagram as shown in FIG.

Now, the stuck-at-1 fault (s) of the I0 (0) signal line is
Consider generating a test pattern that detects -a-1). First, when the RT-level HDL description is used, for example, the values of I0 (0: 1) = 00 and I1 (0: 1) = 00 result in a failure difference (1/0) of O (0). It is immediately apparent from the description shown in FIG. When I0 and I1 are not input, the input signal value can be obtained by further using the RT level HDL description. Also O
When (0) is not the output, the input value for propagating the fault difference to the output can be obtained using the RT level description.

If the same thing is attempted using the gate level description, I (0) = 0 can be obtained from s-a-1 of I0 (0). G2 in order to propagate the fault difference (0/1)
The values of L16 and I1 (0), which are inputs of 1, may be set to L16 = 0, I1 (0) = 0, for example. In order to set L16 = 0, L9 = 1, L10 = 1, L11 = 1, to further set L9 = 1, 7 = 0, L8 = 0, and to set L7 = 0, for example, L2 You can set = 0. When L2 = 0, L10 = 1 and L11 = 1, which are consistent. Further, in order to set L2 = 0, for example, pI0 (1) = 0, I1 (1) = 0 and when I0 (1) = 0, L8 = 0, which is consistent. From the above, I0 (0: 1) = 00 and I1 (0: 1) = 00 are obtained. It can be seen that it takes much time and effort to generate a test pattern using the gate level HDL description as compared with the case of using the RT level HDL description.

The GL test pattern generator 106 will be described using a more detailed example. The input / output values of the 4-bit adder are I0 (0: 3) = 0000 and I1 (0: 3) = 000 by the test pattern TP obtained by the RT-level test pattern generation.
It is assumed that 0, CI = 0, and O (0: 3) = 0000. Also, as a RT level failure of the 4-bit adder portion due to TP, RF = {I0 (0) 1, I0 (1) 1, I0 (2) 1,
I0 (3) 1, I1 (0) 1, I1 (1) 1, I1
(2) 1, I1 (3) 1, CI1, 0 (0) 1,0
It is assumed that (1) 1,0 (2) 1,0 (3) 1} can be detected.

[0028]

[Table 1] The result of the fault simulation using the gate level description of the 4-bit adder is as follows.

[0029]

[Table 2] From this result, among the gate level failures of the 4-bit adder using TP, I0 (0) 1, I1 (1) 1, CI
1, O (0) 1, L71, L81, L90, L100,
L110, L161, I0 (0) 1, I1 (1) 1, O
(1) 1, L21, L130, L170, L181, I
0 (2) 1, I1 (2) 1, O (2) 1, L00, L10
, L41, L190, L201, I0 (3) 1, I1
It can be seen that (3) 1, O (3) 1 and L61 can be detected.

As described above, according to this embodiment, if the RT level is designed, what kind of RT level HDL
As for the description, the test pattern generation process can be performed using the RT level description as much as possible. Therefore, the amount of memory used can be suppressed as compared with the conventional method. In addition, the processing efficiency can be improved as compared with the conventional method.

[0031]

As described above, according to the test pattern generation device of the present invention, the processing time for generating the test pattern can be shortened and the amount of memory used in the test pattern generation device can be reduced. .

[Brief description of drawings]

FIG. 1 is a block diagram showing a test pattern generation device according to the present invention.

FIG. 2 HDL description at RT level and HD at gate level
It is the figure which showed the correspondence of L description.

FIG. 3 is a diagram showing a part of an RT-level HDL description (4-bit adder).

FIG. 4 is a circuit diagram showing a part of a gate-level HDL description (4
It is the figure represented by the bit adder).

FIG. 5 is a block diagram showing a conventional test pattern generation device.

[Explanation of symbols]

1, 101 RTL (register transfer level HDL description) 1, 102 logic synthesis section 3, 103 GL (gate level HDL description) 4, 104 GL failure extraction section 5, 105 GL failure list 6, 106 GL test pattern generation section 7,107 GL test pattern 111 RTL failure extraction unit 112 RTL failure list 113 Difference extraction unit 114 Differential failure list 115 RTL test pattern generation unit 116 RTL test pattern 117 Test pattern

Claims (1)

[Claims] 1. An apparatus for generating a test pattern used to detect a failure of a logic circuit, wherein an RT level HDL description describing the logic circuit is input, logic synthesis is performed, and a gate level HDL description is output. A logic synthesizing unit, a GL fault extracting unit that inputs a gate-level HDL description output from the logic synthesizing unit, extracts a portion to be tested, and creates a GL fault list, and describes the logic circuit. Enter the RT-level HDL description that was written, and select the RT-level HD from among the areas to be tested.
Extract the place where the failure list can be created by L description, and RT
An RTL failure extraction unit that creates an L failure list, a difference extraction unit that inputs the GL failure list and the RTL failure list, extracts the differences between them, and creates a differential failure list, and a difference extraction unit A GL test pattern generation unit that generates a test pattern based on the generated differential fault list; and an RTL test pattern generation unit that generates a test pattern based on the RTL fault list created by the RTL fault extraction unit. A test pattern generation device, wherein the test patterns generated by the GL test pattern generation unit and the RTL test pattern generation unit are used as test patterns used for detecting a failure of the logic circuit.