JPH05259184A - Manufacture of insulated gate type field effect semiconductor device - Google Patents

Abstract

PURPOSE:To provide a method for manufacturing an insulated gate type field effect semiconductor device which has a small OFF current and in which ON/ OFF response can be carried out at a high speed. CONSTITUTION:The method for manufacturing an insulated gate type field effect semiconductor device comprises the steps of forming a nonsingle crystalline semiconductor 2 in which hydrogen or halogen element is added on an insulating board 1, forming a gate insulating film 3 on the semiconductor, forming a gate by selectively forming a gate electrode 4 on the insulating film, adding impurities to an entire region formed with the semiconductor including a region to become a source or a drain, and promoting crystallization of the semiconductor of the other part with the gate as a mask by optically annealing the entire semiconductor region.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an insulated gate field effect semiconductor device used in semiconductor integrated circuits, liquid crystal display panels and the like.

[0002]

2. Description of the Related Art Insulated gate type field effect semiconductor devices using single crystal silicon are widely used in the field of semiconductors. A representative example thereof is Japanese Patent Publication No. 50-1986 relating to the invention of the present applicant.
There is a "semiconductor device and its manufacturing method" disclosed in Japanese Patent Publication No. However, instead of using a single crystal semiconductor in a channel formation region to which hydrogen is not added, an insulated gate field effect semiconductor provided with a non-single crystal semiconductor to which hydrogen or a halogen element is added at a concentration of 1 atomic% or more. As for the device, Japanese Patent Application No. 53-
A typical example thereof is "Semiconductor Device and Manufacturing Method Thereof" (filed on October 7, 1978) disclosed in Japanese Patent No. 124021. Such an insulated gate field effect semiconductor device in which a non-single crystal semiconductor to which hydrogen or a halogen element is added, particularly a silicon semiconductor is used for a channel formation region has a lower off current than a conventionally known single crystal semiconductor. 10 ³ ~
It is as small as ^1/5 . Therefore, it is said that the insulated gate field effect semiconductor device is effectively used for controlling a liquid crystal display panel.

This insulated gate field effect semiconductor device is
As disclosed in the above-mentioned Japanese Patent Application No. 53-124021, a lateral channel type insulated gate field effect semiconductor device in which a gate electrode is provided on the upper side of a semiconductor in a channel formation region, and Japanese Patent Application Sho 56-001767
Gazette "Insulated gate type semiconductor device and its manufacturing method"
Vertical channel type insulated gate field effect semiconductor device shown in (Jan. 9, 1981), and so-called generally known thin film insulation in which a gate electrode is provided below a semiconductor forming a channel formation region. Gate type field effect semiconductor devices are known.

However, compared to the latter two of them, the former one has the same structure as the conventionally known insulated gate type field effect semiconductor device using single crystal silicon, and therefore the already completed technique can be applied. It had an extremely excellent feature. Further, as a conventional example, in the field effect transistor described in Japanese Patent Laid-Open No. 58-2073, the source region and the drain region are selectively annealed to form a polycrystalline region and the channel forming region is an amorphous region. I am trying. That is, in the field effect transistor disclosed in the publication, a part of the amorphous region is selectively annealed to form a polycrystalline region.

[0005]

On the other hand, in such an insulated gate field effect semiconductor device, the source region and the drain region are formed by the CVD method (including the plasma CVD method).
The thin film is not deposited by means of ion implantation but added by an ion implantation method, and the additive is annealed within a temperature range not degassing hydrogen or halogen elements below 400 ° C.
Must be an active donor or acceptor depending on the group. In order to solve the above problems, it is an object of the present invention to provide a method for manufacturing an insulated gate field effect semiconductor device which has a small off current and can be turned on and off with a high-speed response. ..

[0006]

In order to solve the above problems, a method of manufacturing an insulated gate field effect semiconductor device according to the present invention is a non-single crystal in which hydrogen or a halogen element is added to an insulating substrate. A step of forming a semiconductor, a step of forming a gate insulating film on the non-single-crystal semiconductor, a step of forming a gate portion by selectively forming a gate electrode on the gate insulating film, a source or A step of adding an impurity to the entire region where the non-single crystal semiconductor is formed including a region to be a drain, and a photo-annealing process to the entire non-single crystal semiconductor region are performed so that the gate portion is used as a mask. And a step of promoting crystallization of the other portion of the non-single-crystal semiconductor.

Specific examples of means for solving the problems of the present invention are as follows. A gate insulator and a gate electrode on a non-single-crystal semiconductor without or with little impurities (hereinafter, a non-single-crystal semiconductor to which hydrogen or a halogen element is added are simply referred to as a semiconductor or a non-single-crystal semiconductor). It was provided selectively. Further, by using this gate electrode as a mask, a source by an ion implantation method,
For example, phosphorus or arsenic is used in an N channel type insulated gate field effect semiconductor device to which an impurity for drain is added, and boron is added to the source and drain regions of a non-single crystal semiconductor in a P channel type insulated gate field effect semiconductor device. Was added through the gate insulating film.

After that, the entire region of the substrate including the region to which the inactive impurities are added is irradiated with intense light at a temperature of 400 ° C. or less, and a strong ultraviolet light anneal (hereinafter, simply referred to as optical anneal). -L). Thus, all the non-single crystal semiconductor regions are irradiated with light except for the channel formation region shielded by the gate portion. Then, the non-single-crystal semiconductors forming the impurity regions for the source and the drain are all irradiated with light, and the degree of crystallinity of those regions is accelerated more than that of the channel formation region. It was transformed into a semiconductor. That is, according to the present invention, ions are implanted into a conventionally known single crystal semiconductor to which hydrogen or a halogen element is not added, and strong light annealing is performed on the semiconductor. Since this optical annealing is performed over the entire surface of the substrate, light is scanned from one end of the substrate surface to the other end to include crystal growth in the process and promote crystallinity to form an impurity region.

[0009]

[Operation] As a result, in the method for manufacturing an insulated gate field effect semiconductor device according to the present invention, the gate electrode was provided above the non-single-crystal semiconductor forming the channel formation region on the substrate. Further, the impurity region of the present invention has almost the same optical energy as 1.6 to 1.8 eV with respect to the optical energy of this non-single crystal semiconductor (1.7 to 1.8 eV in the case of a silicon semiconductor),
And it became an active area. Thus, since the optical energy is the same as or roughly the same as the channel formation region,
On-state current does not easily flow when the insulated gate field effect semiconductor device is turned “ON” or “OFF”, and on the other hand, the current does not flow dully when the current falls. That is, the insulated gate field effect semiconductor device of the present invention has a small off current and can be turned on and off with a high speed response. The present invention will be described below with reference to examples.

[0010]

EXAMPLE FIG. 1 is a vertical cross-sectional view for explaining a manufacturing process of an insulated gate field effect field effect semiconductor device which is an embodiment of the present invention. The substrate (1) is made of quartz glass, for example, and its thickness is 1.1 m as shown in FIG. 1 (A).
The size was 10 cm × 10 cm. This board
On the upper surface of (1), hydrogen concentration of 1 atomic% or more was obtained by photoplasma CVD without dimer (Si ₂ H ₆ ) mercury excitation method (low pressure mercury lamp including wavelength of 2537Å, substrate temperature 210 ° C). Non-single-crystal semiconductors containing amorphous structure added to (2)
Were formed to a thickness of 0.2 μm, for example.

Further, a gate insulating film (3) made of, for example, a silicon nitride film is laminated on the upper surface of the non-single crystal semiconductor (2) by the photo-CVD method without exposing the semiconductor surface to the atmosphere in the same reaction furnace. It was That is, the gate insulating film (3) is
The reaction of disilane (Si ₂ H ₆ ) with ammonia (NH ₃ ) or hydrazine (N ₂ H ₄ ) (low pressure mercury lamp containing a wavelength of 2537 Å, substrate temperature 250 ° C) was used to sensitize Si ₃ N ₄ with mercury. Was made to a thickness of 1000Å without using. Thereafter, a region for forming an insulated gate field effect semiconductor device is formed.
The portion except (5) was removed by the plasma etching method. Plasma etching reaction is CF ₄ + O ₂ (5%)
The reaction gas was introduced, and a frequency of 13.56 MHz was applied to a parallel plate electrode (not shown) at room temperature. The gate insulating film (3) may be formed over the entire surface of the substrate (1).

On the gate insulating film (3), N ⁺ conductive type microcrystalline or polycrystalline semiconductor was laminated to a thickness of 0.3 μm. In this N ⁺ semiconductor film, the gate electrode (4) was formed after removing the undesired portion by photoetching using the resist film (6). After that, with this resist film (6),
By using the gate portion composed of the gate electrode (4) of the N ⁺ semiconductor and the gate insulating film (3) as a mask, a region of a source and a drain of 1 × 10 ²⁰ cm ⁻³ was formed by ion implantation. As shown in FIG. 1 (B), an impurity of one conductivity type, for example, phosphorus was added to the concentration to form a pair of impurity regions (7) and (8).

Further, the substrate (1) was subjected to a photo-annealing process of strong ultraviolet light (10) after the resist film (6) of the gate electrode (4) was removed. That is, ultra-high pressure mercury lamp (output 5KW, wavelength 250 ~ 600nm, light diameter 15mm,
180 mm in length, the back side uses a parabolic reflector and uses a quartz cylindrical lens (focal length 150 c
m, the condensing part width 2 mm, and the length 180 mm), the irradiation part was formed linearly. Then, the irradiation surface of the substrate (1) is scanned at a speed of 5 to 50 cm / min in a direction orthogonal to the linear irradiation portion, and strong light (10) is applied to the entire surface of the substrate 10 cm × 10 cm. It was irradiated.

In this way, since the gate electrode (4) has a large amount of phosphorus added to the side of the gate electrode (4), it has sufficiently absorbed light to be polycrystallized. Further, the impurity regions (7) and (8) are
By melting and recrystallization once, melting and recrystallization were shifted (moved) in the scanning direction, that is, the X direction.
As a result, the crystal grain size could be increased because a growth mechanism was added as compared with the case where the entire surface was uniformly heated or irradiated with light. A non-single-crystal semiconductor is selectively formed on an insulating substrate, and the non-single-crystal semiconductor of the other part acts as a source region or a drain region except for a channel forming region covered with the gate part of the non-single-crystal semiconductor. The crystallization of all the non-single-crystal semiconductors in this impurity region can be promoted. The region polycrystallized by this strong light anneal is
It is not necessary to extend to the entire area below the impurity regions (7) and (8). In FIG. 1, as indicated by broken lines (11) and (11 '), only the upper layer is crystallized, and the impurity region
It is important to activate (7) and (8).

Further, the end portions (15) and (15 ') of the source region and the drain region are the end portions (16) and (1
6 ') is provided so as to enter the channel region side. Further, the channel forming region including the N-type impurity regions (7) and (8), the I-type non-single-crystal semiconductor region (2), the junction interfaces (17) and (17 ') is a non-single-crystal region in the I-type semiconductor region. It has a hybrid structure composed of a semiconductor and a crystallized semiconductor that enters from an impurity region. The degree of crystallized semiconductor in the I-type semiconductor region is determined by the scanning speed and intensity (illuminance) of the optical anneal.

After the step of FIG. 1B, the polyimide resin is coated on the entire surface to a thickness of 2 μm. Then, in the polyimide resin, after the electrode holes (13) and (13 ') are formed,
Aluminum ohmic contacts and their leads (1
4) and (14 ') are formed. This second layer lead (14), (1
4 ′) may be connected to the gate electrode (4) when formed. The result of this optical annealing is that the sheet resistance is 4 × 10 ^-3 (ohm cm) ^-1 to 1 × 10 ⁺² (ohm cm) before light irradiation.
It became ^-1 , and the electric conductivity characteristics were improved compared to before the photo-annealing. When the length of the channel forming region is 3 μm and 10 μm, under the condition that the channel width is 1 mm, as indicated by reference numerals (21) and (22) in FIG. 2, respectively,
A current of 1 × 10 ⁻⁵ A and 2 × 10 ⁻⁵ A could be obtained at V _th = + 2 V and V _DD = 10 V. The off current is (V _GG = 0
V) 10 ^-10 to 10 ^-11 (A), which is 10 ^-6 (A) of a single crystal semiconductor.
It was 1 of 10 ^-4 , which was smaller than that of.

In the present embodiment, since the linearly condensed light is irradiated so as to scan the entire surface of the substrate, a large area and large scale integration can be performed. Therefore, it is possible to fabricate 500 × 500 insulated gate field effect semiconductor devices in a large area of 30 cm × 30 cm, for example. I was able to apply. Since it was a low temperature treatment of 400 ° C. or less by the photo-annealing process, a polycrystallized or single-crystallized semiconductor could be formed containing hydrogen or halogen element inside. Also, the optical annealing is not performed on the entire surface of the substrate at the same time,
Scan from one end to the other. Therefore, the light emitted from the cylindrical ultra-high pressure mercury lamp was condensed into a linear shape by the parabolic mirror and the quartz lens. The linearly condensed light was able to optically anneal the surface of the non-single crystal semiconductor by scanning the substrate in a direction orthogonal to the light.

Since this optical annealing is performed with ultraviolet rays, crystallization is promoted inward from the surface of the non-single crystal semiconductor. Therefore, the sufficiently polycrystallized or single-crystallized impurity region near the surface can control the current flowing in the channel formation region in the immediate vicinity of the gate insulating film without any trouble. Light irradiation annealing - Upon le step, hydrogen or a halogen element added to the channel formation region is not affected at all, since it is possible to hold the non-single-crystal semiconductor state, 1/10 ³ to the off-current single-crystal semiconductor It can be 1/10 ⁵ . Since the source region and the drain region are formed by optical annealing after forming the gate electrode and the gate insulating film, dirt is not attached to the interface of the gate insulator,
Stabilize the characteristics. Further, as compared with the conventionally known method, not only quartz glass but also any substrate such as soda glass and heat resistant organic film can be used as the substrate material.

The non-single-crystal semiconductor-gate insulating film-gate electrode forming the channel forming region, which is the interface of different materials, can be formed by the process in the same reaction furnace without exposing to the atmosphere. It has the characteristic that the number of positions is small. In this embodiment, it is important that the non-single crystal semiconductor in the channel formation region has an impurity concentration of 5 × 10 ¹⁸ cm ⁻³ or less for all of oxygen, carbon, and nitrogen. That is, these are 1 to 3 in the channel layer in the conventionally known insulated gate field effect semiconductor device.
It was mixed at a concentration of × 10 ²⁰ cm ^-3 . In the case of using an amorphous silicon semiconductor, carriers which are particularly important in a P channel type insulated gate field effect semiconductor device are used.
The lifetime of the module is shortened, and the characteristic is one of the characteristics of the insulated gate field effect semiconductor device of this embodiment.
Only a current of / 3 or less flows. In addition, the hysteresis characteristic was observed when the drain electric field was applied to the I _DD -V _GG characteristic at 2 × 10 ⁶ V / cm or more. On the other hand, oxygen is 5
Hysteresis was not observed even at a voltage of 3 × 10 ⁶ V / cm when it was set to × 10 ¹⁸ cm ^-3 or less.

[0020]

According to the present invention, since the optical annealing treatment for promoting crystallization is not selectively performed, there is no need for alignment, and the non-single-crystal semiconductor layer and the non-single-crystal semiconductor layer do not exist. Light irradiation can be performed on the entire area including the area. That is, crystallization of a large number of non-single-crystal semiconductor regions can be promoted simply by scanning focused linear light without making individual ones of the insulated gate field effect semiconductor devices. You can Further, according to the present invention, since there is no non-single-crystal region having a high resistance other than the channel forming region, there is no hysteresis in the gate voltage-drain current characteristic of the insulated gate field effect semiconductor device,
Good switching characteristics at high frequency were obtained. Furthermore, according to the present invention, since the channel formation region is activated by the addition of hydrogen or a halogen element,
The high frequency switching characteristics of the insulated gate field effect semiconductor device have been improved.

[Brief description of drawings]

FIG. 1 is a vertical cross-sectional view for explaining a manufacturing process of an insulated gate field effect field effect semiconductor device which is an embodiment of the present invention.

FIG. 2 is a diagram showing characteristics of drain current-gate voltage.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Substrate 2 ... Non-single crystal semiconductor 3 ... Gate insulating film 4 ... Gate electrode 5 ... Area | region which forms an insulated gate field effect semiconductor device 6 ... Resist film 7, 8・ ・ ・ Impurity region 10 ・ ・ ・ Strong light 11 ・ ・ ・ Dashed line 13, 13 ′ ... Electrode hole 14, 14 ′ ... Lead 15, 15 ′ ... Ends of source and drain regions 16, 16 '... end of gate electrode 17, 17' ... junction interface

Claims (1)

[Claims] 1. A step of forming a non-single-crystal semiconductor to which hydrogen or a halogen element is added on an insulating substrate, a step of forming a gate insulating film on the non-single-crystal semiconductor, and a step of selectively forming on the gate insulating film. Forming a gate portion by forming a gate electrode on the substrate, adding an impurity to the entire region where the non-single crystal semiconductor is formed including a region to be a source or a drain, and the non-single crystal An insulated gate field effect semiconductor device comprising: a step of accelerating the crystallization of the non-single-crystal semiconductor of the other part by using the gate part as a mask by performing an optical annealing process on the entire semiconductor region. Of manufacturing.