JPH0525372B2 - - Google Patents
Info
- Publication number
- JPH0525372B2 JPH0525372B2 JP62219896A JP21989687A JPH0525372B2 JP H0525372 B2 JPH0525372 B2 JP H0525372B2 JP 62219896 A JP62219896 A JP 62219896A JP 21989687 A JP21989687 A JP 21989687A JP H0525372 B2 JPH0525372 B2 JP H0525372B2
- Authority
- JP
- Japan
- Prior art keywords
- capacitor
- plating
- coupling agent
- multilayer ceramic
- multilayer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000003990 capacitor Substances 0.000 claims description 26
- 238000007747 plating Methods 0.000 claims description 22
- 239000003985 ceramic capacitor Substances 0.000 claims description 21
- 239000007822 coupling agent Substances 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 12
- 239000000919 ceramic Substances 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 229910000679 solder Inorganic materials 0.000 description 10
- 238000011282 treatment Methods 0.000 description 10
- 239000006087 Silane Coupling Agent Substances 0.000 description 3
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 238000010304 firing Methods 0.000 description 3
- 229910052745 lead Inorganic materials 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 230000002378 acidificating effect Effects 0.000 description 2
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 description 2
- 229910002113 barium titanate Inorganic materials 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 238000005336 cracking Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000007598 dipping method Methods 0.000 description 2
- 238000001035 drying Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000007654 immersion Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 230000035515 penetration Effects 0.000 description 2
- 239000000843 powder Substances 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- 241000080590 Niso Species 0.000 description 1
- 229910020220 Pb—Sn Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000006071 cream Substances 0.000 description 1
- 238000007606 doctor blade method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003792 electrolyte Substances 0.000 description 1
- NKSJNEHGWDZZQF-UHFFFAOYSA-N ethenyl(trimethoxy)silane Chemical compound CO[Si](OC)(OC)C=C NKSJNEHGWDZZQF-UHFFFAOYSA-N 0.000 description 1
- WOXXJEVNDJOOLV-UHFFFAOYSA-N ethenyl-tris(2-methoxyethoxy)silane Chemical compound COCCO[Si](OCCOC)(OCCOC)C=C WOXXJEVNDJOOLV-UHFFFAOYSA-N 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 125000000956 methoxy group Chemical group [H]C([H])([H])O* 0.000 description 1
- 125000000325 methylidene group Chemical group [H]C([H])=* 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 239000004014 plasticizer Substances 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- BPSIOYPQMFLKFR-UHFFFAOYSA-N trimethoxy-[3-(oxiran-2-ylmethoxy)propyl]silane Chemical compound CO[Si](OC)(OC)CCCOCC1CO1 BPSIOYPQMFLKFR-UHFFFAOYSA-N 0.000 description 1
Description
産業上の利用分野
本発明は、チツプ型および外装型積層セラミツ
クコンデンサの製造方法に関する。更に詳しくは
外部電極に対する金属メツキの工程においてメツ
キ液の侵入のない信頼性に優れた積層セラミツク
コンデンサの製造方法に関する。
従来の技術
近年、セラミツクコンデンサは電子機器並びに
回路の小型化、高速化、信頼性向上のため不可欠
な部品として広く使用されるようになつた。
第3図は、外部電極を取り付ける前の積層セラ
ミツクコンデンサの概略斜視図、第4図は外部電
極を取り付けた積層セラミツクコンデンサの概略
斜視図である。
かかる積層セラミツクコンデンサ1を製造する
には、チタン酸バリウム系等のセラミツク粉末に
有機溶剤、可塑剤、バインダー等を加えて混練
し、泥しよう化した後、ドクターブレード法等を
用いて長尺のセラミツクグリーンシート2を得
る。つぎにこのグリーンシートを所定の大きさに
切断し、その上の所定の位置にスクリーン印刷法
等により内部電極3を被着形成する。しかる後、
この素子を複数枚積層し、その上下に保護層とし
てグリーンシート膜を積層し、加圧一体化して積
層体を得る。次にこの積層体を所定の寸法に切断
分離し、積層セラミツクコンデンサ生チツプを得
る。ついで、該生チツプをセラミツク粉末の焼成
に適した温度で焼成する。さらに、第4図に示す
ごとく、得られたコンデンサチツプの両端の内部
電極導出部にAgあるいはAg−Pdからなる外部接
続用電極4を被着して積層セラミツクコンデンサ
が得られる。
このようにして製造された積層セラミツクコン
デンサは、プリント配線基板上の導体ランド上に
外部電極を対向して配置され、熔融した半田に浸
漬する半田浸漬法か、クリーム半田を用いたリフ
ロー半田法を用いて電子機器中に組み込まれる。
しかしながら、外部電極を直接半田付けにより
基板に取り付けると、外部電極が“半田くわれ”
によつて薄くなり、コンデンサの取付強度が弱く
なるという問題がある。このような積層セラミツ
クコンデンサ外部電極の半田くわれを防止するた
め、従来導電AgペーストまたはAg−Pdペースト
を用いて形成した外部電極上に、さらにNiまた
はCuメツキを施して半田くわれ防止バリアとし、
更にこの上に半田メツキ(またはSn,Pbメツキ)
を行いハンダの流れをよくした積層チツプコンデ
ンサがある。
発明が解決しようとする問題点
しかしながらNi,Cuなどのメツキを行うにあ
たつては、PH4.5程度の酸性電解メツキ液中に、
また半田メツキを行うにはPH1〜4またはそれ以
下の酸性電解メツキ液中に積層チツプコンデンサ
を浸漬する必要があり、メツキ液が積層コンデン
サ内に浸入し電気容量の低下、電流損失の増大な
どコンデンサ性能の劣化を招く。
本発明は、かかる従来の積層セラミツクコンデ
ンサのメツキ工程における品質低下を防止し、容
易に信頼性の高いコンデンサを得る方法を提供す
ることを目的とする。
問題点を解決するための手段
本発明は、積層セラミツクコンデンサの製造方
法であつて、セラミツクシートと内部電極とが積
層した板状コンデンサ集合体に外部電極を被着す
る工程と、該外部電極に金属メツキを行う工程と
の間にカツプリング剤にて処理する工程を設けた
ことを特徴とする積層セラミツクコンデンサの製
造方法を提供するものである。
本発明において、外部電極を被着し焼成された
積層セラミツクコンデンサは、従来の方法により
製造されたものであつてよい。例えば、セラミツ
クグリーンシートと内部電極(Ag−Pd,Pb,
Ni,Cuなど)とが積層した板状コンデンサ集合
体の内部電極導出部を外部電極用のAgまたはAg
合金のペーストに浸漬または塗布し、600〜850℃
にて焼き付けを行う。
つぎに、このようにして得られた積層セラミツ
クコンデンサをカツプリング剤にて処理する。カ
ツプリング剤としては、各種のシランカツプリン
グ剤をいずれも使用することができ、例えば
ClC3H6Si(OCH3)3,CH2=CHSiCl3,
CH2=CHSi(OC2H5)3,CH2=CHSi(OCH3)3,
CH2=CHSi(OC2H4OCH3)3,
CH2=CCH3COOC3H6Si(OCH3)3,
HSC3H6Si(OCH3)3,NH2C3H6Si(OC2H5)3,
NH2C2H4NHC3H6Si(OCH3)3,
NH2CONHC3H6Si(OC2H5)3
などの構造式で示されるシランカツプリング剤を
用いることができる。カツプリング処理は、焼成
し外部電極を被着した積層セラミツクコンデンサ
をカツプリング剤(またはその溶液)中に浸漬
し、デシケーター内にて減圧下に行う。ついで該
セラミツクコンデンサを取り出し乾燥する。かか
る浸漬および乾燥は2〜3回行うのが好ましい。
このようにしてカツプリング剤にて処理したコ
ンデンサは、つぎに従来のものと同様Niまたは
Cuなどによる電解金属メツキ(約PH4.5)、さらに
は電解半田(またはSn,Pb)メツキ(<PH1〜
4.5)が行われれ、チツプ型コンデンサとするか、
あるいは更にリード線を付けて外装を施し外装型
コンデンサとする。
実施例
つぎに本発明を実施例により更に具体的に説明
する。
(i) チツプ型積層セラミツクコンデンサ
セラミツクシート:チタン酸バリウム
内部電極 Ag−Pd
外部電極 Agペースト
コンデンサ寸法 3.2×1.6mm
(ii) シランカツプリング剤:
(γ−グリシドキシプロピル
トリメトキシシラン)
上記の積層コンデンサ22個をカツプリング剤中
に浸漬して、減圧下30分間デシケータ内に置き、
ポーラス部分へのカツプリング剤の浸透をはかつ
た。浸漬後、コンデンサを引き上げ約150℃にて
乾燥した。
このコンデンサのうち17個を再度カツプリング
剤中に浸漬し、乾燥処理した。うち13個について
はさらに3回目の浸漬、乾燥処理を行つた。
これらのチツプコンデンサーの外部電極に、つ
ぎの条件でNiメツキ、ついで半田メツキを施し
た。
(Niメツキ)
電解液:NiSO4 220g/,NiCl2 45g/、
H3BO3 40g/,PH4〜4.5
電極:Ni板、電圧1V、電流3A
(半田メツキ)
メツキ液:ソルダロンSG(ジヤパンメタル(株)製)
PH4
電極:Pb−Sn板、電圧:1.5V、電流:0.6A
得られたチツプコンデンサのメツキ後の電気損
失(tanδ)を焼成工程後の値と比較して第1表お
よび第1図に示す。
比較例
カツプリング処理を行わなかつた以外は、実施
例と同様にして5個のチツプに金属メツキ行いチ
ツプコンデンサを得た。その物性を前記と同様に
第1表および第1図に示す。
INDUSTRIAL APPLICATION FIELD The present invention relates to a method for manufacturing chip-type and exterior-type multilayer ceramic capacitors. More specifically, the present invention relates to a method for manufacturing a highly reliable multilayer ceramic capacitor that does not allow penetration of plating solution during the process of metal plating external electrodes. BACKGROUND OF THE INVENTION In recent years, ceramic capacitors have come into widespread use as essential components for making electronic devices and circuits smaller, faster, and more reliable. FIG. 3 is a schematic perspective view of a multilayer ceramic capacitor before external electrodes are attached, and FIG. 4 is a schematic perspective view of the multilayer ceramic capacitor with external electrodes attached. In order to manufacture such a laminated ceramic capacitor 1, barium titanate ceramic powder is mixed with an organic solvent, a plasticizer, a binder, etc. to form a slurry, and then a long piece is formed using a doctor blade method or the like. A ceramic green sheet 2 is obtained. Next, this green sheet is cut into a predetermined size, and the internal electrodes 3 are formed on the cut sheet at a predetermined position by screen printing or the like. After that,
A plurality of these elements are laminated, green sheet films are laminated on top and bottom thereof as protective layers, and the elements are integrated under pressure to obtain a laminate. Next, this laminate is cut and separated into predetermined dimensions to obtain raw laminated ceramic capacitor chips. The raw chips are then fired at a temperature suitable for firing ceramic powder. Furthermore, as shown in FIG. 4, external connection electrodes 4 made of Ag or Ag-Pd are applied to the internal electrode lead-out portions at both ends of the obtained capacitor chip, thereby obtaining a multilayer ceramic capacitor. The multilayer ceramic capacitor manufactured in this way is arranged with the external electrodes facing each other on the conductor lands on the printed wiring board, and is soldered using either the solder dipping method, in which the external electrodes are immersed in molten solder, or the reflow soldering method, using cream solder. It is used and incorporated into electronic equipment. However, if the external electrode is attached to the board by direct soldering, the external electrode will be "soldered".
There is a problem in that the capacitor becomes thinner and the mounting strength of the capacitor becomes weaker. In order to prevent solder cracking of the external electrodes of multilayer ceramic capacitors, Ni or Cu plating is further applied to the external electrodes, which were conventionally formed using conductive Ag paste or Ag-Pd paste, as a barrier to prevent solder cracking. ,
Furthermore, solder plating (or Sn, Pb plating) is applied on top of this.
There are multilayer chip capacitors that improve solder flow. Problems to be Solved by the Invention However, when plating Ni, Cu, etc., in an acidic electrolytic plating solution with a pH of about 4.5,
In addition, to perform solder plating, it is necessary to immerse the multilayer chip capacitor in an acidic electrolytic plating solution with a pH of 1 to 4 or lower, which may cause the plating solution to seep into the multilayer capacitor, resulting in a decrease in capacitance, an increase in current loss, etc. This results in performance deterioration. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for easily obtaining a highly reliable capacitor by preventing quality deterioration in the conventional plating process of multilayer ceramic capacitors. Means for Solving the Problems The present invention is a method for manufacturing a multilayer ceramic capacitor, which includes a step of attaching an external electrode to a plate-shaped capacitor assembly in which a ceramic sheet and an internal electrode are laminated, and a step of attaching an external electrode to the external electrode. The present invention provides a method for manufacturing a multilayer ceramic capacitor, characterized in that a step of treating with a coupling agent is provided between the step of metal plating. In the present invention, the multilayer ceramic capacitor coated with external electrodes and fired may be manufactured by a conventional method. For example, ceramic green sheets and internal electrodes (Ag-Pd, Pb,
Ag or Ag for the external electrode
Dip or apply in alloy paste, 600~850℃
Baking is performed. Next, the multilayer ceramic capacitor thus obtained is treated with a coupling agent. As the coupling agent, any of various silane coupling agents can be used, such as ClC 3 H 6 Si(OCH 3 ) 3 , CH 2 =CHSiCl 3 , CH 2 =CHSi(OC 2 H 5 ) 3 , CH2 =CHSi( OCH3 ) 3 , CH2 =CHSi( OC2H4OCH3 ) 3 , CH2 = CCH3COOC3H6Si ( OCH3 ) 3 , HSC 3 H 6 Si (OCH 3 ) 3 , NH 2 C 3 H 6 Si (OC 2 H 5 ) 3 , NH 2 C 2 H 4 NHC 3 H 6 Si (OCH 3 ) 3 , NH 2 CONHC 3 H 6 Si A silane coupling agent represented by a structural formula such as (OC 2 H 5 ) 3 can be used. The coupling treatment is performed by immersing a fired laminated ceramic capacitor with external electrodes in a coupling agent (or its solution) under reduced pressure in a desiccator. The ceramic capacitor is then taken out and dried. It is preferable to carry out such dipping and drying two to three times. Capacitors treated with coupling agents in this way are then treated with Ni or
Electrolytic metal plating (approx. PH4.5) using Cu, etc., and electrolytic solder (or Sn, Pb) plating (<PH1~
4.5) is carried out, and a chip type capacitor is used, or
Alternatively, a lead wire can be attached to the capacitor to form an exterior capacitor. EXAMPLES Next, the present invention will be explained in more detail with reference to Examples. (i) Chip-type multilayer ceramic capacitor Ceramic sheet: Barium titanate Internal electrode Ag-Pd External electrode Ag paste Capacitor dimensions 3.2 x 1.6 mm (ii) Silane coupling agent: (γ-glycidoxypropyl trimethoxysilane) The above 22 multilayer capacitors were immersed in a coupling agent and placed in a desiccator under reduced pressure for 30 minutes.
The penetration of the coupling agent into the porous portion was facilitated. After immersion, the capacitor was pulled up and dried at approximately 150°C. Seventeen of these capacitors were again immersed in the coupling agent and dried. Thirteen of them underwent a third immersion and drying process. The external electrodes of these chip capacitors were plated with Ni and then soldered under the following conditions. (Ni plating) Electrolyte: NiSO 4 220g/, NiCl 2 45g/, H 3 BO 3 40g/, PH4~4.5 Electrode: Ni plate, voltage 1V, current 3A (Solder plating) Plating liquid: Solderon SG (Japan Metal) Co., Ltd.)
PH4 Electrode: Pb-Sn plate, voltage: 1.5V, current: 0.6A The electrical loss (tan δ) of the obtained chip capacitor after plating is compared with the value after the firing process and is shown in Table 1 and Figure 1. . Comparative Example Chip capacitors were obtained by metal plating five chips in the same manner as in the example except that the coupling treatment was not performed. Its physical properties are shown in Table 1 and FIG. 1 in the same manner as above.
【表】
第1表および第1図より明らかなごとく、カツ
プリング剤による処理を行つていないものではメ
ツキ処理後、著しくtanδ値の増大するものが存在
し電気損失が大きい。これに対してカツプリング
剤にて処理を行つたものは1回→3回と処理回数
の増加に伴いメツキ後もtanδ値の増大がなく3回
の処理では焼成後とメツキ後との間に殆ど差が認
められない。
さらに、第2図にカツプリング剤にて処理を行
つたコンデンサのたわみテストの結果を示した。
処理回数の増加にともない“たわみ量”が増大
し、ほぼすべての試験品が2〜3回の処理でたわ
みテスト(日本電子工業会規格RC−3402)の規
格2mmを満たした。
発明の効果
以上のごとく、本発明の製造方法によれば、カ
ツプリング剤による処理により、コンデンサ電流
損失の増大のない信頼性に優れた積層コンデンサ
が得られる。また本発明方法によれば、高いたわ
み特性を有する積層コンデンサが得られる。[Table] As is clear from Table 1 and Figure 1, some of the samples that were not treated with a coupling agent showed a marked increase in tan δ value after the plating treatment, resulting in large electrical losses. On the other hand, for those treated with a coupling agent, the tan δ value did not increase even after plating as the number of treatments increased from once to three times, and with three treatments, there was almost no increase in the tanδ value between after firing and after plating. No difference observed. Furthermore, FIG. 2 shows the results of a deflection test of a capacitor treated with a coupling agent.
As the number of treatments increased, the amount of deflection increased, and almost all test products satisfied the 2 mm deflection test (Japan Electronics Industry Association standard RC-3402) after 2 to 3 treatments. Effects of the Invention As described above, according to the manufacturing method of the present invention, a highly reliable multilayer capacitor without an increase in capacitor current loss can be obtained by treatment with a coupling agent. Furthermore, according to the method of the present invention, a multilayer capacitor having high deflection characteristics can be obtained.
第1図は各処理における金属メツキ前後のtanδ
値を示すグラフ、第2図はカツプリング処理回数
とたわみ量の関係を示すグラフ、第3図は外部電
極被着前のチツプコンデンサを示す概略斜視図、
第4図は外部電極を取り付けたチツプコンデンサ
を示す概略斜視図である。図中の符号はつぎのと
おりである。
1……セラミツクコンデンサ、2……セラミツ
クグリーンシート、3……内部電極、4……外部
電極。
Figure 1 shows tanδ before and after metal plating in each treatment.
Figure 2 is a graph showing the relationship between the number of coupling treatments and the amount of deflection; Figure 3 is a schematic perspective view showing the chip capacitor before external electrodes are attached;
FIG. 4 is a schematic perspective view showing a chip capacitor with external electrodes attached. The symbols in the figure are as follows. 1... Ceramic capacitor, 2... Ceramic green sheet, 3... Internal electrode, 4... External electrode.
Claims (1)
て、セラミツクシートと内部電極とが積層した板
状コンデンサ集合体に外部電極を被着する工程
と、該外部電極に金属メツキを行う工程との間に
カツプリング剤にて処理する工程を設けたことを
特徴とする積層セラミツクコンデンサの製造方
法。1. A method for manufacturing a multilayer ceramic capacitor, in which a coupling agent is used between the step of attaching an external electrode to a plate-shaped capacitor assembly in which ceramic sheets and internal electrodes are laminated, and the step of plating the external electrode with metal. 1. A method for manufacturing a multilayer ceramic capacitor, comprising a step of processing.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62219896A JPS6461904A (en) | 1987-09-01 | 1987-09-01 | Manufacture of laminated ceramic capacitor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62219896A JPS6461904A (en) | 1987-09-01 | 1987-09-01 | Manufacture of laminated ceramic capacitor |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6461904A JPS6461904A (en) | 1989-03-08 |
JPH0525372B2 true JPH0525372B2 (en) | 1993-04-12 |
Family
ID=16742735
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62219896A Granted JPS6461904A (en) | 1987-09-01 | 1987-09-01 | Manufacture of laminated ceramic capacitor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6461904A (en) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0656824B2 (en) * | 1991-01-25 | 1994-07-27 | 太陽誘電株式会社 | Chip-shaped electronic component and manufacturing method thereof |
JP4167360B2 (en) * | 1999-09-30 | 2008-10-15 | 京セラ株式会社 | Chip-type electronic components |
US6876537B2 (en) | 1999-10-07 | 2005-04-05 | Matsushita Electric Industrial Co., Ltd. | Ceramic electronic component and method for manufacturing the same |
JPWO2002082480A1 (en) | 2001-04-05 | 2004-07-29 | 松下電器産業株式会社 | Ceramic electronic component and its manufacturing method |
CN101346786B (en) | 2006-03-15 | 2011-07-27 | 株式会社村田制作所 | Laminated electronic component and method for manufacturing same |
JP6852326B2 (en) * | 2016-09-20 | 2021-03-31 | 株式会社村田製作所 | Multilayer ceramic electronic components |
JP6852327B2 (en) * | 2016-09-20 | 2021-03-31 | 株式会社村田製作所 | Multilayer ceramic electronic components |
JP7243487B2 (en) * | 2019-06-27 | 2023-03-22 | 株式会社村田製作所 | Manufacturing method of multilayer ceramic capacitor |
-
1987
- 1987-09-01 JP JP62219896A patent/JPS6461904A/en active Granted
Also Published As
Publication number | Publication date |
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JPS6461904A (en) | 1989-03-08 |
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