JP2830456B2 - Ceramic capacitors - Google Patents
Ceramic capacitorsInfo
- Publication number
- JP2830456B2 JP2830456B2 JP2300124A JP30012490A JP2830456B2 JP 2830456 B2 JP2830456 B2 JP 2830456B2 JP 2300124 A JP2300124 A JP 2300124A JP 30012490 A JP30012490 A JP 30012490A JP 2830456 B2 JP2830456 B2 JP 2830456B2
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- Japan
- Prior art keywords
- layer
- plating
- plating layer
- capacitor
- ceramic
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Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明は外部電極の焼付け電極層の表面に３層のめっ
き層が形成されたセラミックコンデンサに関するもので
ある。Description: TECHNICAL FIELD The present invention relates to a ceramic capacitor in which three plated layers are formed on the surface of a baked electrode layer of an external electrode.
［従来の技術］ セラミックコンデンサの外部電極として、セラミック
素体の外面にAg,Ag/Pd等の貴金属粉末にガラスフリット
を加えたペーストを塗布して焼付けた焼付け電極層を有
するものが知られている。[Prior Art] As an external electrode of a ceramic capacitor, a capacitor having a baked electrode layer obtained by applying a paste obtained by adding a glass frit to a noble metal powder such as Ag or Ag / Pd on the outer surface of a ceramic body and baking it is known. I have.
従来、この焼付け電極層を下地電極としてこの表面に
Ni,Cu,Sn及びSn/Pbのうち少なくとも１種で形成された
めっき層を有するセラミックコンデンサが提案されてい
る（特開平２−150007）。上記めっき層は電解又は無電
解めっき法により行われ、上記コンデンサはめっき層に
より焼付け電極層の耐熱性が高まってはんだによる電極
食われがなくなり、かつ金属成分の酸化防止とはんだ濡
れ性が向上してはんだ付けが容易になる特長がある。Conventionally, this baked electrode layer is used as a base electrode on this surface.
A ceramic capacitor having a plating layer formed of at least one of Ni, Cu, Sn and Sn / Pb has been proposed (Japanese Patent Laid-Open No. 150007/1990). The plating layer is formed by an electrolytic or electroless plating method.In the capacitor, the heat resistance of the baked electrode layer is increased by the plating layer so that the electrode is not eroded by solder, and the oxidation of metal components and the prevention of solder wettability are improved. This makes it easy to solder.
［発明が解決しようとする課題］ しかし、第３図に示す上記セラミックコンデンサのよ
うに、焼付け電極層２の表面にNiめっき層４とSn/Pbめ
っき層５の２つのめっき層をこの順に形成した場合に
は、Niめっき層４は降温時の引張り応力が高いため、コ
ンデンサを室温から予熱せずに300℃以上のはんだ槽に
浸漬し引上げると、外部電極１の内側のセラミック誘電
体６にクラック７が発生し易い。そしてクラックが発生
すると耐湿性が低下してクラックから水分が浸入しコン
デンサとしての絶縁抵抗が劣化する。[Problems to be Solved by the Invention] However, as in the ceramic capacitor shown in FIG. 3, two plating layers of a Ni plating layer 4 and a Sn / Pb plating layer 5 are formed in this order on the surface of the baked electrode layer 2. In this case, since the Ni plating layer 4 has a high tensile stress at the time of temperature drop, if the capacitor is immersed in a solder bath of 300 ° C. or more without preheating from room temperature and pulled up, the ceramic dielectric 6 inside the external electrode 1 is pulled up. Crack 7 is likely to occur. When a crack occurs, moisture resistance decreases, moisture enters from the crack, and insulation resistance as a capacitor deteriorates.
また第４図に示すようにこのコンデンサをチップコン
デンサとして、基板８の表面にはんだ付け９により実装
し、例えば−25℃から室温を経由して＋85℃まで昇温
し、反対に降温させる温度サイクル試験を行った場合に
は、高い熱応力からクラック７が成長して外部電極１の
部分が折損するか、或いはコンデンサの絶縁抵抗が劣化
するようになる。Further, as shown in FIG. 4, this capacitor is mounted as a chip capacitor on the surface of a substrate 8 by soldering 9 and, for example, a temperature cycle in which the temperature is raised from -25.degree. C. to + 85.degree. When a test is performed, the crack 7 grows due to high thermal stress, and the portion of the external electrode 1 breaks, or the insulation resistance of the capacitor deteriorates.
また、焼付け電極層の表面にCuめっき層とSn又はSn/P
bめっき層の２つのめっき層をこの順に形成した場合に
は、Niめっき層を形成したことによる上記問題点は解消
される反面、CuはNiより耐熱性に劣るため、焼付け電極
層の耐熱性を十分に向上できずはんだによる電極食われ
が生じる欠点がある。In addition, a Cu plating layer and Sn or Sn / P
When the two plating layers of the b plating layer are formed in this order, the above problem caused by the formation of the Ni plating layer is solved, but the heat resistance of the baked electrode layer is lower because Cu has lower heat resistance than Ni. Is not sufficiently improved, and the electrode is eroded by solder.
本発明の目的は、電解めっき法により外部電極を表面
被覆したときの特性劣化がないセラミックコンデンサを
提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a ceramic capacitor having no characteristic deterioration when an external electrode is surface-coated by an electrolytic plating method.
［課題を解決するための手段］ 本発明者らは、焼付け電極層の表面にめっき層を２層
設けた従来のコンデンサの問題点をめっき層を特定の厚
みの特定の３種の金属によって３層構造にすることによ
り解決し、本発明に到達した。[Means for Solving the Problems] The present inventors have solved the problem of the conventional capacitor in which two plating layers are provided on the surface of the baked electrode layer. The plating layer is formed of three specific metals having a specific thickness. The problem was solved by forming a layer structure, and the present invention was reached.
上記目的を達成するために、第１図に示すように本発
明は、セラミック素体10と、この素体外面に形成され貴
金属とガラスフリットとを含む焼付け電極層12を有する
外部電極11とを備え、焼付け電極層12の表面にNi,Cu,Sn
及びSn/Pbのうち少なくとも１種で形成されためっき層
を有するセラミックコンデンサにおいて、焼付け電極層
12の表面にCuめっき層13とNiめっき層14とSn又はSn/Pb
めっき層15がこの順に形成され、Cuめっき層13の厚みが
３〜30μｍの範囲にあり、Niめっき層14の厚みが１〜５
μｍの範囲にあり、Sn又はSn/Pbめっき層15の厚みが３
〜30μｍの範囲にあることを特徴とする。In order to achieve the above object, as shown in FIG. 1, the present invention comprises a ceramic body 10 and an external electrode 11 having a baked electrode layer 12 formed on the outer surface of the body and containing a noble metal and glass frit. Ni, Cu, Sn on the surface of the baked electrode layer 12
And a sintered electrode layer in a ceramic capacitor having a plating layer formed of at least one of Sn and Pb.
12 on the surface of Cu plating layer 13 and Ni plating layer 14 and Sn or Sn / Pb
The plating layer 15 is formed in this order, the thickness of the Cu plating layer 13 is in the range of 3 to 30 μm, and the thickness of the Ni plating layer 14 is 1 to 5 μm.
μm, and the thickness of the Sn or Sn / Pb plating layer 15 is 3
3030 μm.
本発明のセラミックコンデンサは、積層コンデンサの
みならず単層コンデンサをも含む。積層コンデンサは、
内部電極として電極材料を印刷したセラミック誘電体を
積層した後、これを焼成してセラミック素体を形成し、
このセラミック素体の外面に内部電極に導通する外部電
極を形成して作製される。このセラミック誘導体には、
鉛系、チタン酸バリウム系の誘電体が用いられ、内部電
極にはPd,Pt,Ag/Pd等の貴金属、或いはNi,Fe,Co等の卑
金属が用いられる。The ceramic capacitor of the present invention includes not only a multilayer capacitor but also a single-layer capacitor. Multilayer capacitors are
After laminating a ceramic dielectric printed with an electrode material as an internal electrode, it is fired to form a ceramic body,
It is manufactured by forming an external electrode which is connected to an internal electrode on the outer surface of the ceramic body. This ceramic derivative includes:
A lead-based or barium titanate-based dielectric is used, and a noble metal such as Pd, Pt, Ag / Pd or a base metal such as Ni, Fe, Co is used for the internal electrode.
また外部電極としては、Ag,Ag/Pd等の貴金属粉末にガ
ラスフリットを加えたペーストをセラミック素体の外面
に塗布して焼付けた焼付け電極層を備え、この電極層の
表面にめっき層が形成される。The external electrode is equipped with a baked electrode layer obtained by applying a paste obtained by adding a glass frit to a noble metal powder such as Ag, Ag / Pd, etc. to the outer surface of the ceramic body and baking it.A plating layer is formed on the surface of this electrode layer Is done.
本発明のめっき層は３層構造からなり、焼付け電極層
の上には厚みが３〜30μｍのCuめっき層が形成され、こ
のCuめっき層の上には厚みが１〜５μｍのNiめっき層が
形成され、更にNiめっき層の上には厚みが３〜30μｍの
Sn又はSn/Pbめっき層が形成される。The plating layer of the present invention has a three-layer structure, a Cu plating layer having a thickness of 3 to 30 μm is formed on the baked electrode layer, and a Ni plating layer having a thickness of 1 to 5 μm is formed on the Cu plating layer. Formed, and a thickness of 3 to 30 μm on the Ni plating layer.
A Sn or Sn / Pb plating layer is formed.
Cu層を内層にしてNi層を中間層にし、Sn又はSn/Pb層
を外層にし、各めっき層の厚みを上記範囲にするのは、
熱応力の大きいNi層をセラミック誘導体から極力遠ざけ
てセラミック誘導体の熱衝撃を緩和する一方、はんだに
溶解しやすい焼付け電極層をCu層を介してCuより耐熱性
のあるNiでより確実に保護し、かつSn又はSn/Pb層で外
部電極のはんだ濡れ性を高め、同時にCu及びNiの酸化を
防止するためである。The Cu layer is an inner layer, the Ni layer is an intermediate layer, the Sn or Sn / Pb layer is an outer layer, and the thickness of each plating layer is in the above range.
Keep the Ni layer with large thermal stress away from the ceramic derivative as much as possible to alleviate the thermal shock of the ceramic derivative, while protecting the baked electrode layer that is easy to dissolve in solder with Ni, which is more heat-resistant than Cu, via the Cu layer. The reason is that the Sn or Sn / Pb layer enhances the solder wettability of the external electrode and, at the same time, prevents oxidation of Cu and Ni.
これらのめっき層は、無電解及び電解めっき等をバレ
ルめっきで行うことにより形成される。めっき浴はCu,N
i,Sn又はSn/Pbともそれぞれ公知のものを使用する。These plating layers are formed by performing electroless plating, electrolytic plating, and the like by barrel plating. Plating bath is Cu, N
Known ones are used for i, Sn and Sn / Pb.
［作 用］ このように構成したセラミックコンデンサは、コンデ
ンサを室温から予熱せずに300℃以上のはんだ槽に浸漬
し引上げる急激な熱衝撃を与えてもCuめっき層がNiめっ
き層の熱応力を緩和するため、外部電極の熱歪によるセ
ラミック誘電体内のクラックの発生が阻止される。また
はんだ付け時にはNiめっき層が焼付け電極層の電極食わ
れを防止し、Sn又はSn/Pbめっき層が外部電極のはんだ
濡れ性を高めてCu及びNiの酸化を防止する。[Operation] In the ceramic capacitor configured in this way, the Cu plating layer is not subjected to thermal stress of the Ni plating layer even if the capacitor is immersed in a solder bath of 300 ° C or more and pulled up without preheating from room temperature and subjected to a sudden thermal shock. Therefore, generation of cracks in the ceramic dielectric due to thermal distortion of the external electrode is prevented. Further, at the time of soldering, the Ni plating layer prevents electrode erosion of the baked electrode layer, and the Sn or Sn / Pb plating layer enhances the solder wettability of the external electrode to prevent oxidation of Cu and Ni.
［発明の効果］ 以上述べたように、本発明によれば、焼付け電極層の
表面にCuめっき層とNiめっき層とSn又はSn/Pbめっき層
をそれぞれ所定の層厚にしてこの順で形成することによ
り、はんだ耐熱性を具備しつつ、コンデンサが熱衝撃を
受けても誘電体内にクラックを生じず、結果として各種
特性に優れたセラミックコンデンサが得られる。[Effects of the Invention] As described above, according to the present invention, a Cu plating layer, a Ni plating layer, and a Sn or Sn / Pb plating layer are formed on a surface of a baked electrode layer in a predetermined layer thickness and in this order. By doing so, cracks do not occur in the dielectric even when the capacitor is subjected to thermal shock while having solder heat resistance, and as a result, a ceramic capacitor excellent in various characteristics can be obtained.
［実施例］ 次に本発明の実施例を図面に基づいて比較例とともに
詳しく説明する。[Example] Next, an example of the present invention will be described in detail with a comparative example based on the drawings.
＜実施例１＞ 第１図に示すように、この例ではセラミックコンデン
サ20は積層セラミックチップコンデンサであって、セラ
ミック素体10と、このセラミック素体10の側面に形成さ
れた外部電極11とを備える。セラミック素体10は鉛プロ
ブスカイト系であって、貴金属であるPbにより内部電極
19が形成されたセラミック誘電体16を複数枚積層し、こ
れを焼成することにより形成した。<Example 1> As shown in Fig. 1, in this example, a ceramic capacitor 20 is a multilayer ceramic chip capacitor, in which a ceramic body 10 and external electrodes 11 formed on side surfaces of the ceramic body 10 are formed. Prepare. The ceramic body 10 is a lead-provskite-based material, and the internal electrode
A plurality of ceramic dielectrics 16 on which 19 were formed were laminated and fired.
外部電極11としては、焼付け電極層12と、これをめっ
き下地電極とする３層のめっき層13,14及び15を有す
る。焼付け電極層12は耐めっき液性を有するガラスフリ
ットを含んだAgペーストをセラミック素体10の外面に塗
布し、180℃で15分間乾燥した後、最高温度750℃で焼付
けて形成した。The external electrode 11 includes a baked electrode layer 12 and three plating layers 13, 14, and 15 using the baked electrode layer 12 as a base electrode for plating. The baking electrode layer 12 was formed by applying an Ag paste containing glass frit having plating solution resistance to the outer surface of the ceramic body 10, drying at 180 ° C. for 15 minutes, and baking at a maximum temperature of 750 ° C.
３層のめっき層13〜15は次のめっき条件で形成した。 The three plating layers 13 to 15 were formed under the following plating conditions.
Cuめっき（内層） 浴組成 硫酸銅（CuSO4・5H2O 200 g/ 硫酸（H2SO4） 60 g/ pH 4.0 温度 30 ℃ 上記組成の浴を用い、電解バレルめっき法で電極層12
の表面に10〜15μｍ厚のめっき層13を形成した。Using Cu plating (inner layer) bath composition Copper sulfate (CuSO 4 · 5H 2 O 200 g / sulfuric acid (H 2 SO 4) 60 g / pH 4.0 Temperature 30 ° C. bath having the above composition, the electrode layer 12 by electrolytic barrel plating
A plating layer 13 having a thickness of 10 to 15 μm was formed on the surface of the substrate.
Niめっき（中間層） 浴組成 スルファミン酸ニッケルNi（NH2SO3）２・4H2O120 g/ pH 4.0 温度 50 ℃ 上記組成の浴を用い、電解バレルめっき法でCuめっき
層13の表面に１〜３μｍ厚のめっき層14を形成した。Ni plating (intermediate layer) Bath composition Nickel sulfamate Ni (NH 2 SO 3 ) 2・ 4H 2 O 120 g / pH 4.0 Temperature 50 ℃ Using a bath with the above composition, electrolytic barrel plating method was used to deposit 1 on the surface of the Cu plating layer 13. A plating layer 14 having a thickness of about 3 μm was formed.
Sn/Pbめっき（外層） 浴組成 錫（Sn） 15 g/ 鉛（Pb） 6 g/ pH 4.5 温度 25 ℃ 上記組成の浴を用い、電解バレルめっき法でNiめっき
層14の表面に10〜15μｍ厚のめっき層15を形成した。Sn / Pb plating (outer layer) Bath composition Tin (Sn) 15 g / Lead (Pb) 6 g / pH 4.5 Temperature 25 ° C Using a bath with the above composition, the surface of the Ni plating layer 14 is 10 to 15 μm thick by electrolytic barrel plating. A thick plating layer 15 was formed.
＜比較例１＞ のNiめっき（中間層）を行わない以外は実施例１と
同様にして焼付け電極層の表面にCu層とSn/Pb層からな
る２層構造のめっき層を形成した。Comparative Example 1 A plating layer having a two-layer structure composed of a Cu layer and a Sn / Pb layer was formed on the surface of the baked electrode layer in the same manner as in Example 1 except that Ni plating (intermediate layer) was not performed.
＜比較例２＞ のCuめっき（内層）を行わない以外は実施例１と同
様にして焼付け電極層の表面にNi層とSn/Pb層からなる
２層構造のめっき層を形成した。<Comparative Example 2> A plating layer having a two-layer structure including a Ni layer and a Sn / Pb layer was formed on the surface of the baked electrode layer in the same manner as in Example 1 except that the Cu plating (inner layer) was not performed.
上記実施例１、比較例１及び比較例２で作製した積層
セラミックチップコンデンサに対して、熱衝撃試験、温
度サイクル試験及びはんだ耐熱試験を行った。A thermal shock test, a temperature cycle test, and a solder heat resistance test were performed on the multilayer ceramic chip capacitors manufactured in Example 1 and Comparative Examples 1 and 2.
（ａ）熱衝撃試験 第２図に示すように室温におかれた試料となるチップ
コンデンサ20を１個ずつピンセット21でコンデンサの幅
の狭い上下面となるようにつかみ、これを予熱をせずに
350℃のSn60/Pb40共晶はんだ槽に１秒間浸漬した後、引
上げる。この試料を濃硝酸中で20分間煮沸し、外部電極
を溶解させる。(A) Thermal shock test As shown in FIG. 2, a chip capacitor 20 to be a sample at room temperature is gripped one by one with tweezers 21 so that the upper and lower surfaces of the capacitor are narrow, and this is not preheated. To
After being immersed in a Sn60 / Pb40 eutectic solder bath at 350 ° C for 1 second, it is pulled up. The sample is boiled in concentrated nitric acid for 20 minutes to dissolve the external electrode.
実施例１、比較例１及び比較例２のコンデンサをそれ
ぞれ100個ずつ試験し、外部電極跡のセラミック素体に
クラックが発生しているか否か調べ、クラックが発生し
た試料数を数えた。その結果を第１表に示す。Each of the capacitors of Example 1, Comparative Example 1 and Comparative Example 2 was tested for 100 pieces, and it was checked whether or not cracks had occurred in the ceramic body at the trace of the external electrode, and the number of samples in which cracks had occurred was counted. Table 1 shows the results.
（ｂ）温度サイクル試験 厚さ0.635mmのアルミナ基板に試料となるチップコン
デンサを350℃のはんだに浸漬してはんだ付けし、−25
℃で30分間維持しそこから昇温して室温で３分間維持
し、更に昇温して＋85℃で30分間維持した跡、維持時間
を同一にして反対に降温させるサイクルを100サイクル
行う。(B) Temperature cycle test A chip capacitor to be a sample is immersed in a 350 ° C solder and soldered to a 0.635 mm thick alumina substrate.
The temperature was maintained at 30 ° C. for 30 minutes, then the temperature was raised and maintained at room temperature for 3 minutes, and the temperature was raised and maintained at + 85 ° C. for 30 minutes.
実施例１、比較例１及び比較例２それぞれ30個ずつ試
験を行い、コンデンサとしての容量低下、tanδの劣
化、絶縁抵抗の劣化、及びクラック発生数を調べた。こ
の結果を第１表に示す。Example 1, Comparative Example 1 and Comparative Example 2 were each tested for 30 pieces, and the reduction in capacity as a capacitor, the deterioration in tan δ, the deterioration in insulation resistance, and the number of cracks were examined. Table 1 shows the results.
第１表より、実施例１のコンデンサはCuめっき層を有
するためNiめっき層の熱応力を緩和し、比較例１のコン
デンサはNiめっき層を有しないため、それぞれセラミッ
ク誘電体にクラックを全く生じさせず、かつコンデンサ
としての高特性を具備し品質安定性に優れていることが
判った。 From Table 1, it can be seen that the capacitor of Example 1 has a Cu plating layer and thus alleviates the thermal stress of the Ni plating layer, and the capacitor of Comparative Example 1 does not have a Ni plating layer, so that each of the ceramic dielectrics has cracks at all. It was found that the capacitor was not used, and that it had high characteristics as a capacitor and was excellent in quality stability.
（ｃ）はんだ耐熱試験 前記熱衝撃試験で用いたはんだ槽に試料を80秒間浸漬
した後、外観検査を行って焼付け電極層の残存率を調べ
た。(C) Solder heat resistance test The sample was immersed in the solder bath used for the thermal shock test for 80 seconds, and then the appearance was examined to determine the residual ratio of the baked electrode layer.
実施例１、比較例１及び比較例２それぞれ20個ずつ試
験を行い、残存率の平均値をとったところ、実施例１が
95％、比較例２が90％で高かったのに対して、比較例１
は40％で低い値を示し、Niめっき層がはんだ耐熱性に寄
与することが判明した。Example 1, Comparative Example 1 and Comparative Example 2 were each tested for 20 pieces, and the average value of the residual rates was obtained.
Comparative Example 1 was higher than 95% and Comparative Example 2 was 90%.
Shows a low value of 40%, which indicates that the Ni plating layer contributes to the solder heat resistance.
第１図は本発明実施例セラミックコンデンサの断面図。 第２図はその熱衝撃試験を行うときの試料の取扱い状況
を示す斜視図。 第３図は従来例セラミックコンデンサの熱衝撃に起因し
たクラック発生状況を示す断面図。 第４図は第３図のコンデンサを基板にはんだ付けして更
にクラックが成長した状況を示す断面図。 10:セラミック素体、 11:外部電極、 12:焼付け電極層、 13:Cuめっき層、 14:Niめっき層、 15:Sn/Pbめっき層、 16:セラミック誘電体、 19:内部電極、 20:セラミックコンデンサ。FIG. 1 is a sectional view of a ceramic capacitor according to an embodiment of the present invention. FIG. 2 is a perspective view showing how a sample is handled when the thermal shock test is performed. FIG. 3 is a cross-sectional view showing a state of occurrence of cracks due to thermal shock of a conventional ceramic capacitor. FIG. 4 is a cross-sectional view showing a situation in which cracks have grown by soldering the capacitor of FIG. 3 to a substrate. 10: ceramic body, 11: external electrode, 12: baked electrode layer, 13: Cu plating layer, 14: Ni plating layer, 15: Sn / Pb plating layer, 16: ceramic dielectric, 19: internal electrode, 20: Ceramic capacitors.
フロントページの続き (72)発明者 斉藤 征士 埼玉県秩父郡横瀬町大字横瀬2270番地 三菱鉱業セメント株式会社セラミックス 研究所内 (56)参考文献 特開 平２−248020（ＪＰ，Ａ) 特開 平２−150010（ＪＰ，Ａ) (58)調査した分野(Int.Cl.6，ＤＢ名) H01G 4/12 H01G 4/232Continuation of the front page (72) Inventor Seiji Saito 2270 Yokoze, Yokoze-machi, Chichibu-gun, Saitama Prefecture Mitsubishi Ceramics Co., Ltd. Ceramics Research Laboratory (56) References JP-A-2-248020 (JP, A) JP-A-2- 150010 (JP, A) (58) Field surveyed (Int. Cl. 6 , DB name) H01G 4/12 H01G 4/232
Claims (1)
形成され貴金属とガラスフリットとを含む焼付け電極層
（12）を有する外部電極（11）とを備え、前記焼付け電
極層（12）の表面にNi,Cu,Sn及びSn/Pbのうち少なくと
も１種で形成されためっき層を有するセラミックコンデ
ンサにおいて、 前記焼付け電極層（12）の表面にCuめっき層（13）とNi
めっき層（14）とSn又はSn/Pbめっき層（15）がこの順
に形成され、前記Cuめっき層（13）の厚みが３〜30μｍ
の範囲にあり、前記Niめっき層（14）の厚みが１〜５μ
ｍの範囲にあり、前記Sn又はSn/Pbめっき層（15）の厚
みが３〜30μｍの範囲にあることを特徴とするセラミッ
クコンデンサ。1. A ceramic body (10) and an external electrode (11) having a burned electrode layer (12) formed on the outer surface of the body and containing a noble metal and a glass frit. ), A ceramic capacitor having a plating layer formed of at least one of Ni, Cu, Sn and Sn / Pb on the surface of the baked electrode layer (12).
A plating layer (14) and a Sn or Sn / Pb plating layer (15) are formed in this order, and the thickness of the Cu plating layer (13) is 3 to 30 μm.
And the thickness of the Ni plating layer (14) is 1 to 5 μm.
m, and the thickness of the Sn or Sn / Pb plating layer (15) is in the range of 3 to 30 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2300124A JP2830456B2 (en) | 1990-11-06 | 1990-11-06 | Ceramic capacitors |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2300124A JP2830456B2 (en) | 1990-11-06 | 1990-11-06 | Ceramic capacitors |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04171912A JPH04171912A (en) | 1992-06-19 |
| JP2830456B2 true JP2830456B2 (en) | 1998-12-02 |
Family
ID=17881016
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2300124A Expired - Lifetime JP2830456B2 (en) | 1990-11-06 | 1990-11-06 | Ceramic capacitors |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2830456B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003183844A (en) * | 2001-12-18 | 2003-07-03 | Murata Mfg Co Ltd | Electronic component and manufacturing process therefor |
Families Citing this family (12)
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|---|---|---|---|---|
| JP4859270B2 (en) * | 2000-12-27 | 2012-01-25 | イビデン株式会社 | Capacitor, multilayer printed wiring board, and method for manufacturing multilayer printed wiring board |
| KR100465845B1 (en) * | 2002-07-12 | 2005-01-13 | 삼화콘덴서공업주식회사 | Multi layered ceramic capacitor and composition of the electrode |
| JP2006245049A (en) * | 2005-02-28 | 2006-09-14 | Tdk Corp | Electronic component and electronic apparatus |
| JP3918851B2 (en) | 2005-06-03 | 2007-05-23 | 株式会社村田製作所 | Multilayer electronic component and method of manufacturing multilayer electronic component |
| JP2009283986A (en) * | 2009-09-03 | 2009-12-03 | Taiyo Yuden Co Ltd | Electronic component with externally connected electrode, and circuit module |
| KR102121579B1 (en) * | 2018-10-02 | 2020-06-10 | 삼성전기주식회사 | Multi-layered ceramic electronic component |
| JP2022136816A (en) | 2021-03-08 | 2022-09-21 | Tdk株式会社 | Ceramic electronic component |
| JP2022136821A (en) | 2021-03-08 | 2022-09-21 | Tdk株式会社 | Ceramic electronic component |
| JP2022136766A (en) | 2021-03-08 | 2022-09-21 | Tdk株式会社 | Ceramic electronic component |
| JP2022136771A (en) | 2021-03-08 | 2022-09-21 | Tdk株式会社 | Ceramic electronic component |
| JP2022136819A (en) | 2021-03-08 | 2022-09-21 | Tdk株式会社 | Ceramic electronic component |
| JP2023013238A (en) | 2021-07-15 | 2023-01-26 | Tdk株式会社 | Ceramic electronic component |
-
1990
- 1990-11-06 JP JP2300124A patent/JP2830456B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003183844A (en) * | 2001-12-18 | 2003-07-03 | Murata Mfg Co Ltd | Electronic component and manufacturing process therefor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04171912A (en) | 1992-06-19 |
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