JPH04329616A - Laminated type electronic component - Google Patents
Laminated type electronic componentInfo
- Publication number
- JPH04329616A JPH04329616A JP3128575A JP12857591A JPH04329616A JP H04329616 A JPH04329616 A JP H04329616A JP 3128575 A JP3128575 A JP 3128575A JP 12857591 A JP12857591 A JP 12857591A JP H04329616 A JPH04329616 A JP H04329616A
- Authority
- JP
- Japan
- Prior art keywords
- external electrode
- plating
- solder
- silver
- electronic component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims abstract description 13
- 239000011347 resin Substances 0.000 claims abstract description 10
- 229920005989 resin Polymers 0.000 claims abstract description 10
- 239000000919 ceramic Substances 0.000 claims abstract description 9
- 229910052709 silver Inorganic materials 0.000 claims abstract description 9
- 239000004332 silver Substances 0.000 claims abstract description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 16
- 229910052759 nickel Inorganic materials 0.000 claims description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 3
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 229920001187 thermosetting polymer Polymers 0.000 claims description 2
- 229910052725 zinc Inorganic materials 0.000 claims description 2
- 239000011701 zinc Substances 0.000 claims description 2
- 229910052751 metal Inorganic materials 0.000 claims 2
- 239000002184 metal Substances 0.000 claims 2
- 239000000843 powder Substances 0.000 claims 2
- 229910000978 Pb alloy Inorganic materials 0.000 claims 1
- 229910001128 Sn alloy Inorganic materials 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 abstract description 24
- 238000007747 plating Methods 0.000 abstract description 21
- 238000000034 method Methods 0.000 abstract description 17
- 239000000853 adhesive Substances 0.000 abstract description 5
- 230000001070 adhesive effect Effects 0.000 abstract description 5
- 239000011521 glass Substances 0.000 abstract description 3
- 239000007788 liquid Substances 0.000 abstract description 3
- 238000007598 dipping method Methods 0.000 abstract description 2
- SWELZOZIOHGSPA-UHFFFAOYSA-N palladium silver Chemical compound [Pd].[Ag] SWELZOZIOHGSPA-UHFFFAOYSA-N 0.000 abstract description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract description 2
- WUOACPNHFRMFPN-UHFFFAOYSA-N alpha-terpineol Chemical compound CC1=CCC(C(C)(C)O)CC1 WUOACPNHFRMFPN-UHFFFAOYSA-N 0.000 abstract 1
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- SQIFACVGCPWBQZ-UHFFFAOYSA-N delta-terpineol Natural products CC(C)(O)C1CCC(=C)CC1 SQIFACVGCPWBQZ-UHFFFAOYSA-N 0.000 abstract 1
- 238000001035 drying Methods 0.000 abstract 1
- 229940116411 terpineol Drugs 0.000 abstract 1
- 239000003990 capacitor Substances 0.000 description 6
- 239000003985 ceramic capacitor Substances 0.000 description 6
- 238000005476 soldering Methods 0.000 description 5
- 238000009713 electroplating Methods 0.000 description 4
- 230000007774 longterm Effects 0.000 description 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000000149 penetrating effect Effects 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 238000010304 firing Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 239000001856 Ethyl cellulose Substances 0.000 description 1
- ZZSNKZQZMQGXPY-UHFFFAOYSA-N Ethyl cellulose Chemical compound CCOCC1OC(OC)C(OCC)C(OCC)C1OC1C(O)C(O)C(OC)C(CO)O1 ZZSNKZQZMQGXPY-UHFFFAOYSA-N 0.000 description 1
- 239000006071 cream Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000003618 dip coating Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229920001249 ethyl cellulose Polymers 0.000 description 1
- 235000019325 ethyl cellulose Nutrition 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 239000012466 permeate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/228—Terminals
- H01G4/232—Terminals electrically connecting two or more layers of a stacked or rolled capacitor
- H01G4/2325—Terminals electrically connecting two or more layers of a stacked or rolled capacitor characterised by the material of the terminals
Abstract
Description
【0001】0001
【産業上の利用分野】本発明は、積層形電子部品の外部
電極構造に関わり、特に基板に面実装されるチップ形積
層コンデンサや積層バリスタなどの電子部品の実装信頼
性の向上に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the external electrode structure of multilayer electronic components, and particularly to improving the mounting reliability of electronic components such as chip-type multilayer capacitors and multilayer varistors that are surface-mounted on a substrate.
【0002】0002
【従来の技術】積層形電子部品、例えば積層セラミック
コンデンサは、基板に直接面実装でき、しかも、短時間
にかつ、容易にはんだ付け実装が可能なことから大量に
使用されている。2. Description of the Related Art Multilayer electronic components, such as multilayer ceramic capacitors, are used in large quantities because they can be directly surface-mounted on a substrate and can be easily soldered and mounted in a short time.
【0003】これらは、図2に示すように、セラミック
素体2内部に埋め込まれた内部電極1層を有し、その引
出端子部に銀、又は銀とパラジウムの粉末とガラスフリ
ット及び樹脂ビヒクルからなるペ−ストを塗布し、通常
600℃以上の高温で焼成することにより外部電極3を
形成して製造される。このようなチップ形電子部品をプ
リント配線基板にはんだ付け実装するには、まず基板の
パタ−ン部にクリ−ムはんだを印刷塗布し、その上にチ
ップ部品の外部電極3部分を置き、加熱炉ではんだの溶
融温度まで加熱することにより、外部電極3部分と基板
のパタ−ン部がはんだ付けにより接合される。この方法
をリフロ−はんだ付けというが、更に量産性が高く、短
時間にしかも基板の両面に実装できる方法として基板に
チップ部品を接着材で接着し、溶融した噴流はんだの中
に浸漬させることにより外部電極3と基板のパタ−ン部
をはんだ付けするフロ−実装法がある。しかし、前記の
外部電極3構造では、溶融はんだに直接外部電極3が接
触するため、外部電極3中の銀がはんだ中に拡散し、外
部電極3の一部が消失する、いわゆる、はんだくわれ現
象によりフロ−実装ができない。フロ−実装するには、
前記外部電極3の表面にニッケル6及びスズと鉛からな
るはんだ5を順次電気めっき法で形成する外部電極構造
としなければならない。しかしながら、電気めっきの工
程において、めっき液が外部電極3を通して浸透し、通
常では問題の起こらないセラミック素体2の軽微な空隙
部に浸透する結果、損失係数などの電気的性能を低下さ
せたり、長期信頼性を損なうなどの欠点があった。これ
は、従来技術では前記製造法による外部電極の微細構造
を液体の浸透しない緻密構造にできないためである。As shown in FIG. 2, these have one layer of internal electrodes embedded inside the ceramic body 2, and the lead terminals are made of silver or silver and palladium powder, glass frit, and a resin vehicle. The external electrodes 3 are manufactured by applying a paste and firing at a high temperature, usually 600° C. or higher. To solder and mount such a chip-shaped electronic component on a printed wiring board, first print and coat cream solder on the pattern part of the board, place the three external electrodes of the chip component on top of it, and heat it. By heating to the melting temperature of the solder in a furnace, the external electrode 3 portion and the pattern portion of the substrate are joined by soldering. This method is called reflow soldering, but as a method that is more suitable for mass production and can be mounted on both sides of the board in a short time, it is possible to bond the chip components to the board with an adhesive and immerse them in a jet of molten solder. There is a flow mounting method in which the external electrode 3 and the pattern portion of the board are soldered. However, in the above-mentioned structure of the external electrode 3, since the external electrode 3 comes into direct contact with the molten solder, the silver in the external electrode 3 diffuses into the solder and a part of the external electrode 3 disappears, which is called a solder trap. Due to this phenomenon, flow implementation is not possible. To implement the flow,
The external electrode structure must be such that nickel 6 and solder 5 made of tin and lead are sequentially formed on the surface of the external electrode 3 by electroplating. However, in the electroplating process, the plating solution permeates through the external electrode 3 and into the slight voids in the ceramic body 2 that normally do not cause problems, resulting in a decrease in electrical performance such as loss coefficient, etc. There were drawbacks such as loss of long-term reliability. This is because in the conventional technology, the fine structure of the external electrode cannot be made into a dense structure that does not allow liquid to penetrate by the above manufacturing method.
【0004】以上の理由により、従来は比較的空隙部が
できやすい大形のチップコンデンサ(大略4mm角以上
)などの電子部品は、通常ニッケル及びはんだめっきを
行わず、したがって基板実装はリフロ−法に限定される
という欠点があった。また小形の電子部品は、フロ−用
としてニッケル及びはんだめっきを行っているが、前記
の理由から高信頼性を要求される部品については、めっ
きを行わず、したがってフロ−法ができないというもの
があった。For the above reasons, electronic components such as large chip capacitors (approximately 4 mm square or larger), which are relatively prone to forming voids, are usually not plated with nickel or solder, and therefore are mounted on boards using the reflow method. The disadvantage was that it was limited to. In addition, small electronic parts are plated with nickel and solder for flow use, but for the reasons mentioned above, parts that require high reliability are not plated and therefore cannot be used with the flow method. there were.
【0005】[0005]
【発明が解決しようとする課題】前記したように、従来
技術では、チップ形積層セラミックコンデンサなどの電
子部品をフロ−法で基板にはんだ付けするために、ニッ
ケルめっき及びはんだめっきを行うと、めっき工程にお
いて外部電極部分を通してめっき液が部品内部、特に内
部電極層とセラミック層との間隙に浸透し、電気的性能
を低下させたり、長期の信頼性を低下させるという欠点
があった。[Problems to be Solved by the Invention] As mentioned above, in the prior art, when nickel plating and solder plating are performed in order to solder electronic components such as chip-type multilayer ceramic capacitors to a board by the flow method, the plating During the process, the plating solution penetrates into the inside of the component through the external electrode portion, particularly into the gap between the internal electrode layer and the ceramic layer, resulting in a disadvantage in that the electrical performance and long-term reliability are degraded.
【0006】本発明は、上記従来技術の問題点を解決す
るため、めっきを行う前の下地となる外部電極層の構造
を改善することによって、めっき工程におけるめっき液
の浸透を防止し、電気的性能や、長期信頼性を低下させ
ずにめっきを行うことができ、したがって、工業的に有
利なフロ−はんだ付け法によって基板実装できる積層セ
ラミックコンデンサや積層バリスタなどの積層電子部品
を提供することを目的としたものである。[0006] In order to solve the problems of the prior art described above, the present invention improves the structure of the external electrode layer that serves as the base before plating, thereby preventing penetration of the plating solution during the plating process and improving electrical conductivity. Our objective is to provide multilayer electronic components such as multilayer ceramic capacitors and multilayer varistors that can be plated without deteriorating performance or long-term reliability, and therefore can be mounted on boards using the industrially advantageous flow soldering method. This is the purpose.
【0007】[0007]
【課題を解決するための手段】本発明は、内部電極層と
その端部に形成された銀または銀とパラジウムからなる
外部電極と、この外部電極を被覆するようにして形成さ
れた導電性樹脂と、この導電性樹脂の表面に電気めっき
によって形成されたスズ及び鉛からなるはんだ膜を備え
たことを特徴とする積層形電子部品であり、上記導電性
樹脂が熱硬化性樹脂を基材とし、銀、ニッケル、アルミ
ニウム、亜鉛のうちの少なくとも1種の粉末を含み、体
積抵抗率が1×10−3Ωcm以下であるものである。[Means for Solving the Problems] The present invention provides an internal electrode layer, an external electrode made of silver or silver and palladium formed at the end of the internal electrode layer, and a conductive resin formed to cover the external electrode. and a laminated electronic component comprising a solder film made of tin and lead formed by electroplating on the surface of the conductive resin, the conductive resin having a thermosetting resin as a base material. , silver, nickel, aluminum, and zinc, and has a volume resistivity of 1×10 −3 Ωcm or less.
【0008】[0008]
【作用】本発明の構成による積層形電子部品では、最後
のめっき工程の前に水を浸透させない導電性樹脂によっ
て、銀又は銀パラジウムからなる外部電極が被覆されて
いるため、めっき工程でめっき液が内部電極の端面露出
部に浸透することを防止でき、したがって従来技術の問
題点であっためっき液が内部電極層とセラミック層の隙
間から浸透することによって起こる電気的性能の低下及
び長期信頼性の低下を完全に防止することができる。[Function] In the laminated electronic component constructed according to the present invention, the external electrodes made of silver or silver palladium are coated with a conductive resin that does not allow water to penetrate before the final plating process. This prevents the plating solution from penetrating into the exposed end surface of the internal electrode, thus reducing the electrical performance and long-term reliability caused by the plating solution penetrating through the gap between the internal electrode layer and the ceramic layer. can be completely prevented from decreasing.
【0009】[0009]
【実施例】積層セラミックコンデンサを例として述べる
。図1に示すように、公知の製造方法にしたがって、内
部電極1層が50層の長さ5.5mm、幅5.0mm、
厚さ2.0mmの直方体のセラミック素体2を高温焼成
後、内部電極1の端面が露出している直方体の端面に銀
粉末80部、ガラスフリット10部、エチルセルロ−ズ
樹脂5部、タ−ピネオ−ル5部からなるペ−ストを浸漬
法により塗布し、乾燥後800℃の電気炉で焼成し、外
部電極3層を形成した。次に市販の銀粉末80部を含む
エポキシ系導電接着材を前記外部電極3層を被覆するよ
うに浸漬塗布し、200℃ 30分の加熱により硬化
させ導電層4を形成した。なお、この材料の硬化後の体
積抵抗率は、1×10−4Ωcmであった。次に公知の
めっき技術によって、スズ90%、鉛10%からなるは
んだめっき液を用いて電気めっき法によって厚さ5μm
のはんだ膜5を形成した。[Embodiment] A multilayer ceramic capacitor will be described as an example. As shown in FIG. 1, according to a known manufacturing method, one layer of internal electrodes has 50 layers, a length of 5.5 mm, a width of 5.0 mm,
After firing a rectangular ceramic body 2 with a thickness of 2.0 mm at a high temperature, 80 parts of silver powder, 10 parts of glass frit, 5 parts of ethyl cellulose resin, and tar are applied to the end face of the rectangular parallelepiped where the end face of the internal electrode 1 is exposed. A paste consisting of 5 parts of Pineol was applied by dipping, dried and fired in an electric furnace at 800°C to form three layers of external electrodes. Next, a commercially available epoxy conductive adhesive containing 80 parts of silver powder was applied by dip coating to cover the three external electrode layers, and was cured by heating at 200° C. for 30 minutes to form a conductive layer 4. The volume resistivity of this material after curing was 1×10 −4 Ωcm. Next, using a known plating technique, electroplating was performed to a thickness of 5 μm using a solder plating solution consisting of 90% tin and 10% lead.
A solder film 5 was formed.
【0010】以上の方法によって作製したコンデンサを
実施例とし、比較のため、この実施例と同条件で電極層
まで形成した試料に、公知の技術にしたがってニッケル
めっき層及びスズ90%、鉛10%のはんだ層をそれぞ
れ5μmの厚さで順次電気めっきした。[0010] A capacitor manufactured by the above method is used as an example, and for comparison, a sample formed up to the electrode layer under the same conditions as this example was coated with a nickel plating layer and a nickel plating layer of 90% tin and 10% lead according to a known technique. solder layers were sequentially electroplated, each with a thickness of 5 μm.
【0011】上記実施例と従来例の方法でそれぞれ10
00個の試料を作製し、これらの試料について静電容量
、誘電正接、絶縁抵抗、耐電圧をJIS C 64
23で規定された規格で全数検査した結果を表1に示す
。[0011] Each of the methods of the above embodiment and the conventional example
00 samples were prepared, and the capacitance, dielectric loss tangent, insulation resistance, and withstand voltage of these samples were determined according to JIS C 64.
Table 1 shows the results of 100% inspection according to the standards specified in 23.
【0012】0012
【表1】
この表1から明らかなように、実施例の電気的特性の不
良率は、従来例よりも明らかに少ないが、この理由は導
電接着材からなる導電層4によってめっき液がセラミッ
ク素体2中に浸透することを防止した結果である。[Table 1] As is clear from Table 1, the defect rate of the electrical characteristics of the example is clearly lower than that of the conventional example. This is the result of preventing it from penetrating into the body 2.
【0013】次に、上記検査後の実施例及び従来例の試
料から各100個をサンプリングし、125℃の温度で
100Vの直流電圧を2000時間印加する高温負荷試
験を行った結果、実施例では故障が見られなかったのに
対し、従来例からは3%の絶縁抵抗故障(10MΩ以下
)があり、明らかに実施例のほうが信頼性が高いことが
わかった。この理由も、前記と同じ理由によるものであ
る。[0013] Next, after the above inspection, 100 samples each were sampled from the samples of the example and the conventional example, and a high temperature load test was conducted in which a DC voltage of 100V was applied for 2000 hours at a temperature of 125°C. While no failure was observed in the conventional example, there was a 3% insulation resistance failure (10 MΩ or less), indicating that the example was clearly more reliable. The reason for this is also the same as above.
【0014】更に、実施例による試料を270℃の溶融
はんだに10秒間浸漬し、外部電極3表面を観察したと
ころ、はんだくわれ現象は見られず、外部電極3全面が
新しいはんだで覆われていたことから、フロ−はんだ付
け法による基板実装が可能であることを確認した。Furthermore, when the sample according to the example was immersed in molten solder at 270° C. for 10 seconds and the surface of the external electrode 3 was observed, no solder curling phenomenon was observed, indicating that the entire surface of the external electrode 3 was covered with new solder. Therefore, we confirmed that board mounting using flow soldering is possible.
【0015】なお、硬化後の体積抵抗率が異なる種々の
導電接着材を用い、前記実施例と同じ方法でコンデンサ
を試作し、電気的特性を測定した結果、導電接着材の硬
化後の体積抵抗率が1×10−3Ωcmを越えるものを
用いた場合は、コンデンサの誘電正接がJIS C
6423で規定された誘電正接値を満足しないという
結果が得られた。この結果より本発明で用いる導電接着
材の体積抵抗率は、1×10−3Ωcm以下でなければ
ならないことがわかった。[0015] As a result of prototyping capacitors using various conductive adhesives having different volume resistivities after curing in the same manner as in the above example and measuring their electrical characteristics, it was found that If a capacitor with a coefficient exceeding 1 x 10-3 Ωcm is used, the dielectric loss tangent of the capacitor shall be JIS C
The result was that the dielectric loss tangent value specified in 6423 was not satisfied. From this result, it was found that the volume resistivity of the conductive adhesive used in the present invention must be 1×10 −3 Ωcm or less.
【0016】[0016]
【発明の効果】以上述べたように、本発明になる積層形
電子部品は、目的とするめっきを行なっても電気的特性
、及び信頼性の低下が見られず、高いはんだ耐熱性を有
し、溶融はんだによるフロ−はんだ付け法を用いること
ができるので、工業的に非常に価値の高い積層形電子部
品を提供できるものである。[Effects of the Invention] As described above, the laminated electronic component of the present invention shows no deterioration in electrical characteristics and reliability even after the intended plating, and has high solder heat resistance. Since it is possible to use a flow soldering method using molten solder, it is possible to provide a laminated electronic component of great industrial value.
【図1】本発明の一実施例である積層セラミックコンデ
ンサを示す正断面図である。FIG. 1 is a front cross-sectional view showing a multilayer ceramic capacitor that is an embodiment of the present invention.
【図2】従来の積層セラミックコンデンサを示す正断面
図である。FIG. 2 is a front cross-sectional view showing a conventional multilayer ceramic capacitor.
1 内部電極 2 セラミック素体 3 外部電極 4 導電層 5 はんだ膜 1 Internal electrode 2 Ceramic body 3 External electrode 4 Conductive layer 5 Solder film
Claims (2)
少なくとも2層以上の内部電極層と、この内部電極層の
端部が交互に露出するセラミック素体の端面に形成され
た外部電極と、この外部電極を被覆して形成された金属
粉末と樹脂からなる導電層と、この導電層の表面にスズ
及び鉛合金からなるはんだ付け可能な金属膜を備えたこ
とを特徴とする積層形電子部品。1. At least two or more internal electrode layers embedded inside a ceramic body, external electrodes formed on the end faces of the ceramic body from which the ends of the internal electrode layers are alternately exposed, and A laminated electronic component comprising: a conductive layer made of metal powder and resin formed to cover an external electrode; and a solderable metal film made of tin and lead alloy on the surface of the conductive layer.
材に銀、ニッケル、アルミニウム、亜鉛のうちの少なく
とも1種の粉末を含み、硬化後の体積比抵抗が1×10
−3Ωcm以下である請求項1記載の積層形電子部品。2. The conductive layer contains powder of at least one of silver, nickel, aluminum, and zinc in a base material made of a thermosetting resin, and has a volume resistivity of 1×10 after curing.
2. The laminated electronic component according to claim 1, which has a resistance of -3 Ωcm or less.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3128575A JPH04329616A (en) | 1991-04-30 | 1991-04-30 | Laminated type electronic component |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3128575A JPH04329616A (en) | 1991-04-30 | 1991-04-30 | Laminated type electronic component |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04329616A true JPH04329616A (en) | 1992-11-18 |
Family
ID=14988148
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3128575A Pending JPH04329616A (en) | 1991-04-30 | 1991-04-30 | Laminated type electronic component |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04329616A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05226180A (en) * | 1992-02-12 | 1993-09-03 | Hitachi Aic Inc | Laminated ceramic capacitor |
JPH11219849A (en) * | 1998-01-30 | 1999-08-10 | Kyocera Corp | Laminated ceramic capacitor |
JP2000243662A (en) * | 1999-02-19 | 2000-09-08 | Tdk Corp | Electronic device and manufacture thereof |
KR20140027116A (en) * | 2011-02-23 | 2014-03-06 | 나믹스 가부시끼가이샤 | Conductive composition and external electrode using same |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH036005A (en) * | 1989-06-02 | 1991-01-11 | Tdk Corp | Low-temperature constitution of chip-component terminal |
JPH0350708A (en) * | 1989-07-18 | 1991-03-05 | Matsushita Electric Ind Co Ltd | Chip capacitor |
-
1991
- 1991-04-30 JP JP3128575A patent/JPH04329616A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH036005A (en) * | 1989-06-02 | 1991-01-11 | Tdk Corp | Low-temperature constitution of chip-component terminal |
JPH0350708A (en) * | 1989-07-18 | 1991-03-05 | Matsushita Electric Ind Co Ltd | Chip capacitor |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05226180A (en) * | 1992-02-12 | 1993-09-03 | Hitachi Aic Inc | Laminated ceramic capacitor |
JPH0793229B2 (en) * | 1992-02-12 | 1995-10-09 | 日立エーアイシー株式会社 | Monolithic ceramic capacitors |
JPH11219849A (en) * | 1998-01-30 | 1999-08-10 | Kyocera Corp | Laminated ceramic capacitor |
JP2000243662A (en) * | 1999-02-19 | 2000-09-08 | Tdk Corp | Electronic device and manufacture thereof |
JP4501143B2 (en) * | 1999-02-19 | 2010-07-14 | Tdk株式会社 | Electronic device and manufacturing method thereof |
KR20140027116A (en) * | 2011-02-23 | 2014-03-06 | 나믹스 가부시끼가이샤 | Conductive composition and external electrode using same |
JPWO2012114925A1 (en) * | 2011-02-23 | 2014-07-07 | ナミックス株式会社 | Conductive composition and external electrode using the same |
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