JP2000299243A - Laminated chip type electronic component - Google Patents

Laminated chip type electronic component

Info

Publication number
JP2000299243A
JP2000299243A JP11108846A JP10884699A JP2000299243A JP 2000299243 A JP2000299243 A JP 2000299243A JP 11108846 A JP11108846 A JP 11108846A JP 10884699 A JP10884699 A JP 10884699A JP 2000299243 A JP2000299243 A JP 2000299243A
Authority
JP
Japan
Prior art keywords
electrodes
electrode
nickel
electronic component
electrically connected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11108846A
Other languages
Japanese (ja)
Inventor
Takashi Aiba
尚 相庭
Toshiaki Ochiai
利明 落合
Tetsuji Maruno
哲司 丸野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Corp
Original Assignee
TDK Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TDK Corp filed Critical TDK Corp
Priority to JP11108846A priority Critical patent/JP2000299243A/en
Publication of JP2000299243A publication Critical patent/JP2000299243A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To prevent the oxidation of external electrodes and obtain satisfactory electrical conduction by forming main electrode layers electrically connected to internal electrodes of a sintered metal consisting essentially of copper or nickel and arranging the external electrodes whose outer surfaces are covered with plated layers made of a noble metal which is hard to oxidize. SOLUTION: A laminated chip capacitor is fabricated by forming a green sheet from a dielectric material containing barium titanate, and forming an internal electrode 10 of a base metal such as nickel. Using a capacitor chip element assembly 11, which is formed by sintering a plurality of internal electrodes 10 and ceramic sheets alternately laminated one upon another as a substrate, the assembly 11 is provided at both ends thereof with external electrodes 12 electrically connected to the electrodes 10. The electrodes 12 have main electrode layers 12a formed of a sintered metal which is obtained by coating conductive paste, which consists mainly of copper or nickel, to both ends of the assembly 11 and sintering the conductive paste. The layers 12a are electrically connected to the electrodes 10. The outer surface of each electrode 12 is covered with an electroplated layer 12c made of a noble metal such as silver or gold which is hard to be oxidized.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は積層チップ型電子部
品の改良に係り、詳しくは導電性の樹脂材料により回路
パターンのランド部と電気的に導通接合するのに好適な
外部電極の改良に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a multilayer chip type electronic component, and more particularly to an improvement of an external electrode suitable for electrically conductively joining a land portion of a circuit pattern with a conductive resin material. It is.

【0002】[0002]

【従来の技術】積層チップ型電子部品、例えば積層チッ
プコンデンサは、図2で示すようにニッケル等の内部電
極1をセラミックシートと交互に複数積層させて焼成
し、誘電体の積層体でなるコンデンサチップ素体2を形
成し、その内部電極1と電気的に導通する外部電極3を
コンデンサチップ素体2の両端部に設けることにより構
成されている。
2. Description of the Related Art As shown in FIG. 2, a multilayer chip type electronic component, for example, a multilayer chip capacitor, is formed by alternately laminating a plurality of internal electrodes 1 made of nickel or the like with a ceramic sheet and firing the resultant. The chip body 2 is formed, and external electrodes 3 electrically connected to the internal electrodes 1 are provided at both ends of the capacitor chip body 2.

【0003】従来、その積層チップコンデンサの外部電
極3は、銅(Cu)またはニッケル(Ni)を主成分とする
燒結金属で内部電極1と電気的に導通する主電極層3a
を形成すると共に、主電極層3aの半田喰れを防ぐニッ
ケル(Ni)のメッキ層3bで主電極層3aを覆い、更
に、外表面を半田付け性の良好な錫(Sn)またはその合
金(Sn−Pb)のメッキ層3cで覆うことにより形成さ
れている。
Conventionally, the external electrode 3 of the multilayer chip capacitor is made of a sintered metal mainly composed of copper (Cu) or nickel (Ni) and is a main electrode layer 3a electrically connected to the internal electrode 1.
Is formed, the main electrode layer 3a is covered with a nickel (Ni) plating layer 3b for preventing solder erosion of the main electrode layer 3a, and further, the outer surface of the main electrode layer 3a is formed of tin (Sn) or an alloy thereof having good solderability. It is formed by covering with a plating layer 3c of Sn-Pb).

【0004】その積層チップコンデンサは、外部電極3
を回路基板4の板面上に設けた回路パターンのランド部
5に半田6で接合固定することにより回路基板4の板面
に搭載されるが、半田6としては環境等の問題から鉛
(Pb)の含まない銀(Ag)を主成分とした導電性の樹脂
ペーストが用いられる傾向にある。
The multilayer chip capacitor has external electrodes 3
Is mounted on the board surface of the circuit board 4 by bonding and fixing it to the land portion 5 of the circuit pattern provided on the board surface of the circuit board 4 with solder 6.
There is a tendency to use a conductive resin paste containing silver (Ag) as a main component that does not contain (Pb).

【0005】その導電性の樹脂ペーストを接合固定用と
すると、外部電極を回路パターンのランド部と電気的に
確実に導通固定するべく加熱処理で硬化させる場合があ
る。然し、外部電極の最外層が錫(Sn)またはその合金
(Sn−Pb)のメッキ層であると、導電性の樹脂ペース
トによる接合面が加熱処理に伴って酸化することにより
電気的導通不良を生ずる虞れがある。
If the conductive resin paste is used for bonding and fixing, the external electrode may be cured by a heat treatment so that the external electrodes are electrically and securely fixed to the lands of the circuit pattern. However, the outermost layer of the external electrode is tin (Sn) or its alloy.
In the case of a plating layer of (Sn-Pb), there is a possibility that electrical connection failure may occur due to oxidation of a bonding surface made of a conductive resin paste with heat treatment.

【0006】この錫(Sn)またはその合金(Sn−Pb)
のメッキ層による最外層は通常の環境下でも表面の酸化
が経時的に進んで劣化する傾向にあり、特に、湿度の影
響が大きくて外部電極の表面酸化による導通不良が発生
し易い。
This tin (Sn) or its alloy (Sn-Pb)
The surface of the outermost layer formed by the plating layer tends to deteriorate with the passage of time even under a normal environment. In particular, the influence of humidity is large and conduction failure due to surface oxidation of the external electrode is likely to occur.

【0007】[0007]

【発明が解決しようとする課題】本発明は、上述した課
題に鑑み、導電性の樹脂スペーストによる接合固定に要
する加熱処理並びに環境条件による経時劣化や湿度の影
響における外部電極の酸化を防ぎ、回路パターンのラン
ド部と良好な電気的導通が得られる積層チップ型電子部
品を提供することを主たる目的とする。
SUMMARY OF THE INVENTION In view of the above-mentioned problems, the present invention prevents the heat treatment required for bonding and fixing with a conductive resin space and the aging of external electrodes due to environmental conditions and the oxidation of external electrodes due to the influence of humidity. It is a main object of the present invention to provide a multilayer chip electronic component capable of obtaining good electrical conduction with a land portion of a circuit pattern.

【0008】また、本発明は内部電極の形成材料からコ
ストダウンを図ると共に、その内部電極と良好な電気的
導通が得られ、且つ、回路パターンのランド部とも良好
な電気的導通が得られる積層チップ型電子部品を提供す
ることを別の目的とする。
[0008] The present invention also provides a laminate in which the cost can be reduced from the material for forming the internal electrodes, good electrical continuity with the internal electrodes can be obtained, and good electrical continuity can be obtained with the land portions of the circuit pattern. Another object is to provide a chip-type electronic component.

【0009】[0009]

【課題を解決するための手段】本発明の請求項1に記載
の積層チップ型電子部品においては、銅またはニッケル
を主成分とする燒結金属で内部電極と電気的に導通する
主電極層を形成すると共に、外表面を酸化し難い貴金属
のメッキ層で覆った外部電極を設けることにより構成さ
れている。
According to a first aspect of the present invention, there is provided a multilayer chip type electronic component, wherein a main electrode layer electrically connected to an internal electrode is formed of a sintered metal containing copper or nickel as a main component. In addition, an external electrode whose outer surface is covered with a noble metal plating layer that is hardly oxidized is provided.

【0010】本発明の請求項2に記載の積層チップ型電
子部品においては、銅またはニッケルを主成分とする燒
結金属で内部電極と電気的に導通する主電極層を形成す
ると共に、その主電極層の表面を酸化し難い貴金属のメ
ッキ層で覆った外部電極を設けることにより構成されて
いる。
According to a second aspect of the present invention, there is provided a laminated chip type electronic component, wherein a main electrode layer electrically connected to an internal electrode is formed of a sintered metal containing copper or nickel as a main component, and the main electrode is formed. It is constituted by providing an external electrode whose surface is covered with a plating layer of a noble metal which is hardly oxidized.

【0011】本発明の請求項3に記載の積層チップ型電
子部品においては、外表面を酸化し難い銀,金,パラジ
ウム,白金またはそれらの合金である貴金属のメッキ層
で覆った外部電極を設けることにより構成されている。
According to a third aspect of the present invention, there is provided a multilayer chip-type electronic component having an external electrode whose outer surface is covered with a plating layer of a noble metal which is hardly oxidized, such as silver, gold, palladium, platinum or an alloy thereof. It is constituted by.

【0012】本発明の請求項4に記載の積層チップ型電
子部品においては、卑金属の内部電極を設けることによ
り構成されている。
The multilayer chip electronic component according to a fourth aspect of the present invention is configured by providing a base metal internal electrode.

【0013】[0013]

【発明の実施の形態】図1の実施形態は、積層チップ電
子部品として積層チップコンデンサを構成する場合を示
す。この積層チップコンデンサは、チタン酸バリウムを
含む誘電体材料からセラミックグリーンシートを形成
し、それにニッケル等の卑金属から内部電極10を印刷
形成し、この内部電極10をセラミックシートと交互に
複数枚積層させて焼成形成したコンデンサチップ素体1
1を基体とし、両端部には内部電極10と電気的に導通
する外部電極12を設けることにより構成されている。
FIG. 1 shows an embodiment in which a multilayer chip capacitor is formed as a multilayer chip electronic component. In this multilayer chip capacitor, a ceramic green sheet is formed from a dielectric material containing barium titanate, and internal electrodes 10 are formed by printing on a base metal such as nickel, and a plurality of the internal electrodes 10 are alternately laminated with the ceramic sheet. Capacitor body 1 formed by firing
1 is used as a base, and external electrodes 12 electrically connected to the internal electrodes 10 are provided at both ends.

【0014】その外部電極12は、銅(Cu)またはニッ
ケル(Ni)を主成分とする導電性ペーストをコンデンサ
素体11の両端部に塗布し、これを焼付け処理した燒結
金属により内部電極10と電気的に導通する主電極層1
2aを形成すると共に、主電極層12aの半田喰れを防
ぐニッケルの電気メッキ層12bで主電極層12aを覆
い、更に、外表面を酸化し難い銀(Ag),金(Au),パ
ラジウム(Pd),白金(Pt)またはそれらの合金である
貴金属の電気メッキ層12cで覆うことにより形成され
ている。
The external electrodes 12 are formed by applying a conductive paste containing copper (Cu) or nickel (Ni) as a main component to both ends of the capacitor body 11 and sintering the conductive paste to the internal electrodes 10 with a sintered metal. Main electrode layer 1 electrically conducting
2a, the main electrode layer 12a is covered with a nickel electroplating layer 12b for preventing solder erosion of the main electrode layer 12a, and furthermore, silver (Ag), gold (Au), palladium ( It is formed by covering with an electroplating layer 12c of noble metal, which is Pd), platinum (Pt) or an alloy thereof.

【0015】その外部電極12は、ニッケルの電気メッ
キ層12bを省き、銅(Cu)またはニッケル(Ni)を主
成分とする導電性ペーストをコンデンサ素体11の両端
部に塗布し、これを焼付け処理した燒結金属により内部
電極10と電気的に導通する主電極層12aを形成する
と共に、その外表面を酸化し難い銀(Ag),金(Au),
パラジウム(Pd),白金(Pt)またはこれらの合金であ
る貴金属の電気メッキ層12cで覆うことによっても形
成できる。
For the external electrodes 12, the nickel electroplating layer 12b is omitted, and a conductive paste containing copper (Cu) or nickel (Ni) as a main component is applied to both ends of the capacitor body 11, and this is baked. A main electrode layer 12a electrically connected to the internal electrode 10 is formed by the treated sintered metal, and its outer surface is hardly oxidized, such as silver (Ag), gold (Au),
It can also be formed by covering with a precious metal electroplating layer 12c which is palladium (Pd), platinum (Pt) or an alloy thereof.

【0016】このように構成する積層チップコンデンサ
では、内部電極10をニッケル等の卑金属で形成するこ
とからコストダウンを図れる。また、内部電極10を卑
金属で形成しても、銅(Cu)またはニッケル(Ni)を主
成分とする燒結金属により内部電極10と電気的に導通
する主電極層12aを形成するため、外部電極12の主
電極層12aと内部電極10と良好な電気的導通が取れ
る。
In the multilayer chip capacitor configured as described above, since the internal electrodes 10 are formed of a base metal such as nickel, the cost can be reduced. Further, even if the internal electrode 10 is formed of a base metal, the main electrode layer 12a electrically connected to the internal electrode 10 is formed by a sintered metal containing copper (Cu) or nickel (Ni) as a main component. Twelve main electrode layers 12a and the internal electrodes 10 can have good electrical continuity.

【0017】また、外部電極12は外表面を酸化し難い銀
(Ag),金(Au),パラジウム(Pd),白金(Pt)また
はこれらの合金である貴金属の電気メッキ層12cで覆
うため、導電性の樹脂ペーストを半田13として外部電
極12を回路パターンのランド部14に接合固定するこ
とにより回路基板15に搭載しても、導電性の樹脂ペー
ストによる接合固定に要する加熱処理並びに環境条件に
よる経時劣化や湿度の影響における外部電極の酸化を防
げて回路パターンのランド部14と良好な電気的導通が
得られる。
The external electrode 12 is made of silver whose outer surface is hardly oxidized.
(Ag), gold (Au), palladium (Pd), platinum (Pt) or a precious metal electroplating layer 12c of these alloys. Even when mounted on the circuit board 15 by bonding and fixing to the land portion 14, the heat treatment required for bonding and fixing with the conductive resin paste and the deterioration of the external electrode due to the aging due to environmental conditions and the influence of humidity can be prevented, and the circuit pattern can be prevented. And good electrical continuity with the land portion 14 can be obtained.

【0018】その有効性を確認するべく、内部電極をニ
ッケルで形成したコンデンサチップ素体を基体とし、次
の表1で示すように銅またはニッケルを主成分とする導
電性ペーストを塗布,焼き付けした主電極層を形成し、
ニッケルによる第2のメッキ層を設けたもの(実施例1
〜4)と、第2層のメッキ層を設けないもの(実施例5〜
8)とにより、外表面を銀,金,パラジウム,白金のい
ずれかのメッキ層で覆った積層チップセラミックコンデ
ンサを作製した。
In order to confirm its effectiveness, a capacitor chip having an internal electrode made of nickel was used as a base, and a conductive paste containing copper or nickel as a main component was applied and baked as shown in Table 1 below. Forming a main electrode layer,
One provided with a second plating layer made of nickel (Example 1
To 4) and those without the second plating layer (Examples 5 to 5).
8), a multilayer chip ceramic capacitor whose outer surface was covered with any one of silver, gold, palladium and platinum plating layers was produced.

【0019】その各実施例と特性を比較するべく、内部
電極をニッケルで形成したコンデンサチップ素体を基体
とし、銅を主成分とした導電性ペーストを焼き付けて主
電極層を形成し、この主電極層をニッケルのメッキ層で
覆い、更に、外表面を錫のメッキ層で覆って外部電極を
設けた積層チップセラミックコンデンサ(従来例)を作製
した。その他に、銅のみによる外部電極を設けた積層チ
ップセラミックコンデンサ(比較例)も作製した。この積
層チップセラミックコンデンサは、いずれも2.0×
1.2×0.6mmの大きさで矩形形状のものに形成し
た。
In order to compare the characteristics with those of the respective embodiments, a main electrode layer was formed by baking a conductive paste containing copper as a main component with a capacitor chip body having an internal electrode formed of nickel as a base. A multilayer chip ceramic capacitor (conventional example) in which the electrode layer was covered with a nickel plating layer and the outer surface was further covered with a tin plating layer to provide external electrodes was produced. In addition, a multilayer chip ceramic capacitor (comparative example) provided with external electrodes made only of copper was also manufactured. Each of these multilayer chip ceramic capacitors is 2.0 ×
It was formed in a rectangular shape having a size of 1.2 × 0.6 mm.

【0020】[0020]

【表1】 [Table 1]

【0021】その積層チップコンデンサを各試料1〜1
0とし、アルミナ基板を回路基板として夫々5個ずつ回
路パターンのランド部と導電性樹脂により接着し、次の
試験条件で各導通抵抗の変化を測定した。また、各導通
抵抗は図1のポイントで接続した測定回路により外部電
極と導電性樹脂の接合部分とにおいて抵抗値を測定し
た。
The multilayer chip capacitor was connected to each of samples 1 to 1
The value was set to 0, and each of the alumina substrates was used as a circuit board, and five lands were adhered to the lands of the circuit pattern with a conductive resin, and the change in each conduction resistance was measured under the following test conditions. The resistance value of each conductive resistance was measured at the external electrode and the junction of the conductive resin by a measuring circuit connected at the points in FIG.

【0022】第1の耐湿性での導通抵抗は、85℃,8
5%RH:100時間で測定した。第2のPCTでの導
通抵抗は、121℃,95%RH2パスカル:100時
間で測定した。第3の熱衝撃での導通抵抗は、−55℃
〜125℃(常温なし,各30分/サイクル):100
サイクルで測定した。この結果は、次の表2で示す通り
であった。なお、表中、Kは×1000を示す。
The conduction resistance at the first moisture resistance is 85 ° C., 8
5% RH: measured at 100 hours. The conduction resistance in the second PCT was measured at 121 ° C. and 95% RH2 Pascal: 100 hours. The conduction resistance at the third thermal shock is −55 ° C.
125125 ° C. (no normal temperature, 30 minutes / cycle each): 100
Measured in cycles. The results were as shown in Table 2 below. In the table, K indicates x1000.

【0023】[0023]

【表2】 [Table 2]

【0024】この表2から判るように、試料No9,1
0のものは耐湿試験,PCT,熱衝撃試験のいずれにお
いても大幅に導通抵抗が増加し、試料No1〜8に比べ
て30倍〜30000倍の抵抗値の上昇が見られた。そ
の導通抵抗の増加は本来の回路特性を確保できないとこ
ろから、電子回路としては品質の悪いものとなる。これ
に対し、試料No1〜8のものはいずれの試験において
も殆ど導通抵抗の変化は見られなかった。
As can be seen from Table 2, Sample Nos. 9 and 1
In the case of No. 0, the conduction resistance was greatly increased in any of the humidity resistance test, the PCT, and the thermal shock test, and the resistance value was increased 30 to 30,000 times as compared with Sample Nos. 1 to 8. Since the increase in the conduction resistance cannot secure the original circuit characteristics, the quality of the electronic circuit becomes poor. On the other hand, the samples Nos. 1 to 8 showed almost no change in conduction resistance in any of the tests.

【0025】上述した実施例では外表面を銀,金,パラ
ジウム,白金のいずれかのメッキ層で覆って外部電極を
形成したものを示したが、外表面を銀,金,パラジウ
ム,白金の合金によるメッキ層で覆った外部電極でも同
様な電気的特性が得られる。また、内部電極は従来例と
同様に、ニッケル等の卑金属で形成しても、外表面を
銀,金,パラジウム,白金またはこれらの合金のメッキ
層で覆って外部電極を形成すれば、導電性の接着樹脂に
よる良好な電気的導通乃至は接合が得られる。
In the above-described embodiment, the outer electrode is formed by covering the outer surface with a plating layer of any one of silver, gold, palladium and platinum. However, the outer surface is formed of an alloy of silver, gold, palladium and platinum. The same electrical characteristics can be obtained even with an external electrode covered with a plating layer formed by the above method. Even if the internal electrode is formed of a base metal such as nickel, as in the conventional example, if the external electrode is formed by covering the outer surface with a plating layer of silver, gold, palladium, platinum or an alloy thereof, the conductive property can be improved. Good electrical continuity or bonding by the adhesive resin is obtained.

【0026】なお、上述した外部電極の構成は積層チッ
プコンデンサの他に、積層チップインダクタ,LC複合
チップ電子部品,共振器等の外部電極としても有効な効
果が得られる。
The above-described configuration of the external electrodes can provide an effective effect not only as a multilayer chip capacitor but also as an external electrode of a multilayer chip inductor, an LC composite chip electronic component, a resonator, and the like.

【0027】[0027]

【発明の効果】以上の如く、本発明の請求項1〜3に係
るいずれの積層チップ型電子部品に依れば、外表面を酸
化し難い貴金属のメッキ層で覆った外部電極を設けるこ
とにより、導電性の樹脂スペーストによる接合固定に要
する加熱処理並びに環境条件による経時劣化や湿度の影
響における外部電極の酸化が防げ、回路パターンのラン
ド部と良好な電気的導通が得られてQ値等の電気特性の
劣化を防止することができる。
As described above, according to any one of the laminated chip electronic components according to the first to third aspects of the present invention, by providing the external electrode whose outer surface is covered with a noble metal plating layer which is hardly oxidized. The heat treatment required for bonding and fixing with a conductive resin space and the aging of the external electrodes due to environmental conditions and the effect of humidity can be prevented, and good electrical continuity with the land of the circuit pattern can be obtained. Can be prevented from being deteriorated.

【0028】本発明の請求項4に係る積層チップ型電子
部品に依れば、内部電極を卑金属材料から形成すること
によりコストダウンを図ると共に、銅またはニッケルを
主成分とする燒結金属で内部電極と電気的に導通する主
電極層を形成すると共に、外表面を半田付け性の良好な
貴金属のメッキ層で覆った外部電極を設けることによ
り、内部電極と良好な電気的導通が得られ、且つ、回路
パターンのランド部とも良好な電気的導通が得られる。
According to the multilayer chip type electronic component of the present invention, the cost is reduced by forming the internal electrode from a base metal material, and the internal electrode is formed of a sintered metal mainly composed of copper or nickel. By forming a main electrode layer electrically conducting with the external electrode and providing an external electrode whose outer surface is covered with a plating layer of a noble metal having good solderability, good electrical conduction with the internal electrode is obtained, and Also, good electrical continuity can be obtained with the land portions of the circuit pattern.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係る積層チップ型電子部品の構成並び
に導通抵抗の測定ポイントを示す説明図である。
FIG. 1 is an explanatory diagram showing a configuration of a multilayer chip electronic component according to the present invention and measurement points of conduction resistance.

【図2】従来例に係る積層チップ型電子部品の構成を示
す説明図である。
FIG. 2 is an explanatory diagram illustrating a configuration of a multilayer chip electronic component according to a conventional example.

【符号の説明】[Explanation of symbols]

10 内部電極 11 積層チップ素体 12 外部電極 12a 主電極層 12b ニッケルのメッキ層 12c 貴金属のメッキ層 DESCRIPTION OF SYMBOLS 10 Internal electrode 11 Stacked chip body 12 External electrode 12a Main electrode layer 12b Nickel plating layer 12c Noble metal plating layer

───────────────────────────────────────────────────── フロントページの続き (72)発明者 丸野 哲司 東京都中央区日本橋一丁目13番1号 ティ ーディーケイ株式会社内 Fターム(参考) 4K044 AA13 AB10 BA06 BA08 BB02 BC02 BC14 CA15 CA18 5E001 AB03 AC09 AE02 AE03 AF00 AF06 AH01 AH07 AH08 AJ03 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Tetsuji Maruno 1-13-1 Nihonbashi, Chuo-ku, Tokyo TDK Corporation F-term (reference) 4K044 AA13 AB10 BA06 BA08 BB02 BC02 BC14 CA15 CA18 5E001 AB03 AC09 AE02 AE03 AF00 AF06 AH01 AH07 AH08 AJ03

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 内部電極をセラミックシートと交互に複
数枚積層させて焼成した積層チップ素体を基体とし、そ
の内部電極と電気的に導通する外部電極をチック素体の
両端部に設ける積層チップ型電子部品において、銅また
はニッケルを主成分とする燒結金属で内部電極と電気的
に導通する主電極層を形成すると共に、外表面を酸化し
難い貴金属のメッキ層で覆った外部電極を設けてなるこ
とを特徴とする積層チップ型電子部品。
1. A laminated chip in which a plurality of internal electrodes are alternately laminated with ceramic sheets and fired by laminating the laminated chip element as a base, and external electrodes electrically connected to the internal electrodes are provided at both ends of the tic element. In a type electronic component, a main electrode layer electrically connected to an internal electrode is formed of a sintered metal containing copper or nickel as a main component, and an external electrode whose outer surface is covered with a plating layer of a noble metal that is hardly oxidized is provided. A multilayer chip-type electronic component characterized in that:
【請求項2】 銅またはニッケルを主成分とする燒結金
属で内部電極と電気的に導通する主電極層を形成すると
共に、その主電極層の表面を酸化し難い貴金属のメッキ
層で覆った外部電極を設けてなることを特徴とする請求
項1に記載の積層チップ型電子部品。
2. An external electrode in which a main electrode layer electrically connected to an internal electrode is formed of a sintered metal containing copper or nickel as a main component, and a surface of the main electrode layer is covered with a noble metal plating layer which is hardly oxidized. The multilayer chip-type electronic component according to claim 1, further comprising an electrode.
【請求項3】 外表面を酸化し難い銀,金,パラジウ
ム,白金またはそれらの合金である貴金属のメッキ層で
覆った外部電極を設けてなることを特徴とする請求項1
または2に記載の積層チップ型電子部品。
3. An external electrode whose outer surface is covered with a plating layer of a noble metal which is hardly oxidized, such as silver, gold, palladium, platinum or an alloy thereof.
Or the multilayer chip electronic component according to 2.
【請求項4】 卑金属の内部電極を設けてなることを特
徴とする請求項1〜3のいずれかに記載の積層チップ型
電子部品。
4. The multilayer chip-type electronic component according to claim 1, further comprising a base metal internal electrode.
JP11108846A 1999-04-16 1999-04-16 Laminated chip type electronic component Pending JP2000299243A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11108846A JP2000299243A (en) 1999-04-16 1999-04-16 Laminated chip type electronic component

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11108846A JP2000299243A (en) 1999-04-16 1999-04-16 Laminated chip type electronic component

Publications (1)

Publication Number Publication Date
JP2000299243A true JP2000299243A (en) 2000-10-24

Family

ID=14495077

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11108846A Pending JP2000299243A (en) 1999-04-16 1999-04-16 Laminated chip type electronic component

Country Status (1)

Country Link
JP (1) JP2000299243A (en)

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Publication number Priority date Publication date Assignee Title
US7525241B2 (en) * 2003-09-30 2009-04-28 Epcos Ag Ceramic multi-layer component and method for the production thereof
JP2015029050A (en) * 2013-06-27 2015-02-12 株式会社村田製作所 Multilayer ceramic electronic component
JP2016012689A (en) * 2014-06-30 2016-01-21 株式会社村田製作所 Ceramic electronic component
CN111755249A (en) * 2019-03-27 2020-10-09 三星电机株式会社 Multilayer capacitor
US10840008B2 (en) 2015-01-15 2020-11-17 Murata Manufacturing Co., Ltd. Electronic component and electronic component-mounted structure
CN112530699A (en) * 2019-09-17 2021-03-19 三星电机株式会社 Multilayer capacitor

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7525241B2 (en) * 2003-09-30 2009-04-28 Epcos Ag Ceramic multi-layer component and method for the production thereof
US8776364B2 (en) 2003-09-30 2014-07-15 Epcos Ag Method for producing a multilayer ceramic component
US9186870B2 (en) 2003-09-30 2015-11-17 Epcos Ag Ceramic multi-layer component and method for the production thereof
JP2015029050A (en) * 2013-06-27 2015-02-12 株式会社村田製作所 Multilayer ceramic electronic component
JP2016012689A (en) * 2014-06-30 2016-01-21 株式会社村田製作所 Ceramic electronic component
US10269491B2 (en) 2014-06-30 2019-04-23 Murata Manufacturing Co., Ltd. Ceramic electronic component
US10840008B2 (en) 2015-01-15 2020-11-17 Murata Manufacturing Co., Ltd. Electronic component and electronic component-mounted structure
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US11515091B2 (en) 2019-09-17 2022-11-29 Samsung Electro-Mechanics Co., Ltd. Multilayer capacitor
US11776746B2 (en) 2019-09-17 2023-10-03 Samsung Electro-Mechanics Co., Ltd. Multilayer capacitor

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