JP4544896B2 - Electronic components - Google Patents

Description

  The present invention relates to a chip-shaped electronic component used by being incorporated in an electronic device such as a mobile phone.

  As a conventional electronic component, one having a structure in which external electrodes are attached to both end faces of an electronic component element body that is formed in a chip shape with a ceramic material or the like is known. The electrode is coated with an Ni plating layer for preventing solder erosion and an Sn plating layer for improving solder wettability in order on the surface of the base layer made of Ag, Cu, Cu / Ni alloy or the like. It is constructed by wearing and stacking.

In addition, when the above-described electronic component is mounted on an external wiring substrate such as a mother board by conventionally known soldering or the like, a “chip standing phenomenon” in which the electronic component rises due to the surface tension of the molten solder may occur. For this reason, in order to prevent such inconvenience, it has been proposed to deposit a metal material having poor solder wettability on the surface of the external electrode other than the mounting surface (see, for example, Patent Document 1). .)
JP-A-8-330174

  However, as in the conventional electronic component described above, advanced microfabrication technology is required to selectively deposit a metal material having poor solder wettability only on the surface of the external electrode other than the mounting surface. For this reason, the manufacturing process of the electronic component is greatly complicated, and there is a drawback that the mass productivity of the electronic component is significantly reduced.

  The present invention has been devised in view of the above-mentioned problems, and an object thereof is to provide a chip component that has good solder wettability and does not cause a chip standing phenomenon.

Electronic component of the present invention is an electronic component having external electrodes which are external electric circuit and soldered to the surface of the electronic component body, wherein the external electrodes, the underlying conductor layer, the first plating containing at least tin a layer, than the first plating layer and the second plated layer made of low melting point tin alloy, is formed by a product layer such that the second plating layer is a surface layer side of the first plating layer The thickness T ₁ of the first plating layer is 3 μm to 4 μm, the thickness T ₂ of the second plating layer is 0.005 μm to 0.1 μm, and the value of T ₁ / T ₂ is 30 to 800 Oh and is characterized in Rukoto.

  In the electronic component of the present invention, the base conductor layer is made of Ni plating, and the thickness of the second plating layer is set to 0.01 μm to 0.05 μm.

  Furthermore, the electronic component of the present invention is characterized in that the melting point of the first plating layer is 12 to 18 ° C. higher than the melting point of the second plating layer.

Further electronic component of the present invention, the feature that the metal component of said first plating layer is composed of Sn, a metal component of said second plating layer is made of any one of Sn-Ag, Sn-Cu, Sn-Bi To do.

Further electronic component of the present invention also provides that said electronic component body is a capacitor body formed by stacking via an internal electrode in which a plurality of dielectric layers are electrically connected to the external electrodes during It is characterized by.

  According to the electronic component of the present invention, the outer layer of the external electrode has two types of plating layers with good solder wettability, that is, a first plating layer containing Sn, and an Sn alloy having a lower melting point than the first plating layer. And the second plating layer having a low melting point is arranged on the surface layer side of the first plating layer having a high melting point, so that the electronic component is soldered to the external wiring board. When the temperature in the solder reflow furnace reaches the melting point of the second plating layer (near the solidus temperature of the solder) when mounted on the solder, the Sn alloy forming the second plating layer becomes familiar with the solder and the solder And the surface of the first plating layer is exposed. At this time, since the surface state of the external electrode is governed by the melting point of the exposed first plating layer, acceleration of solder wetting is effectively suppressed, and before the solder crawls along the surface of the external electrode. Don't be. After that, when the temperature in the furnace is further raised to near the melting point of the first plating layer (near the solder liquidus temperature), Sn and the like forming the first plating layer melt and become familiar with the solder. At this point, the solder is already bonded to the external wiring board, so that the force to suppress the “chip standing phenomenon” is applied. By soldering two types of plating layers having good solder wettability while being familiar with the solder at two stages, it is possible to mount the electronic component satisfactorily and stably.

  According to the present invention, the thickness of the second plating layer is made thinner than the thickness of the first plating layer, so that the melting of the solder is promoted, and the second plating layer is diffused into the first plating layer. This effect is enhanced by promoting the action of exposing the surface of the external electrode to suppress solder wetting on the side surface of the external electrode, in particular, by setting the thickness of the second plating layer to 0.01 to 0.05 μm.

  Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a sectional view showing an embodiment in which an electronic component of the present invention is applied to a multilayer ceramic capacitor, FIG. 2 is an external perspective view of the multilayer ceramic capacitor of FIG. 1, and the multilayer ceramic capacitor 10 shown in FIG. It has a structure in which external electrodes 4 are formed on the surface of a laminate 1 as a body.

  The laminate 1 is formed by laminating a plurality of dielectric layers 2 with an internal electrode 3 interposed therebetween, and the dielectric layer 2 is made of, for example, barium titanate, calcium titanate, strontium titanate. Etc., and the thickness thereof is set to 1 μm to 25 μm, for example. The internal electrode 3 disposed inside the multilayer body 1, specifically, the adjacent dielectric layer 2-2 is made of, for example, a metal material mainly composed of Ni, Cu, or an alloy thereof. The thickness is set to 1 μm to 5 μm, for example.

  In order to manufacture the laminate 1, first, an appropriate organic solvent, glass frit, organic binder, etc. are added to and mixed with the dielectric material powder to form a slurry, and this is made into a conventionally known doctor blade. A ceramic green sheet having a predetermined shape and thickness is obtained by a method or the like. Next, a conductive paste obtained by mixing Ni frit with a glass frit, a vehicle composed of an organic binder and a solvent is applied to one main surface of each ceramic green sheet in a predetermined pattern by a conventionally known screen printing method or the like. Print and apply on. Next, a large number of ceramic green sheets are produced by laminating and pressing a predetermined number of the obtained ceramic green sheets by a conventionally known green sheet laminating method or the like. This large laminate was collectively cut using a dicing apparatus for each element region to form an unfired laminate 1. When this cutting is performed, a part of the conductor pattern 3 that becomes the internal electrode 3 is exposed from a pair of end faces facing each other of the multilayer body 1. Then, for example, by firing at a temperature of 1100 ° C. to 1400 ° C., a rectangular parallelepiped laminated body 1 in which a plurality of dielectric layers 2 are laminated with an inner conductor 3 film interposed therebetween is formed.

In addition, the external electrode 4 formed on the surface of the multilayer body 1 was formed by sequentially laminating a first base conductor layer 7, a second base conductor layer 8, a first plating layer 9, and a second plating layer 11. It has a four-layer structure.

The first base conductor layer 7 is a thick film conductor made of a metal material mainly composed of Cu, Cu / Ni, for example, and the thickness thereof is set to, for example, 5 to 30 μm, and the inner conductor 3 in the multilayer body 1. And electrically connected. The second base conductor layer 8 is, for example, for enhancing solder resistance, and is formed by Ni plating or the like, and the thickness thereof is set to 1 μm to 5 μm, for example.

To form the underlying conductor layers 7 and 8, first, a conductor paste is prepared by mixing a vehicle containing an organic binder and a solvent with a powder containing spherical Cu / Ni powder, flaky Cu / Ni powder and glass powder. To do. The conductor paste thus obtained is printed and applied to the side surface of the laminate 1 by a conventionally known dip method or screen printing method. Incidentally, when printing and coating, paste top surface of the layered structure 1, sneak on the lower surface and the other side, that form a part of the first base conductor layer 7. Next, the conductor paste is fired at 600 ° C. to 900 ° C. and baked on the side surface of the multilayer body 1, thereby forming the first base conductor layer 7 as a thick film conductor. At this time, the baked first base conductor layer 7 is electrically connected to the outer peripheral portion of the internal electrode 2 exposed on the side surface of the multilayer body 1 before applying the conductor paste. Then, by forming a Ni plating layer on the surface of the first base conductor layer 7 using a wet plating method such as electrolytic plating, the second base conductor layer 8 is formed.

  On the other hand, the first plating layer 9 is composed of a plating layer containing at least Sn, and the thickness thereof is set to 3 μm or more, for example. The second plating layer 11 is formed on the surface layer side of the first plating layer 9, and the material thereof is an Sn alloy having a melting point lower than that of the first plating layer 9, for example, Sn-Ag, Sn-Cu. Sn-Bi or the like is used, and the thickness thereof is set to 0.01 μm to 0.05 μm, for example.

For the formation of the first plating layer 9 and the second plating layer 11, wet plating such as electrolytic plating is used as in the case of forming the second base conductor layer 8 described above.

  Thus, the multilayer ceramic capacitor 10 described above is mounted on an external wiring board such as a mother board by conventionally known soldering or the like, and is an active component that constitutes a predetermined circuit together with other electric circuits and electronic components. Will function as.

  In the electronic component of the present embodiment as described above, the outer layer of the external electrode 4 has two types of plating layers with good solder wettability, that is, the first plating layer 9 containing Sn and the first plating layer 9. And a second plating layer 11 made of a low melting point Sn alloy. In addition, since the second plating layer 11 having a low melting point is arranged on the surface layer side of the first plating layer 9 having a high melting point, a solder reflow furnace is used when mounting electronic components on the external wiring board by soldering. When the temperature of the inside reaches the melting point of the second plating layer 11 (near the solidus temperature of the solder), the Sn alloy forming the second plating layer 11 becomes familiar with the solder and promotes the melting of the solder. The surface of the plating layer 9 is exposed. At this time, since the surface state of the external electrode 4 is governed by the melting point of the exposed first plating layer 9, the acceleration of solder wetting is effectively suppressed, and the solder crawls along the surface of the external electrode 4. It won't be up to. Thereafter, when the temperature in the furnace is further raised to near the melting point of the first plating layer 9 (near the solder liquidus temperature), Sn or the like forming the first plating layer 9 melts and becomes familiar with the solder. However, since the solder is already bonded to the external wiring board at this point, the force to suppress the “chip standing phenomenon” is applied. Thus, it is possible to mount the electronic component satisfactorily and stably by soldering the two types of plating layers having good solder wettability while being familiar with the solder at two stages.

  In the electronic component of this embodiment, the second plating layer 11 is made thinner than the first plating layer 9 to promote melting of the solder, and the second plating layer 11 is diffused into the first plating layer 9. Then, the second plating layer 11 is exposed and the action of suppressing solder wetting to the side surface of the external electrode 4 is promoted. In particular, the thickness of the second plating layer 11 is set to 0.01 μm to 0.05 μm. Further, it is possible to more effectively suppress solder wetting on the side surface of the external electrode 4.

  In addition, this invention is not limited to embodiment mentioned above, A various change, improvement, etc. are possible in the range which does not deviate from the summary of this invention.

  For example, in the above-described embodiment, the external electrode 4 may be configured by laminating a Sn alloy plating layer having a melting point lower than that of the second plating layer 11 on the surface of the second plating layer 11.

In the embodiment described above, the base electrode layer is formed by laminating the first base conductor layer 7 made of the thick film conductor and the second base conductor layer 8 made of the Ni plating film. Instead of this, a single underlying conductor layer made of a Ni plating film may be used. In this case, the base conductor layer is directly connected to the exposed portion of the internal electrode exposed on the surface of the electronic component element body.

Further, in the above-described embodiment, the case where the electronic component of the present invention is applied to a multilayer ceramic capacitor has been described as an example. However, it is needless to say that the present invention can be applied to electronic components other than the multilayer ceramic capacitor.
(Experimental example)

  Next, the effect of this invention is demonstrated based on an experiment example.

First, multilayer ceramic capacitor samples with different thicknesses of the first plating layer and the second plating layer were prepared, and a solder wettability evaluation test and a chip standing evaluation test were performed. The prepared samples had four types of first plating layers in the Sn thickness range of 1-4 μm and six types of second plating layers in the Sn—Cu thickness range of 0.005-1 μm. In the experiment, a reflow furnace having a profile of preheating 150 ° C., 120 seconds, peak temperature 230 ° C., 10 seconds was obtained by placing a sample of the above multilayer ceramic capacitor on a test glass epoxy substrate printed with solder paste at a predetermined position. Went through. A solder paste having a Sn / Ag / Cu weight ratio of 98.5 / 1.0 / 0.5 was used. The test results are shown in Table 1. In this experiment, the solder wetting evaluation test was evaluated as x when the area of the sample covered with solder was less than 90%, Δ when 90 to 95%, and ◯ when 95% or more. In the chip standing evaluation test, for each of 100 samples, the number of samples rising from one electrode of the sample being detached from the test substrate was counted.

  According to Table 1, it was confirmed that no chip standing occurred when the thickness of the second plating layer was 0.01 to 0.05 μm, and good solder wettability was obtained when the thickness of the first plating layer was 3 μm or more.

Also, by using a material in which Cu, Ag or Bi is mixed with Sn, eight types of capacitor samples were prepared by changing the melting point with a second plating layer thickness of 0.03 μm by a known alloy plating method, and the same solder evaluation test Went. The test results are shown in Table 2.

  According to Table 2, it was confirmed that no chip standing occurred when the difference in melting point between the first plating layer and the second plating layer was in the range of 12 to 18 ° C. Therefore, it is preferable that the melting point of the first plating layer is 12 to 18 ° C. higher than the melting point of the second plating layer.

It is sectional drawing which shows embodiment which applied the electronic component of this invention to the multilayer ceramic capacitor. FIG. 2 is an external perspective view of the multilayer ceramic capacitor of FIG. 1.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Laminated body 2 ... Dielectric layer 3 ... Internal electrode 4 ... External electrode 7, 8 ... Base conductor layer 9 ... 1st plating layer (Sn plating layer)
10 ... Multilayer ceramic capacitor 11 ... Second plating layer (Sn-Cu plating layer)

Claims (5)

In an electronic component having an external electrode soldered to an external electric circuit on the surface of the electronic component body,
The external electrode has, on a base conductor layer, and the first plating layer containing at least tin, than the first plating layer and the second plated layer made of low melting point of tin alloy, the second plating layer is the than the first plating layer is formed is the product layer such that the surface layer side, the thickness _{T 1} of the first plating layer is 3Myuemu～4myuemu, the thickness _{T 2} of the second plating layer is 0.005μm a _{～0.1Myuemu,} electronic component values of T 1 / _{T 2} is wherein 30 to 800 der Rukoto. The electronic component according to claim 1, wherein the base conductor layer is made of Ni plating, and a thickness T ₂ of the second plating layer is set to 0.01 μm to 0.05 μm. Electronic component according to claim 1 or claim 2, wherein the melting point of said first plating layer is 12 to 18 ° C. temperature higher than the melting point of the second plating layer. The metal component of the first plating layer is made of Sn, the metallic component of the second plating layer is Sn-Ag, Sn-Cu, claims 1, characterized in that it consists of one of Sn-Bi 3 The electronic component according to any one of the above. It said electronic component body is a plurality of dielectric layers, wherein said that the external electrode is a capacitor body formed by stacking via an internal electrode that is electrically connected between the claims 1 to Item 5. The electronic component according to Item 4 .

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