JPH05251565A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH05251565A JPH05251565A JP4905192A JP4905192A JPH05251565A JP H05251565 A JPH05251565 A JP H05251565A JP 4905192 A JP4905192 A JP 4905192A JP 4905192 A JP4905192 A JP 4905192A JP H05251565 A JPH05251565 A JP H05251565A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor integrated
- integrated circuit
- terminal
- mos transistor
- type mos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体集積回路、特に、
スタンダード・セル,ゲートアレイなどのセミカスタム
の半導体集積回路に関する。BACKGROUND OF THE INVENTION The present invention relates to semiconductor integrated circuits, and more particularly,
The present invention relates to semi-custom semiconductor integrated circuits such as standard cells and gate arrays.
【0002】[0002]
【従来の技術】従来、この種の半導体集積回路は半導体
集積回路内部の論理回路を直接外部からアクセスする為
の測定パッドを機能ブロックとして有していなかった。2. Description of the Related Art Conventionally, this type of semiconductor integrated circuit does not have a measurement pad as a functional block for directly accessing a logic circuit inside the semiconductor integrated circuit from the outside.
【0003】[0003]
【発明が解決しようとする課題】上述した従来の半導体
集積回路は、半導体集積回路内部の論理回路を直接アク
セスする為の測定パッドを機能ブロックとして有してい
ないので、外部から電位を与えたり、電位を測定する事
が難かしいという欠点がある。Since the conventional semiconductor integrated circuit described above does not have a measurement pad as a functional block for directly accessing the logic circuit inside the semiconductor integrated circuit, it is possible to apply a potential from the outside or a potential. Has the drawback that it is difficult to measure.
【0004】[0004]
【課題を解決するための手段】本発明の半導体集積回路
は、半導体集積回路内部の論理回路を直接外部からアク
セスする為の測定パッドを機能ブロックとして有してい
る。A semiconductor integrated circuit according to the present invention has a measurement pad as a functional block for directly accessing a logic circuit inside the semiconductor integrated circuit from the outside.
【0005】[0005]
【実施例】次に本発明について図面を参照して説明す
る。図1は、本発明の一実施例を示すブロック図であ
る。測定パッド1は本回路を含む半導体集積回路チップ
の外部から電位を与えたり電位を測定する為の測定パッ
ドである。入出力端子10は測定パッド1を通して電位
を与えたり電位を測定する被測定機能ブロックを接続す
る為の端子、入出力端子11は通常動作時に被測定機能
ブロックを他の機能ブロックに接続する為の端子であ
る。又、制御端子12は外部から測定パッド1を通して
アクセスするか否かを制御する端子である。The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. The measurement pad 1 is a measurement pad for applying a potential from the outside of the semiconductor integrated circuit chip including this circuit or measuring the potential. The input / output terminal 10 is a terminal for connecting a measured functional block that applies a potential through the measurement pad 1 or measures the potential, and the input / output terminal 11 is a terminal for connecting the measured functional block to another functional block during normal operation. It is a terminal. The control terminal 12 is a terminal for controlling whether or not an access is made from the outside through the measurement pad 1.
【0006】制御端子12にLレベルの電位を入力する
とN型MOSトランジスタ20はオフ状態、N型MOS
トラジスタ21はオン状態となり入出力端子10と入出
力端子11の間に信号パスが形成される。一方、制御端
子12にHレベルの電位を入力すると、N型MOSトラ
ンジスタ20がオン状態、N型MOSトランジスタ21
がオフ状態となり入出力端子10と11の間の信号パス
が遮断され、測定パッド1と入出力端子10の間に信号
パスが形成され、外部から測定パッド1を通して入出力
端子10に接続される被測定機能ブロックをアクセスす
る事が可能となる。When an L-level potential is input to the control terminal 12, the N-type MOS transistor 20 is turned off and the N-type MOS transistor 20 is turned off.
The transistor 21 is turned on and a signal path is formed between the input / output terminal 10 and the input / output terminal 11. On the other hand, when an H level potential is input to the control terminal 12, the N-type MOS transistor 20 is turned on and the N-type MOS transistor 21 is turned on.
Is turned off, the signal path between the input / output terminals 10 and 11 is cut off, a signal path is formed between the measurement pad 1 and the input / output terminal 10, and is externally connected to the input / output terminal 10 through the measurement pad 1. It is possible to access the measured function block.
【0007】図2は本発明の一使用例を示すブロック図
である。機能ブロック(1)101と機能ブロック
(2)102の間に図1に示す回路を挿入する事により
制御端子12からの制御信号に応じて機能ブロック
(1)101(又は機能ブロック(2)102)から機
能ブロック(2)102(又は機能ブロック(1)10
1)へ信号を伝搬させるか、半導体集積回路チップ外部
から機能ブロック(2)102を直接アクセスするかを
選択する事ができる。FIG. 2 is a block diagram showing an example of use of the present invention. By inserting the circuit shown in FIG. 1 between the functional block (1) 101 and the functional block (2) 102, the functional block (1) 101 (or the functional block (2) 102 is responsive to the control signal from the control terminal 12. ) To the functional block (2) 102 (or the functional block (1) 10
It is possible to select whether to propagate the signal to 1) or to directly access the functional block (2) 102 from outside the semiconductor integrated circuit chip.
【0008】[0008]
【発明の効果】以上説明したように本発明は、半導体集
積回路内部の論理回路を直接外部からアクセスする為の
測定パッドを機能ブロックとして有しており半導体集積
回路の設計者が望む所にこの測定パッドブロックを挿入
することにより半導体集積回路の内部の任意の論理回路
を直接外部からアクセスできる効果がある。As described above, according to the present invention, the measurement pad for directly accessing the logic circuit inside the semiconductor integrated circuit from the outside is provided as a functional block. By inserting the measurement pad block, an arbitrary logic circuit inside the semiconductor integrated circuit can be directly accessed from the outside.
【図1】本発明の一実施例を示すブロック図FIG. 1 is a block diagram showing an embodiment of the present invention.
【図2】本発明の一使用例を示すブロック図である。FIG. 2 is a block diagram showing a usage example of the present invention.
1 測定パッド 10 入出力端子 11 入出力端子 12 制御端子 20 N型MOSトランジスタ 21 N型MOSトランジスタ 30 インバータ回路 1 Measuring Pad 10 Input / Output Terminal 11 Input / Output Terminal 12 Control Terminal 20 N-type MOS Transistor 21 N-type MOS Transistor 30 Inverter Circuit
Claims (1)
下機能ブロックと呼ぶ)を組合せて一つの半導体装置を
構築するスタンダード・セル又はゲートアレイタイプの
半導体集積回路において、半導体集積回路の外部から直
接内部の論理回路の電位を測定したり、電位を与える事
を可能とする測定パッドを機能ブロックとして有する事
を特徴とする半導体集積回路。1. In a standard cell or gate array type semiconductor integrated circuit in which a logic circuit block having a certain function (hereinafter referred to as a functional block) is combined to construct one semiconductor device, the inside is directly external to the inside of the semiconductor integrated circuit. 2. A semiconductor integrated circuit having a measurement pad as a functional block capable of measuring the electric potential of the logic circuit and applying the electric potential.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4905192A JPH05251565A (en) | 1992-03-06 | 1992-03-06 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4905192A JPH05251565A (en) | 1992-03-06 | 1992-03-06 | Semiconductor integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH05251565A true JPH05251565A (en) | 1993-09-28 |
Family
ID=12820288
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4905192A Pending JPH05251565A (en) | 1992-03-06 | 1992-03-06 | Semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH05251565A (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60206042A (en) * | 1984-03-29 | 1985-10-17 | Toshiba Corp | Semi-custom ic |
JPH02191359A (en) * | 1988-01-22 | 1990-07-27 | Matsushita Electric Ind Co Ltd | Standard cell and semiconductor integrated circuit device using same |
JPH03155658A (en) * | 1989-11-14 | 1991-07-03 | Seiko Epson Corp | Pad cell for master slice layout integrated circuit device |
-
1992
- 1992-03-06 JP JP4905192A patent/JPH05251565A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60206042A (en) * | 1984-03-29 | 1985-10-17 | Toshiba Corp | Semi-custom ic |
JPH02191359A (en) * | 1988-01-22 | 1990-07-27 | Matsushita Electric Ind Co Ltd | Standard cell and semiconductor integrated circuit device using same |
JPH03155658A (en) * | 1989-11-14 | 1991-07-03 | Seiko Epson Corp | Pad cell for master slice layout integrated circuit device |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19980818 |