JPH0318954Y2 - - Google Patents

Description

[Detailed explanation of the idea] The present invention relates to an output circuit of an integrated circuit device.

It is well known that the input/output circuits of integrated circuit devices that have a clear purpose are generally designed to have characteristics commensurate with that purpose. Or, if the drive capability becomes extremely small, test items and test time when testing the integrated circuit device increase, resulting in a reduction in mass production capacity. In addition, if testing of internal circuits that operate at high speeds is only possible through output circuits with low drive capacity, the input impedance of the measuring instrument used during the test makes it impossible to test at high speeds and sufficient test results cannot be obtained. There were other problems.

The present invention was developed in consideration of these points.
It is an object of the present invention to provide an output circuit of an integrated circuit device configured to improve the characteristics of the output circuit, especially the drive ability, or to make the characteristics uniform only during testing.

In the present invention, for an output circuit having an output transistor circuit connected between power supply terminals having a constant potential difference and driving the output terminal based on an operational input signal, a transistor is provided between at least the output terminal and one power supply terminal. and control means for receiving at least a test signal, the transistor being in a cut-off state during non-testing,
During a test, the output transistor circuit conducts at least a period during which a current path is formed between the output terminal and the one power supply terminal, and the output transistor circuit is made conductive between the output terminal and the one power supply terminal. The present invention is characterized in that it includes a control means for forming a current path through the transistor. Therefore, the output circuit according to the present invention can not only shorten test items and test time, but also perform internal tests that require high-speed operation without taking into account the influence of the input impedance of the measuring instrument. Test results are available. Furthermore, the present invention has the above-mentioned effects particularly in cases where an upper limit of the drive capacity is set to prevent double keys, such as the key scan signal output circuit of an integrated circuit device for an electronic desktop calculator. .

The present invention will be explained below with reference to the drawings.

Figure 1 shows an n-channel MOS field effect transistor (hereinafter simply referred to as a transistor) _Q11 and
Figure 2, which is an example of a conventional output circuit composed of _Q12 , is a complementary MOS logic circuit (C-MOS).
This is an example of a conventional output circuit, and its operation is well known, so a description of its operation will be omitted.

FIG. 3 shows an embodiment in which the present invention is applied to the output circuit of FIG. 1, in which transistors Q ₁₁ and Q ₁₂ are
This transistor has the same characteristics as the one shown in the figure. A transistor Q ₁₃ whose source and drain electrodes are connected to the power supply V DD and output terminal 2, respectively.
is “ON” only during testing by test signal input 3
This is a transistor to equivalently improve the drive ability of the transistor _Q11 , while the transistor _Q14 whose source and drain electrodes are connected to the output terminal and the ground potential is the test signal input 3.
A transistor that turns “ON” and “OFF” in synchronization with transistor Q ₁₂ only when given
This will equivalently improve the Q ₁₂ 's drive ability. It is also a gate circuit for supplying a signal to the gate electrode of the transistor Q ₁₄ for operating the AND gate circuit 4 transistor Q ₁₄ only during testing in synchronization with the transistor Q ₁₂ . FIG _. 4 shows an embodiment in which the present invention is applied to the output circuit of FIG. 2, and as in the _explanation of FIG.
Similarly, Q ₂₄ is used to equivalently improve the drive ability of transistor Q ₂₂ only during testing. By configuring the output circuit of an integrated circuit device as proposed, the influence of the input impedance of measuring instruments and other devices during testing is reduced, making high-speed testing easier, reducing test time, and improving the speed of high-speed operating parts within integrated circuit devices. The effect can be obtained by obtaining sufficiently good results in the test. Also, if the characteristics of transistors Q 13 and Q 14 are given so that the characteristics of transistors Q ₁₁ and Q ₁₃ and the characteristics of transistors _{Q 12} and _{Q 14} in Fig. 2 are the same as the corresponding characteristics of other output circuits, Output circuits that exhibit different output characteristics during actual use can be measured at the same time under the same test conditions, reducing test time. Needless to say, the same applies to the case shown in FIG.

FIGS. 5 and 6 are modifications of FIGS. 3 and 4, and are other embodiments of the present invention. Note that both transistors Q ₁₃ and Q ₁₄ in FIG _. 3 and transistors Q ₂₃ and Q ₂₄ in FIG _.
may be omitted. Similarly, in FIG. 4, various modifications can be made without departing from the purpose of the present invention, such as the transistor Q ₂₃ may be omitted if the drive capability of the transistor Q ₂₁ is sufficiently large.

As described above, for an output circuit having an output transistor circuit connected between power supply terminals with a constant potential difference and driving the output terminal based on an operational input signal, a transistor is connected between at least the output terminal and one power supply terminal. and control means for receiving at least a test signal, the transistor being in a cut-off state during non-testing,
During a test, the output transistor circuit conducts at least a period during which a current path is formed between the output terminal and the one power supply terminal, and the output transistor circuit is made conductive between the output terminal and the one power supply terminal. By providing control means for forming a current path through the transistor,
The drive ability to the output terminal can be increased only during testing, reducing the influence of input impedance of measuring instruments, etc., facilitating high-speed testing, and shortening test time.

[Brief explanation of the drawing]

Figure 1 is an example of a conventional output circuit using an n-channel MOS field effect transistor, and Figure 2 is a complementary type.
An example of a conventional output circuit using a MOS logic circuit, FIG. 3 is an embodiment of the present invention for FIG. 1, FIG. 4 is an embodiment of the present invention for FIG. 2, and FIGS.
The figure shows another embodiment of the present invention. _Q11 to _Q15 , _Q21 to _Q26 ...MOS field effect transistors, _Q21 , _Q23 , _Q25 ... _Q22 , _Q24 , _Q26 and MOS field effect transistors having a different channel type. 1...Internal operation signal input, 2...Output terminal for deriving it, 3...Test signal input, 4...
AND gate circuit, 5... Inverter circuit, 6...
...OR circuit, V DD ...power supply terminal.

Claims (1)

[Scope of utility model registration request] In an output circuit having an output transistor circuit connected between power supply terminals with a constant potential difference and driving the output terminal based on an operation input signal, a transistor is provided between at least the output terminal and one power supply terminal, and at least control means for receiving a test signal, the control means being configured to keep the transistor in a cut-off state during non-testing, and for a period during which the output transistor circuit forms a current path between at least the output terminal and the one power supply terminal during testing; A control means is provided for making the transistor conductive to form a current path through the transistor between the output terminal and the one power supply terminal, thereby increasing the drive ability to the output terminal only during testing. output circuit.