KR840001544B1 - Test circuit for mos deuices - Google Patents

Abstract

A test circuit for use in an MOS device includes two inputs, a first input which is responsive to a test signal of opposite polarity to that of the supply voltage, and a second ouput which is responsive to a test signal of the same polarity as that of supply voltage but of a substantially higher magnitude than that of the supply voltage.

Description

Test circuit for MOS device

1 is a circuit diagram of a specific embodiment of a first gate circuit of a test circuit according to the present invention.

2 is a block diagram of a specific embodiment of a test circuit according to the present invention.

The present invention relates to an integrated MOS transistor having a test circuit comprising a first MOS transistor and at least one second MOS transistor circuit on the same substrate, wherein the test circuit and the second MOS transistor circuit have one or more external input connection terminals commonly used. The output of the test circuit is connected to a second MOS circuit, the output of the second MOS circuit is connected to an external output connection terminal, and a test signal having a polarity opposite to that of the normal supply voltage V _{B is} provided to the first circuit of the test circuit. When applied to the input connection terminal of the one-gate circuit, the second MOS transistor circuit is brought into a test mode and the second MOS circuit is fully or partially tested. Accordingly, the second MOS circuit generates an output signal at an output connection terminal, which indicates whether the second MOS circuit performs correct or incorrect operation.

As is known, as the degree of directivity and hence the complexity of the directing circuitry is increased, it is necessary to carry out a test called so called pretesting so that defects which occur in the integrated circuit during manufacture are detected. Design of integrated circuits having MOS transistors to be tested as well as test circuits is known from US Pat. No. 4,253,059. However, it is obvious that testing such a circuit becomes increasingly difficult because the integration increases the complexity of the integrated circuit but does not increase accordingly. As a result of mismatch between each connection terminal of the integrated circuit (and between other integrated circuit terminals), the voltage transient due to the polarity and the reverse polarity of the normal signal and the voltage due to the normal supply voltage are generated during the normal operation of the circuit. A phenomenon occurred that caused the test circuit to turn on accidentally during normal operation, such a change in test mode would cause the circuit to malfunction during normal operation and eventually destroy the system.

Accordingly, it is an object of the present invention to provide an integrated circuit which reduces the external connection board and does not cause any problem in testing the circuit. Therefore, the integrated transistor device according to the present invention includes a first gate circuit G ₁ having first and second inputs C _O (C ′) and an output A, and three latch circuits L ₁ ( L ₂ ) (L ₃ ) and the decoder consists of a test circuit (G ₁ , L ₁ , L ₃ , L ₃ , DEC). External input terminals (terminals of the circuit to be tested) may be connected to the inputs C _O and C ′ of the gate circuit like the input terminals C ₁ (C ₂ ) and C ₃ of the latch circuit. The first input C _O receives a test signal having a polarity opposite to that of the normal voltage V _B , and the second input C ′ has the same polarity as the supply voltage V _B but with a greater amplitude. Receive a test signal having a. Thereafter, the first gate circuit G _{1 generates an} enable signal E ₁ , E ₂ , E ₃ at the output terminal A, thereby providing an input connection terminal C ₁ (C ₂ ) (C ₃ ). The test signal I ₁ (I ₂ ) (I ₃ ) of the test circuit applied to) is tested.

An integrated circuit having a test circuit and a MOS transistor circuit according to the present invention, and in general, having an external input connection terminal, requires a small number of external input connection terminals, which is a test signal having a polarity opposite to that of a normal supply voltage. Is only possible when is used. One test gate circuit is provided to prevent voltage transients due to the opposite polarity of the normal supply voltage. This transient occurs during normal operation of the second MOS transistor circuit, and therefore the test circuit is accidentally turned on. Phenomenon occurs. Such voltage transients are caused by mismatches between the connection terminals of several integrated circuits (MOS) transistors. In the integrated circuit according to the present invention, the test circuit is not turned on accidentally by the voltage transient phenomenon. By installing the first gate circuit in the test circuit according to the present invention, under the control of a test signal having the same polarity but a larger amplitude than the normal voltage applied to the second input, the gate circuit needs to test the test terminal. Only respond to test signals. Therefore, the circuit is not set in the test mode by accident, and additional precautions for the wrong selection of the test mode can be made by using two test signals for the first gate circuit.

In a preferred embodiment of the test circuit according to the present invention, the present invention provides that the first gate circuit includes first, second and third depletion FETs, and fourth, fifth, sixth and seventh incremental FETs. Characterized in that. The first FET has a gate coupled to the first input and a source coupled to ground, the gate and source of the second FET are interconnected and coupled to the drain of the first FET, and have a drain coupled to the supply voltage. A sixth FET having a gate coupled to the second input and a drain coupled to the supply voltage, a sixth FET having a gate coupled to the supply voltage and a source coupled to ground and a drain coupled to the source of the fifth FET, and the seventh FET has a The fourth FET has a gate coupled to the drain and a source coupled to ground, and the fourth FET has a gate coupled to the drain of the first FET, a source coupled to the drain of the seventh FET, and the third FET has a gate coupled to the drain and output of the fourth FET. And a drain coupled to the source and supply voltage.

For example, the test signal may be blocked in the test terminal because signal transmission occurs from a test terminal to a corresponding point of another circuit through another circuit turned on and off by the output signal of the first gate circuit.

According to the arrangement of the first gate circuit according to the present invention, a preferable switching function is performed. That is, a "low" output signal is generated only when the voltage on the first input is lower than -3V and when the voltage on the second input is higher than the normal supply voltage.

In a further preferred embodiment of the test circuit according to the invention, the test circuit according to the invention comprises at least one (n) latch circuit and one out of 2 ⁿ (1 out) consisting of a signal input, an output of a pair of enable input waves. of 2) ⁿ decoder. The signal input of each latch circuit is coupled to one of the test terminals and the output of the inter latch circuit is coupled to one of the inputs of the 1 out of 2 ⁿ decoder. The enable input of the latch circuit is coupled to the output of the first gate circuit, and the output of the 1 out of 2 ⁿ decoder is coupled to the connection point of the other circuit to which the test signal is to be applied.

The latch circuit has the following characteristics; When the enable input goes from the "high" level to the "low" level, the information ("0" '1') that appears at the signal input is passed to the output, where the value passed to the output is enabled again. It stays until you reach level. The output is always "low" when the enable input is "high".

According to an arrangement of test circuits, which is a preferred embodiment of the present invention, 2 ⁿ different test modes can be achieved by a second input of n + 1 test terminals and a first gate circuit, wherein the latch circuit is applied thereto. It serves to maintain a test signal of a specific pattern. Such a pattern can only be changed when the enable signal on the output of the first gate circuit is in the "high" state and again in the "low" state, and the retained pattern will not be affected by the voltage wave on the test terminal. Do not receive.

Hereinafter, the present invention will be described in detail with reference to the drawings.

1 shows a test circuit according to the present invention using three deficient MOSFETs (T ₁ , T ₂ , T ₃ ) and four incremental MOSETs (T ₄ , T ₅ , T ₆ , T ₇ ). Treated specific examples are shown.

In the FET _1, is coupled to the first input gate test terminal C _O, the source is grounded.

In FET T ₂ , the gate and the source are coupled to each other and to the drain of FET T ₁ ,

The drain is coupled to the + V _B supply voltage. In FET T ₅ , the gate is coupled to the second input C ′ and the drain is coupled to the + V _B supply voltage.

In FET T ₆ , the gate is coupled to the + V _B supply voltage, the source is grounded, and the drain is coupled to the source of FET T ₅ .

In FET T ₇ , the gate is coupled to the drain of FET T ₆ and the source is grounded.

In FET T ₄ , the gate is coupled to the drain of FET T ₁ , and the source is coupled to the drain of FET T ₇ .

In FET T ₃ , the gate and the source are respectively coupled to the drain wave output A of FET T _{4 and} the drain is coupled to the + V _B supply voltage.

In the figure, + V _B is an operating voltage.

Input C 'does not need to be a special terminal on the IC, but is a terminal required for the rated operating mode. However, the terminal receives a test signal having the same polarity as the rated supply voltage wave but having a larger amplitude. A test signal having a polarity opposite to the polarity of the rated supply voltage of the integrated circuit is applied to the input C _O , and at the same time a test signal having the same polarity as the rated supply voltage but greater than the rated supply voltage is applied to the input C ′. Only if so, this circuit will be set to the test mode. In this case, this circuit works as follows.

At a supply voltage of + 5V, if a signal of + 12V is applied to the input C ', the internal connection point 2 goes from the HIGH state (more than 2.5V) to the LOW state (about 0V).

The drain of FET T ₅ - T ₆ the source resistance of the drain of the FET - are lower than the source resistance. Therefore, the connection point 2 will be higher than + 2.5V. If the signal from the wave between 0 + 5V is applied to the input -C 'drain of FET T ₆ - the source-drain resistance of the FET T ₆ - voltage is higher than the source resistor connecting point (2) is almost OV.

If 3V is applied to less than the input signal is an internal connection point C _O (1) is a HIGH state. Therefore, the connection point (1) (2) only when the signal is above 12V unit signals below -3V is applied to the input C _O at the same time applied to the input C 'is a HIGH state. Therefore, FETs T ₄ and T ₇ are turned on and the output A of the first gate circuit is turned low (almost OV). If one of the two inputs _CO or C 'does not meet the above condition, the output A of the first gate circuit will be HIGH (+ 5V).

2 is a block diagram of a test circuit according to the present invention. The first gate circuit G ₁ has two inputs C ₀ , C ′ and an output A, and the three latch circuits L ₁ , L ₂ , L ₃ (thus n = 3 in this example) are each a signal. Input (I ₁ , I ₂ , I ₃ ) Wave, Drive Input (E ₁ , E ₂ , E ₃ ) Wave Output Pair (Q ₁ , Q ₁ ), (Q ₂ , Q ₂ ), (Q ₃ , Q ₃ Has

The test terminals to which test signals with a polarity opposite to the polarity of the rated supply voltage are applied are denoted by C _O , C ₁ , C ₂ and C ₃ . These rosettes are used as terminals for the other circuits to be tested. The connection between the test terminal and other circuits is denoted by S ₀ , S ₁ , S ₂ and S ₃ . The test terminal C _O forms a first input of the first gate circuit, while each of the test terminals C ₁ , C ₂ , C ₃ has a signal input I ₁ , I ₂ , I ₃ of the associated latch circuit. Is coupled to.

₁,Q₂,

₂,Q₃,Q₃)의 출력은 디코더(1 out of 2³)에 결합된다. 상기 디코더의 출력(본 실시예에서는 M₁내지 M₈의 8개의 출력)은 테스트 신호가 인가되는 다른 회로의 접속점에 결합된다.The second input of the first gate circuit is coupled to terminal C ', which is supplied with a test signal having the same polarity as the supply voltage wave but having a larger amplitude than the supply voltage, and via the connection point S' of the other circuit. Appropriate connection points are coupled to the terminals. Thus terminal S 'can be used as a terminal for another circuit. Latch Circuit (Q ₁ ,

₁ , Q ₂ ,

The outputs of ₂ , Q ₃ and Q ₃ are coupled to a decoder 1 out of 2 ³ . The output of the decoder (eight outputs of M ₁ to M ₈ in this embodiment) is coupled to the connection point of another circuit to which a test signal is applied.

If the signal at connection point A is in the LOW (OV) state, the latch circuit will be set via the test terminals I ₁ , I ₂ , I ₃ . The logic state of the latch circuit is maintained until the latch circuit is reset by the first gate circuit. Therefore, if the signal at connection point A is HIGH (+5) and the latch circuit is not set via the test terminals I ₁ , I ₂ and I ₃ , it will be reset if the latch circuit is set. .

₃)은 LOW 상태로 될것이다. 이는 디코더의 출력(M₁내지 M₈)이 HIGH 상태로 된다는 것을 의미하며, 회로는 정격동작 모드로 된다. 그러나, 만일 접속점 A의 신호가 LOW 상태이고, 테스트 모드가 테스트 단자를 거쳐 선택되면, 디코더 출력중의 하나는 LOW 상태로 되고, 다른 7개의 디코더 출력은 HIGH로 된다. 이는 테스트 모드중의 하나가 얻어지게 되어 회로가 상기 얻어진 테스트 모드로 동작될 것이라는 것을 의미한다.In this case, the output of the latch circuit (Q ₁ , Q ₂ ,

₃ ) will be LOW. This means that the outputs M ₁ to M ₈ of the decoder go to the HIGH state, and the circuit is in the rated operation mode. However, if the signal of connection point A is in the LOW state and the test mode is selected via the test terminal, one of the decoder outputs becomes LOW and the other seven decoder outputs become HIGH. This means that one of the test modes will be obtained so that the circuit will be operated in the obtained test mode.

Claims (1)

A test circuit comprising a first MOS transistor and at least one second MOS transistor circuit on the same substrate, wherein the test circuits G ₁ , L ₁ L ₂ ... L _n , DEC and the second MOS transistor circuit External input connection terminals (C ′, S ′, C _O , S ₀ , S ₀ , C ₁ , S ₁ ... C _n , S _n ), and the outputs of the test circuit (M, M ₁ , M ₂₎ ... M ₈ ) is coupled to a second MOS transistor circuit, the output of the second MOS transistor circuit is coupled to an external connection terminal, and the test signal is one or more external input connection terminals C ′, C _O , C ₁ .. Is applied to .C _n ) to place the second MOS transistor circuit in test mode, thereby partially or fully testing the second MOS transistor circuit, thereby generating a signal indicative of a malfunction of the second MOS transistor circuit at the output of the second MOS transistor circuit. An integrated MOS transistor device configured to comprise: Root circuit _{(G 1, L 1, L} 2, L 3, DEC) and a 2MOS transistor circuit has more than one external input connection terminals _{(C ', C 0, C} 1 ... C n) in common, wherein The first gate circuit of the test circuit has a first input (C _O ) wave for receiving a test signal having a polarity opposite to that of the normal supply voltage (V _B ), having the same polarity as that of the normal supply voltage but more than that. The first gate circuit G ₁ includes a second input C ₁ for receiving an additional test signal having a large amplitude and an output A, and only when the test signal is received at an input of the first gate circuit. ) Generates an enable signal (E ₁ , E ₂ ... E _n ) at the output (A) and the test signal (I) applied to the input connection terminals (C ₁ , C ₂ , C ₃ ... C _n ). A test circuit for a MOS device, characterized in that ₁ , I ₂ ... I ₃ ...) are supplied to a second circuit to be tested.

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