KR100247221B1 - Test mode activation circuit - Google Patents

Abstract

1. Field of the Invention:

To a semiconductor memory device.

2. Technical Problems to be Solved by the Invention:

And a test mode activation circuit capable of reducing the number of pads of the semiconductor memory device.

3. The point of the solution of the invention

A test mode activation circuit for applying a test enable signal to a test circuit for verifying whether or not the semiconductor memory device operates normally compares a voltage difference between an external signal input through a pad and an internal supply voltage of the semiconductor memory device, A voltage sensing unit for outputting a comparison voltage; And a latch circuit connected to the output terminal of the voltage sensing unit for outputting the test enable signal in response to the comparison voltage in a test mode and outputting the inverted test enable signal in response to a reset signal in a normal operation mode, And a control unit.

4. Important Uses of the Invention

And is suitably used for a semiconductor memory device.

Description

Test mode enable circuit

FIG. 1 is a circuit diagram for entering a test mode according to a conventional technique; FIG.

FIG. 2 is a circuit diagram for entering a test mode according to a first embodiment of the present invention. FIG.

FIG. 3 is a circuit diagram for entering a test mode according to a second embodiment of the present invention. FIG.

FIG. 4 is a circuit diagram for entering a test mode according to a third embodiment of the present invention; FIG.

5 is a timing diagram according to the present invention;

The present invention relates to semiconductor memory devices, and more particularly, to a test mode activation circuit for entering a test mode.

In recent years, according to the trend of high-speed, low-power, and miniaturization of the system, the parts mounted inside thereof are also becoming smaller. Therefore, in the case of a semiconductor integrated circuit, studies for reducing the chip size as much as possible in order to enable high-speed operation, power saving, and productivity increase are ongoing, and further research is ongoing.

As a method for reducing the chip size, there may be a method of minimizing the chip size or optimally reducing the number of other control circuits. However, this method has a physical limitation and can not be reduced to an appropriate level or more. It is necessary to rely a lot on the process of the memory chip in order to minimize the influence of the secondary effect of the memory chip. In this case, however, the size of the pad to be connected by the wire bonding and the external pin necessary for driving the semiconductor memory can not be easily reduced.

FIG. 1 is a test mode activating circuit diagram for outputting a test enable signal used for a redundant cell test by inputting an external signal according to a conventional technique.

Referring to FIG. 1, when the external signal TE inputted through the pad is higher than the internal supply voltage Vint of the semiconductor memory device, the drain terminal of the transistor 101 becomes high level, And outputs a test enable signal Tout for entering the test mode. The pad is a test entry pad for entering the test mode, i.e., for verifying the characteristics. These pads are typically required pads for each memory chip to enter the test mode.

Therefore, an object of the present invention is to provide a test mode activation circuit capable of reducing the number of pads of a semiconductor memory device.

Another object of the present invention is to provide a test mode activating circuit capable of entering a test mode by using a monitoring pad for measuring an existing DC level without using a pad normally used for entering a test mode of a semiconductor memory have.

According to an aspect of the present invention, there is provided a test mode activation circuit for applying a test enable signal to a test circuit for verifying normal operation of a semiconductor memory device, A voltage sensing unit for sensing a voltage difference of an internal supply voltage of the semiconductor memory device and outputting a corresponding comparison voltage; An initialization circuit for initializing a first node to a first level of a predetermined level in response to an external control signal; A test mode enable circuit connected between the first node and an output terminal of the test mode activating circuit, the test mode enable circuit outputting the test enable signal in response to the comparison voltage in a test mode, A latch circuit for outputting an enable signal; And a transfer gate connected between the output terminal of the voltage sensing unit and the first node and transmitting the comparison signal to the first node in response to an output signal of the latch circuit.

Hereinafter, a detailed description of preferred embodiments of the present invention will be given with reference to the accompanying drawings.

It should be noted that the same components and parts of the drawings denote the same reference numerals as far as possible.

FIG. 2 is a test mode activation circuit diagram configured to share a pad for entering a test mode with an existing monitoring pad according to a first embodiment of the present invention.

The present invention is limited to a circuit for outputting a test enable signal Tout for entering the mode when the external signal TE input to the monitoring pad has a voltage level higher than the internal supply voltage.

Referring to FIG. 2, the internal supply voltage generating unit 220 is a circuit used for providing an internal supply voltage of the semiconductor memory device. An inverter 240 for sensing a voltage difference between the internal supply voltage and an external signal provided through the monitoring pad 230 to provide a comparison voltage, an inverter 240 connected to an output terminal of the inverter 240, A data latch 211 connected between the node B and the node C for performing a latch operation; a data latch 211 connected between the output terminal of the inverter 206 and the node B, And a transfer gate 207 made up of a NMOS transistor and a PMOS transistor responding to a signal applied to the NMOS transistor. The inverter 240 comprises the fmotor transistors 202 and 203 and the NMOS transistors 204 and 205. The W (width) / L (length) of the NMOS transistor 204 constituting the inverter 240 is designed to be smaller than that of the PHOS transistor 203 so that the external voltage applied to the monitoring pad 230 is a semiconductor It is used as a voltage sensing circuit that causes node A to go low when the internal supply voltage Vint of the memory device is higher than Vint.

On the other hand, when the voltage level applied to the monitoring pad 230 is lower than the internal supply voltage Vint of the semiconductor memory device, the node A remains at the high level, and thus the test enable signal Tout maintains the low level. That is, operating in the normal operation mode.

The power-up signal PU is a signal for assuring that the internal supply voltages of the semiconductor memory device can have respective voltage levels, and the test mode activation circuit maintains a low level before the normal operation, Level signal to the gate of the NMOS transistor 208 connected to the NMOS transistor 208 so that the node B can be maintained at a low level. On the other hand, when the power-up signal PU becomes a high level, the emmos transistor 208 is turned off and the node B is kept latched to the low level.

When a voltage equal to or higher than the internal voltage Vint of the semiconductor memory device is applied to the monitoring pad 230, the node A becomes a low level and the test enable signal Tout becomes a high level. At this time, the node C is in a latching relationship with the node B through the data latch 211, and the transfer gate 207 is turned off so that the test enable signal continues to be at the high level . ≪ / RTI >

3 is a test mode activation circuit diagram configured to share a test pad and a test pad according to a second embodiment of the present invention. In FIG. 3, a circuit for switching to the normal operation mode is added after entering the test mode.

When a voltage higher than the internal voltage Vint of the semiconductor memory device is applied to the monitoring pad 230, the test operation is started but the voltage applied to the monitoring pad 230 is removed, The test mode is maintained. Therefore, in FIG. 3, a circuit for switching from the test mode to the general operation mode is added using a reset RESET.

2, the NAND gate 302 outputs a signal applied to the node B at a changed level in response to the reset signal RESET, and an inverter 301 connected between the node C and the node B , And performs the above-described latch operation and mode switching by this circuit. When the reset signal RESET is input to one input terminal of the NAND gate 302 at a low level through the inverter 303, the node C becomes a high level and the test enable signal Tout becomes a low level, It is disabled.

FIG. 4 is a test mode activation circuit diagram configured to share a test pad with a monitoring pad according to a third embodiment of the present invention.

FIG. 4 is an embodiment in which the inverter 240 operating as a voltage sensing circuit is replaced with a differential amplifier 250 although it is a circuit having a function similar to that of FIG. In this case, the voltages at both ends of the differential amplifier 250 are an internal supply voltage of the semiconductor memory device and an external voltage applied to the monitoring pad 230. Using the output of the differential amplifier 250, do.

FIG. 5 is a timing diagram according to the present invention.

Referring to FIG. 5, when a voltage higher than the internal supply voltage Vint of the semiconductor memory device is applied to the monitoring pad 230 used as a substitute for the test entry pad for testing purposes from the outside, The voltage must be given a time to assure a latch between the node B and the node C (test entry area), and the actual test will be performed when the pad has its own level (test mode) .

As described above, according to the present invention, there is an advantage that the number of pads of the semiconductor memory device can be reduced. Further, the present invention has an advantage that characteristic verification can be performed without using a test entry pad which is normally included in order to verify characteristics of a semiconductor memory. In addition, the present invention has an advantage of contributing to improvement in productivity in semiconductor production by reducing the size of the semiconductor chip.

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made therein without departing from the spirit and scope of the invention.

Claims (10)

1. A test mode activation circuit for applying a test enable signal to a test circuit for verifying whether a semiconductor memory device is operating normally, the test mode activation circuit comprising: A voltage sensing unit for comparing a voltage difference between an external signal input through a pad and an internal supply voltage of the semiconductor memory device and outputting a corresponding comparison voltage; And outputting the test enable signal in response to the comparison voltage in a test mode and outputting the inverted test enable signal in response to a reset signal in a normal operation mode, An initialization circuit for initializing a first node to a first voltage of a predeterminedlevel in response to an external control signal and an initialization circuit connected between the first node and an output terminal of the test mode activation circuit for switching from the test mode to the normal operation mode And a latch circuit for outputting the inverted test enable signal by the reset signal. The test mode activation circuit according to claim 1, wherein the test mode activation circuit is connected between the first node and an output terminal of the voltage sensing unit, and transmits the comparison signal to the first node in response to an output signal of the latch circuit Further comprising a gate connected to the gate of the test mode activation circuit. 2. The test mode activation circuit of claim 1, wherein the first voltage is a low level voltage. The apparatus of claim 1, wherein the voltage sensing unit comprises an inverter for outputting the comparison voltage at a low level when the external signal having a channel width / channel length different from the internal supply voltage is input, Activation circuit. The test mode activation circuit according to claim 1, wherein the voltage sensing unit comprises a differential amplifier that outputs the comparison voltage with the internal supply voltage and the external signal as two inputs. The test mode activation circuit according to claim 1, wherein the comparison voltage is a low level voltage in the test mode and a high level voltage in the normal operation mode. 2. The test mode activation circuit of claim 1, wherein the pad comprises a monitoring pad. A test mode activation circuit for applying a test enable signal to a test circuit for verifying whether or not the semiconductor memory device is operating normally, the test mode activation circuit comprising: A voltage sensing unit for sensing a voltage difference between an external signal input through the monitoring pad and an internal supply voltage of the semiconductor memory device and outputting a corresponding comparison voltage; An initialization circuit for initializing a first node to a first voltage of a predetermined level in response to an external control signal; A test mode enable circuit connected between the first node and an output terminal of the test mode activating circuit, the test mode enable circuit outputting the test enable signal in response to the comparison voltage in a test mode, A latch circuit for outputting an enable signal; And a transfer gate connected between an output terminal of the voltage sensing unit and the first node and transmitting the comparison signal to the first node in response to an output signal of the latch circuit. 9. The method of claim 8, wherein the voltage sensing unit comprises an inverter for outputting the comparison voltage at a low level when the external signal having a channel width / channel length different from the internal supply voltage is input, Activation circuit. The test mode activating circuit according to claim 9, wherein the voltage detecting unit comprises a differential amplifier for outputting the comparison voltage with the internal supply voltage and the external signal as two inputs.