JPH0982895A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device which is capable of ascertaining that a step-up circuit outputs a prescribed potential or not even after a semiconductor circuit equipped with a step-up circuit in it is packaged. SOLUTION: A step-up judging circuit 3 which judges whether an inner step-up circuit 1 outputs a prescribed potential or not is mounted inside a semiconductor integrated circuit device, wherein the step-up judging circuit 3 outputs the judgment result through an IO pin 9 electrically connected to an IO pad 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having a function of monitoring whether or not an internal potential generating circuit provided inside a chip outputs a predetermined potential. Regarding

[0002]

^2. Description of the Related Art Conventionally, an internal booster circuit for outputting a voltage higher than a power supply voltage is provided in a semiconductor memory such as an E ² PROM. In the case of monitoring the output potential of this type of booster circuit, it was possible to measure or monitor the potential by directly applying a needle to the pad or wiring of the output potential with a tester or the like before housing in the package.

However, when the chip is housed in the package, the output potential of the booster circuit cannot be monitored because there is usually no IO pad directly connected to the booster circuit. That is, once the chip was housed in the package, it was not possible to measure whether the booster circuit was outputting the set potential.

[0004]

As described above, the conventional semiconductor integrated circuit device has a problem that it is impossible to measure whether the internal potential generating circuit outputs the set potential when the chip is housed in the package. It was

An object of the present invention is to provide a semiconductor integrated circuit device capable of monitoring the potential output from the internal potential generating circuit even when it is housed in a package.

[0006]

[Means for Solving the Problems]

(Structure) (1) An internal potential generation circuit that generates a predetermined potential from an external power supply voltage, a potential determination circuit that determines whether the internal potential generation circuit outputs a set potential, and a test mode signal The determination result of the potential determination circuit as IO
A semiconductor integrated circuit device, comprising: a determination result output circuit for outputting to a pad.

(2) The potential determination circuit outputs digital signals corresponding to the case where the output potential of the internal potential generation circuit is higher than the set potential and the case where the output potential is lower than the set potential. It is characterized by doing.

(3) After the semiconductor integrated circuit device is housed in the package, the determination result of the potential determination circuit can be monitored from the IO pin electrically connected to the IO pad.

(4) The internal potential generating circuit is a booster circuit.

(5) The internal potential generating circuit is a step-down circuit.

(Operation) According to the present invention, the potential determining circuit for determining whether or not the internal potential generating circuit is outputting the set potential is provided in the same chip, and the determination result of the potential determining circuit is output to the IO pad. Therefore, even after the chip is housed in the package, it is possible to monitor whether the internal potential generating circuit outputs the set potential from the IO pin electrically connected to the IO pad.

[0012]

1 is a circuit diagram showing the configuration of a semiconductor integrated circuit device according to an embodiment of the present invention. FIG.
FIG. 6 is a waveform diagram showing an operation of the semiconductor integrated circuit device according to the embodiment of the present invention. In FIG. 1, a line output from an internal booster circuit (internal potential generation circuit) 1 is branched to a limiter circuit 2, a boosting determination circuit 3, a transfer gate 4, a flip-flop 5, an inverting transfer circuit 6, an output buffer 7, an IO. Pad 8 is connected in series, and the above circuit
It is mounted on the same chip together with a circuit for realizing a predetermined function. The IO pad 8 is connected to the IO pin 9 of the package while the chip is housed in a package (not shown).

The transfer gate 4 is composed of a p-MOS transistor Q ₁ and an n-MOS transistor Q ₂ connected in parallel with the p-MOS transistor Q ₁ . The gate electrode of the transistor Q ₁ and Q ₂ are adapted to the test mode signal "COM" inputted, particularly to the transistor Q ₁ is adapted to the input signal "COM" via the NOT circuit G ₁ ing. The flip-flop 5 is a NOT circuit G
₂ and a NOT circuit G ₃ connected in parallel therewith. The inverting transfer circuit 6 schematically shows a combination of a NOT circuit and a transfer gate.

Further, "COM" through the NOT circuit G ₄
Signal "RE" to signal and read
And the inverted signal are input to the NOR circuit G _5, and N
The signal output from the OR circuit G ₅ and passing through the NOT circuits G ₆ and G ₇ serves as a switching signal for controlling the operation of the inverting transfer circuit 6. Here, the signal “COM” and the signal “RE”
Are simultaneously input, the inverting transfer circuit 6 operates to invert the signal sent from the flip-flop 5 and transfer it to the output buffer 7. The IO pad 8 is a terminal provided on the substrate for inputting / outputting a data signal to / from the outside. The IO pin 9 is provided on the package, electrically connected to the IO pad 8, and used for inputting / outputting signal data to / from the outside after the substrate is housed in the package.

The semiconductor integrated circuit device of this embodiment has a test mode different from the normal operation when the test mode signal is input, and the operation described below is the test mode when the test mode signal is input. . Internal booster circuit 1
Is operated, the potential V _pp output from the internal booster circuit 1
Is limited by the limiter circuit 2. The boosting determination circuit 3 outputs to the node N ₁ digital data “H” when the limit potential is reached and “L” when the limit potential is not reached. When the command “COM” is input to the transfer gate 4 during the operation of the booster circuit 1, the transfer gate 4 is turned on and the digital data of the booster determination circuit 3 is latched by the flip-flop 5. The determination result latched by the flip-flop 5 is transferred from the inversion transfer circuit 6 to the output buffer 7 at the read enable timing. Then, after the semiconductor integrated circuit device is housed in the package, the determination result can be monitored from the IO pin 9 through the IO pad 8 from the output buffer 7.

By doing so, by inputting a command for monitoring a boosted potential during a write operation or an erase operation for operating the internal booster circuit 1, it is determined whether or not the internally boosted potential has reached the set potential. After being stored in, it can be monitored through the IO pin 9 used for input / output of normal signal data. Since the IO pin 9 is a pad used for inputting / outputting a signal in a normal state, it is not necessary to provide a special output terminal for outputting a determination result at the time of packaging.

Next, an example of the boost determination circuit will be shown. FIG. 3 is a diagram showing the configuration of the boost determination circuit. FIG. 4 is a waveform diagram showing the operation of this boost determination circuit. The boost determination circuit 3 is
The operational amplifier 10, the C-MOS inverter 11, and the NOT circuit G ₈ are connected in series. C-MO
The S inverter 11 includes a p-MOS transistor Q ₃ and an n-
It is composed of a MOS transistor Q _4, and the output of the operational amplifier 10 is used as a switching signal for the transistor Q 4.
It is designed to be input to the gates of ₃ and Q ₄ .

The potential signal V boosted by the internal booster circuit 1
_{The pp} is attenuated at a constant rate by the limiter circuit 2 including a resistance attenuator and output to the node N ₃ , and the limiter circuit 2
The operational amplifier 10 compares the potential output from the node N ₃ with the reference potential. Here, the set potential, which is a desired potential, is set so that the potential value at the node N ₃ attenuated by the limiter circuit 2 and the reference potential of the operational amplifier 10 become substantially equal. Op 10 when higher than the output potentials of the reference potential from the limiter circuit 2 outputs "H", outputs "L" when low node N _4. The analog data thus boosted is converted into digital data by the operational amplifier 10. However, as shown in FIG. 4, the output of the operational amplifier 10 has a poor rise.
Is inputted to the C-MOS inverter 11 to make the rising edge of the output signal sharp. P-MOS transistor Q ₃ is OF when the output of the operational amplifier 10 is "H"
F, n-MOS transistor Q ₄ is turned on and CM
“L” is output from the OS inverter 11. Also when the output of the operational amplifier 10 is "L" is, p-MOS transistor Q ₃ is turned ON, n-MOS transistor Q ₄ is turned ON, the "H" from the C-MOS inverter 11 is outputted. Then, the signal inverted by the inverter 11 is inverted by the NOT circuit G ₈ , and the same digital signal as the output signal of the operational amplifier 10 is output as N ₅ .

The effects of this embodiment are as follows.

By combining the flip-flop 5 and the inverting transfer circuit 6, the judgment result latched by the flip-flop 5 is passed through the inverting transfer circuit 6 when “COM” and “RE” are simultaneously output. It can be transferred to the output buffer 7.

The operational amplifier 10 has a C-MOS inverter 1
By combining 1's, it is possible to make the output signal of the determination result of the operational amplifier 10 rise slowly, into a signal with a quick rise.

(Modification) This embodiment includes the following modifications.

The step-up circuit 1 may be a step-down circuit.

In addition, various modifications can be made without departing from the scope of the present invention.

[0025]

According to the present invention, the potential determination circuit determines whether or not the internal potential generation circuit outputs the set potential even when the semiconductor integrated circuit is housed in the package. IO that electrically connects the result to the IO pad
It can be monitored from the pin.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a waveform diagram showing an operation of the semiconductor integrated circuit according to the embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a boost determination circuit according to an embodiment of the present invention.

FIG. 4 is a waveform diagram showing the operation of the boost determination circuit according to the embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Internal boosting circuit (internal potential generation circuit) 2 ... Limiter circuit 3 ... Boosting determination circuit (potential determination circuit) 4 ... Transfer gate 5 ... Flip-flop 6 ... Inversion transfer circuit 7 ... Output buffer 8 ... IO pad 9 ... IO pin 10 ... operational amplifier 11 ... C-MOS inverter _{Q 1, Q 3 ... p-} MOS transistors _{Q 2, Q 3 ... n-} MOS transistors _{G 1, G 2, G 3} , G 4, G 6, G 7, G 8 ... NOT circuit G ₅ ... NOR circuit

Claims (1)

[Claims] 1. An internal potential generation circuit for generating a predetermined potential from an external power supply voltage, a potential determination circuit for determining whether or not the internal potential generation circuit is outputting a set potential, and a test mode signal according to a test mode signal. A determination result output circuit for outputting the determination result of the potential determination circuit to an IO pad.