JPH05226654A - Etching processing method for tft array - Google Patents
Etching processing method for tft arrayInfo
- Publication number
- JPH05226654A JPH05226654A JP2936092A JP2936092A JPH05226654A JP H05226654 A JPH05226654 A JP H05226654A JP 2936092 A JP2936092 A JP 2936092A JP 2936092 A JP2936092 A JP 2936092A JP H05226654 A JPH05226654 A JP H05226654A
- Authority
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- Japan
- Prior art keywords
- gas
- film
- etching
- plasma
- tft array
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Liquid Crystal (AREA)
- Drying Of Semiconductors (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、例えば薄膜トランジ
スタ（以下、ＴＦＴと略称）を用いたアクティブマトリ
クス型液晶表示素子の製造に用いられるＴＦＴアレイの
エッチング加工方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of etching a TFT array used for manufacturing an active matrix type liquid crystal display device using, for example, a thin film transistor (hereinafter abbreviated as TFT).
【０００２】[0002]
【従来の技術】近年、液晶やエレクトロルミネセンス
（ＥＬ）を用いた表示装置として、テレビ表示やグラフ
ィックディスプレイ等を指向した大容量、高密度のアク
ティブマトリクス方式の開発，実用化が盛んである。こ
のようなアクティブマトリクス方式は、マトリクス状に
配置した電極の交点に画素に接続したスイッチング素子
を設ける方式である。このアクティブマトリクス方式の
うちＴＦＴ型は、特に開発研究が活発に行なわれてい
る。そして、ＴＦＴをガラス基板に配設したものを一方
の基板とするものは、例えばIEEE Trans. on Electron
Devices 第20巻995 〜1001頁(1973 年) に詳細に記載さ
れている。2. Description of the Related Art In recent years, as a display device using liquid crystal or electroluminescence (EL), a large-capacity, high-density active matrix system for television displays and graphic displays has been developed and put into practical use. Such an active matrix system is a system in which switching elements connected to pixels are provided at the intersections of electrodes arranged in a matrix. Among the active matrix systems, the TFT type is under active development and research. And, the one in which the TFT is arranged on the glass substrate is used as, for example, the IEEE Trans. On Electron.
It is described in detail in Devices Vol. 20, pp. 995-1001 (1973).
【０００３】このようなＴＦＴアレイ基板を製作する工
程は、先ず、例えばガラスのような絶縁基板を前面ガラ
ス基板として、その上に走査電極線とゲ−ト電極を同時
に形成し、その上にゲ−ト絶縁膜，半導体膜，半導体保
護膜を順次形成する。次に、低抵抗半導体膜を成膜し、
半導体膜と低抵抗半導体膜を同時に成形する。その後、
画素電極の形成、電極パット上のゲ−ト絶縁膜の除去を
行ない、信号電極およびソ−ス電極、ドレイン電極を形
成する。このままではソ−ス電極とドレイン電極は低抵
抗半導体膜により短絡しているので、半導体保護膜上の
低抵抗半導体膜をソ−ス電極とドレイン電極をマスクと
して除去する。最後に、ＴＦＴアレイ基板を保護するた
めに絶縁膜を形成する。In the process of manufacturing such a TFT array substrate, first, an insulating substrate such as glass is used as a front glass substrate, a scan electrode line and a gate electrode are simultaneously formed on the front glass substrate, and a gate electrode is formed thereon. -The insulating film, the semiconductor film, and the semiconductor protective film are sequentially formed. Next, a low resistance semiconductor film is formed,
A semiconductor film and a low resistance semiconductor film are simultaneously formed. afterwards,
The pixel electrode is formed and the gate insulating film on the electrode pad is removed to form a signal electrode, a source electrode and a drain electrode. As it is, the source electrode and the drain electrode are short-circuited by the low-resistance semiconductor film, so the low-resistance semiconductor film on the semiconductor protective film is removed using the source electrode and the drain electrode as a mask. Finally, an insulating film is formed to protect the TFT array substrate.
【０００４】アクティブマトリクス型液晶表示装置の組
み立てに当たっては、上記のようなＴＦＴアレイ基板を
前面ガラス基板とし、表面に非画素電極部分からの透過
光およびＴＦＴへの入射光を遮蔽するためのブラックマ
トリクスと呼ばれる遮光膜と透明な対向電極として例え
ばインジウム・錫酸化膜（ＩＴＯ）を形成したガラス基
板を後面ガラス基板とする。前面ガラス基板のＴＦＴ形
成後と後面ガラス基板の対向電極側にそれぞれ液晶配向
膜を塗布し、例えばラビングにより配向処理を施した表
面をそれぞれ内側として、前面ガラス基板と後面ガラス
基板をほぼ１０μｍ離して平行に対向させて貼り合わ
せ、その間に液晶を封入し液晶セルを構成する。更に、
このようにして製造した液晶セルに外部回路を接続した
後、ケ−スに収納する。In assembling an active matrix type liquid crystal display device, the TFT array substrate as described above is used as a front glass substrate, and a black matrix for blocking the transmitted light from the non-pixel electrode portion and the incident light to the TFT on the surface. A glass substrate on which a light-shielding film called "indium tin oxide film (ITO)" is formed as a transparent counter electrode is used as a rear glass substrate. After forming the TFT on the front glass substrate and applying a liquid crystal alignment film to the opposite electrode side of the rear glass substrate respectively, the front glass substrate and the rear glass substrate are separated by about 10 μm with the surfaces subjected to the alignment treatment by rubbing, for example, inside. A liquid crystal cell is constructed by enclosing the liquid crystal in parallel while facing each other and bonding them together. Furthermore,
After connecting an external circuit to the liquid crystal cell manufactured in this manner, it is housed in a case.
【０００５】[0005]
【発明が解決しようとする課題】上記のような液晶表示
装置の製造工程、特にＴＦＴアレイの製造工程におい
て、半導体保護膜上の低抵抗半導体膜を除去する工程
は、アレイの特性に与える影響が大きい。半導体保護膜
の性能を損なうことなく、低抵抗半導体膜を選択的にエ
ッチング出来ることが必要である。低抵抗半導体膜に
は、Ｐ（燐）もしくはＢ（ボロン）などをド−プしたｎ
型半導体もしくはｐ型半導体が用いられる。半導体材料
としては、Ｓｉを母材としたｐｏｌｙ−Ｓｉもしくはａ
−Ｓｉが用いられる。又、半導体保護膜にはＳｉＮｘ
（窒化シリコン）とか、ＳｉＯｘ（シリコン酸化膜）が
使用される場合が多い。このエッチング加工方法として
は、プラズマを用いたプラズマエッチング技術が用いら
れる。In the manufacturing process of the liquid crystal display device as described above, particularly the manufacturing process of the TFT array, the process of removing the low resistance semiconductor film on the semiconductor protective film has an influence on the characteristics of the array. large. It is necessary that the low resistance semiconductor film can be selectively etched without impairing the performance of the semiconductor protective film. The low resistance semiconductor film is doped with P (phosphorus) or B (boron) or the like.
Type semiconductor or p-type semiconductor is used. As a semiconductor material, poly-Si having a base material of Si or a
-Si is used. Further, SiNx is used for the semiconductor protective film.
In many cases, (silicon nitride) or SiOx (silicon oxide film) is used. As this etching method, a plasma etching technique using plasma is used.
【０００６】例えば低抵抗半導体膜としてｎ′型のａ−
Ｓｉを用いた液晶表示装置の場合、ｎ′ａ−Ｓｉと半導
体保護膜との選択比が十分大きくないと、エッチング速
度むら、膜厚のむら等、薄膜形成、あるいはパタ−ン成
形工程で通常起こる変動を吸収する必要がある。特に、
液晶表示装置が大形の場合、使用する基板も大形化する
ため、量産性を加味したプロセスマ−ジンを得るうえで
もこの要請は必須である。For example, as the low resistance semiconductor film, an n'-type a-
In the case of a liquid crystal display device using Si, unless the selection ratio of n'a-Si and the semiconductor protective film is sufficiently large, the etching rate unevenness, the film thickness unevenness, etc. usually occur in the thin film formation or the pattern forming process. It is necessary to absorb fluctuations. In particular,
When the liquid crystal display device is large, the size of the substrate to be used is also large, and this requirement is indispensable for obtaining a process margin taking mass productivity into consideration.
【０００７】現在、エッチング方法としてフロン単独，
フロン＋酸素，ＳＦ6 ＋フロン等の組み合わせが知られ
ているが、これらの組み合わせで得られる選択比は文献
等により最大で３〜６と報告されている。液晶表示装置
のうち特に大形基板を使用する場合、この程度の選択比
では、工程のバラツキを吸収して、むらのない画質，満
足なＴＦＴ特性を得るには十分でなく、成膜工程，エッ
チング工程の均一性の向上と装置改良に過大な負担を強
いている。又、フロンレスのエッチング方法としてＳＦ
6 ＋Ｃｌ2 ガスを主体にしたプラズマ中でのエッチング
も試みたが、選択比は〜６程度である。At present, CFC alone is used as an etching method.
Freon + oxygen, combinations such as SF 6 + Freon is known, selection ratio obtained with these combinations has been reported to 3-6 at the maximum by the literature. Especially when using a large-sized substrate in a liquid crystal display device, such a selection ratio is not sufficient to absorb process variations and obtain uniform image quality and satisfactory TFT characteristics. It imposes an excessive burden on improving the uniformity of the etching process and improving the equipment. In addition, SF is used as a CFC-less etching method.
The etching in plasma mainly composed of 6 + Cl 2 gas was also tried, but the selection ratio is about -6.
【０００８】この発明は、上記事情に鑑みなされたもの
で、半導体膜と他の絶縁膜との十分なエッチング選択比
が得られ、成膜工程，エッチング装置に固有と考えられ
た局部的なむらが解消され、画質が大幅に改良出来るＴ
ＦＴアレイのエッチング加工方法を提供することを目的
とする。The present invention has been made in view of the above circumstances, and it is possible to obtain a sufficient etching selection ratio between a semiconductor film and another insulating film, and it is considered that the local unevenness is considered to be peculiar to the film forming process and the etching apparatus. Can be eliminated and the image quality can be improved significantly.
An object of the present invention is to provide a method for etching an FT array.
【０００９】[0009]
【課題を解決するための手段】この発明は、チャンバ−
内で、プラズマ中で弗素イオン又は弗素ラジカルを形成
するガスとしてＳＦ6 を使用し、更に他のガスとして組
成の中に塩素又は臭素を含むガスを少なくとも有する混
合ガスのプラズマを用いて硅素薄膜と窒化硅素薄膜との
選択エッチングを行なうＴＦＴアレイのエッチング加工
方法において、上記ＳＦ6 の単位時間当たりの流量を上
記チャンバ−の体積の０．００１７以下とし、且つ全ガ
ス圧力を１５Ｐａ以上とするＴＦＴアレイのエッチング
加工方法である。SUMMARY OF THE INVENTION The present invention is directed to a chamber-
In the above, SF 6 is used as a gas that forms fluorine ions or fluorine radicals in plasma, and a mixed gas plasma containing at least a gas containing chlorine or bromine in the composition is used as another gas to form a silicon thin film. In a method of etching a TFT array for performing selective etching with a silicon nitride thin film, a TFT array in which the flow rate of SF 6 per unit time is 0.0017 or less of the volume of the chamber and the total gas pressure is 15 Pa or more. Is an etching method.
【００１０】[0010]
【作用】この発明によれば、プラズマ中で弗素イオン又
は弗素ラジカルを形成するガスとしてＳＦ6 を使用し、
これに等量のＣｌ2 を混合して使用した場合、ＳＦ6 の
単位時間当たりの流量（以下、単に流量又はＳＣＣＭで
表す）をチャンバ−の体積の０．００１７以下とし、全
ガス圧力を１５Ｐａ以上でａ−ＳｉとＳｉＮｘの選択エ
ッチングを行なうと、１０以上の選択比が容易に得られ
る。そして、混合するＣｌ2 の量が例えば１／３〜３倍
の間で変化しても、１０以上の選択比が容易に得られ
る。又、これにキャリアガスとしてＡｒ，Ｈｅ，Ｎ２０
を添加しても良い。例えば、チャンバ−の体積が９リッ
トルの平行平板電極を備えた容量結合型の装置を用い、
カソ−ド電極には１３．５６ＭＨｚの高周波を印加し
た。According to the present invention, SF 6 is used as a gas for forming fluorine ions or fluorine radicals in plasma,
When an equal amount of Cl 2 is mixed and used, the flow rate of SF 6 per unit time (hereinafter, simply referred to as flow rate or SCCM) is 0.0017 or less of the volume of the chamber, and the total gas pressure is 15 Pa. When selective etching of a-Si and SiNx is performed as described above, a selection ratio of 10 or more can be easily obtained. Then, even if the amount of Cl 2 to be mixed changes, for example, between 1/3 and 3 times, a selection ratio of 10 or more can be easily obtained. In addition, Ar, He, N20 as carrier gas
May be added. For example, using a capacitively coupled device equipped with parallel plate electrodes having a chamber volume of 9 liters,
A high frequency of 13.56 MHz was applied to the cathode electrode.
【００１１】ＳＦ6 の流量が１５ＳＣＣＭ、ト−タル圧
力が１０Ｐａの場合、ａ−Ｓｉ／ＳｉＮｘの選択比は４
〜５が得られる。上記と同じ条件でゲ−トバルブで圧力
を２０Ｐａにすると、選択比は１５が得られた。この
時、ａ−Ｓｉのエッチング速度は殆ど変化しないが、Ｓ
ｉＮｘのエッチング速度が大幅に低下している。When the flow rate of SF 6 is 15 SCCM and the total pressure is 10 Pa, the selection ratio of a-Si / SiNx is 4
~ 5 is obtained. When the pressure was set to 20 Pa with the gate valve under the same conditions as above, a selection ratio of 15 was obtained. At this time, the etching rate of a-Si hardly changes, but S
The etching rate of iNx is significantly reduced.
【００１２】ＳＦ6 の流量が２０ＳＣＣＭ、ト−タル圧
力が１０Ｐａの場合、ａ−Ｓｉ／ＳｉＮｘの選択比は４
〜５が得られる。上記と同じ条件でゲ−トバルブで圧力
を２０Ｐａにしても、選択比は４〜５しか得られない。When the flow rate of SF 6 is 20 SCCM and the total pressure is 10 Pa, the selection ratio of a-Si / SiNx is 4
~ 5 is obtained. Even if the pressure is 20 Pa with the gate valve under the same conditions as described above, the selection ratio is only 4 to 5.
【００１３】ＳＦ6 の流量が１５ＳＣＣＭ、ト−タル圧
力が２０〜５０Ｐａの場合、ａ−Ｓｉ／ＳｉＮｘの選択
比は１０〜２０が得られた。５０Ｐａ以上になるとａ−
Ｓｉのエッチング速度が急速に低下し、１０以上の選択
比が得られなくなる。When the flow rate of SF 6 was 15 SCCM and the total pressure was 20 to 50 Pa, the selection ratio of a-Si / SiNx was 10 to 20. A-when the pressure exceeds 50 Pa
The etching rate of Si rapidly decreases, and a selectivity ratio of 10 or more cannot be obtained.
【００１４】上記のエッチングでＳＦ6 の条件の外に、
これに等量のＣｌ2 、キャリアガスを混合している。Ｓ
Ｆ6 の流量が５ＳＣＣＭの場合でも、圧力条件が上記の
条件の場合、同じような結果が得られる。In addition to the SF 6 condition by the above etching,
An equal amount of Cl 2 and a carrier gas are mixed with this. S
Similar results are obtained even when the flow rate of F 6 is 5 SCCM when the pressure condition is the above-mentioned condition.
【００１５】又、Ｃｌ2 の代わりにＢｒ2 ，ＢＣｌ3 ，
ＨＣｌ，ＨＢｒ，Ｃ2 ＨＣｌ2 Ｆ3を添加しても良い。
ＳｉＮｘの代わりにＳｉＯｘを使用すると、ＳｉＮｘの
場合よりも更に高い選択比が得られる。このような結果
は、同じようにプラズマ中で弗素イオン又は弗素ラジカ
ルを形成するＣＦ4 にＣｌ2 を混合して使用した場合に
は得られない。Further, instead of Cl 2 , Br 2 , BCl 3 ,
HCl, HBr, C 2 HCl 2 F 3 may be added.
The use of SiOx instead of SiNx gives a much higher selectivity than that of SiNx. Such a result cannot be obtained when CF 4 which similarly forms fluorine ions or fluorine radicals in plasma is mixed with Cl 2 .
【００１６】以上述べたように、ＳＦ6 の流量と圧力と
の関係が極めて狭い範囲においてのみ成り立ち、他の弗
素系ガスでは見られない特性であり、この条件内では極
めて再現性が良いので、ＴＦＴアレイの製造において非
常に有用な技術を提供出来る。As described above, the relationship between the flow rate of SF 6 and the pressure is established only in an extremely narrow range, and it is a characteristic that cannot be found in other fluorine-based gases. Under these conditions, reproducibility is very good, It is possible to provide a very useful technique in manufacturing a TFT array.
【００１７】[0017]
【実施例】以下、図面を参照して、この発明の一実施例
を詳細に説明する。図１は、この発明の一実施例を用い
て形成したＴＦＴアレイ基板の一部を示す概略断面図で
あり、製造工程に従って述べることにする。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a schematic sectional view showing a part of a TFT array substrate formed by using one embodiment of the present invention, which will be described according to the manufacturing process.
【００１８】先ず、ガラス基板１上に、例えばモリブデ
ン・タンタル合金薄膜をスパッタ法などにより約０．２
μｍ形成し、ホトリソグラフィ法によりストライプ状の
走査電極線と走査電極に電気的に接続しているゲ−ト電
極２のパタ−ンを形成する。次に、例えばプラズマ化学
気相成長（以下、化学気相成長をＣＶＤと略称）法など
によりゲ−ト絶縁膜３として例えば０．３μｍの窒化硅
素（ＳｉＮｘ）と、半導体膜４として膜厚０．１μｍの
非晶質硅素（ａ−Ｓｉ）と半導体保護膜５として約０．
３μｍの窒化硅素を連続して堆積し、ホトリソグラフィ
法によりゲ−ト電極２の上方に半導体保護膜５を成形す
る。First, for example, a molybdenum-tantalum alloy thin film is formed on the glass substrate 1 by a sputtering method to a thickness of about 0.2.
Then, the stripe-shaped scanning electrode lines and the pattern of the gate electrodes 2 electrically connected to the scanning electrodes are formed by photolithography. Next, for example, a silicon nitride (SiNx) film having a thickness of 0.3 μm as the gate insulating film 3 and a semiconductor film 4 having a thickness of 0 are formed by, for example, a plasma chemical vapor deposition (hereinafter, chemical vapor deposition is abbreviated as CVD) method. 1 μm of amorphous silicon (a-Si) and the semiconductor protective film 5 having a thickness of about 0.
3 μm of silicon nitride is continuously deposited, and the semiconductor protective film 5 is formed above the gate electrode 2 by photolithography.
【００１９】次に、例えばプラズマＣＶＤ法によりｎ′
ａ−Ｓｉよりなる低抵抗半導体膜６を成膜し、ホトリソ
グラフィ法により半導体膜４および低抵抗半導体膜６を
同時に成形する。Next, for example, by the plasma CVD method, n '
A low resistance semiconductor film 6 made of a-Si is formed, and the semiconductor film 4 and the low resistance semiconductor film 6 are simultaneously formed by photolithography.
【００２０】次に、外部と電気的な接続が必要な部分、
例えば電極パット上のゲ−ト絶縁膜３をホトリソグラフ
ィ法により除去しておく。次に、例えばＩＴＯをスパッ
タ法で約０．１μｍ堆積させ、ホトリソグラフィ法によ
り画素電極７を形成する。Next, a portion that needs to be electrically connected to the outside,
For example, the gate insulating film 3 on the electrode pad is removed by photolithography. Next, for example, ITO is deposited to a thickness of about 0.1 μm by the sputtering method, and the pixel electrode 7 is formed by the photolithography method.
【００２１】次に、例えば０．０５μｍのＭｏと約１．
０μｍのＡｌをスパッタリング法などで堆積し、ホトリ
ソグラフィ法により信号電極線とこの信号電極線に電気
的に接続しているドレイン電極８とソ−ス電極９を同時
に成形する。Next, for example, Mo of 0.05 μm and about 1.
Al of 0 μm is deposited by a sputtering method or the like, and the signal electrode line and the drain electrode 8 and the source electrode 9 electrically connected to this signal electrode line are simultaneously formed by the photolithography method.
【００２２】次に、ドレイン電極８とソ−ス電極９をマ
スクとして、低抵抗半導体膜６のプラズマエッチングを
行なう。使用したエッチング装置は、チャンバ−内に平
行平板電極を備えた容量結合型で、カソ−ド電極には１
３．５６ＭＨｚの高周波を印加した。使用したガスは、
チャンバ−の体積に対し、ＳＦ6 を０．１７％，これと
等量のＣｌ2 ガス、キャリヤ−ガスとしてＡｒをＳＦ6
の２倍量添加した混合ガスで、圧力を２０Ｐａとした。
ｎ′ａ−Ｓｉよりなる低抵抗半導体膜６のエッチング速
度は１５００〜２０００オングストロ−ムが得られた。
モニタ−として入れたＳｉＮｘ膜のエッチング速度は１
００〜１５０オングストロ−ムであった。Next, the low resistance semiconductor film 6 is plasma-etched using the drain electrode 8 and the source electrode 9 as a mask. The etching equipment used was a capacitively coupled type with parallel plate electrodes inside the chamber, and the cathode electrode was 1
A high frequency of 3.56 MHz was applied. The gas used is
Chamber - to the volume, the SF 6 0.17%, which an equivalent amount of Cl 2 gas, carrier - Ar as gas SF 6
The pressure was set to 20 Pa with a mixed gas added in an amount twice that of the above.
The etching rate of the low resistance semiconductor film 6 made of n'a-Si was 1500 to 2000 angstroms.
The etching rate of the SiNx film inserted as a monitor is 1
It was from 00 to 150 angstrom.
【００２３】次に、例えばＳｉＮｘのような絶縁膜１０
を全面ガラス基板１上に約０．１μｍから１．０μｍの
厚さで堆積し、ホトリソグラフィ法により電気的に接続
が必要な部分の絶縁膜１０を取り除いておく。こうして
ＴＦＴアレイ基板が完成する。Next, for example, an insulating film 10 such as SiNx.
Is deposited on the entire surface of the glass substrate 1 to a thickness of about 0.1 μm to 1.0 μm, and the insulating film 10 in a portion that needs to be electrically connected is removed by photolithography. Thus, the TFT array substrate is completed.
【００２４】さて図２は、図１に示したＴＦＴアレイ基
板を用いて作成した液晶表示装置を示す断面図である。
この図２において、ガラス基板１１上にはＴＦＴアレイ
基板のＴＦＴと対向させる位置に、例えばＣｒからなる
遮光膜１２と例えばＩＴＯからなる対向電極１３を形成
する。FIG. 2 is a sectional view showing a liquid crystal display device produced using the TFT array substrate shown in FIG.
In FIG. 2, a light shielding film 12 made of, for example, Cr and a counter electrode 13 made of, for example, ITO are formed on the glass substrate 11 at positions facing the TFTs of the TFT array substrate.
【００２５】次に、ガラス基板１とガラス基板１１にそ
れぞれ配向膜１４を塗布した後、例えばラビングにより
配向処理を行なう。続いて、配向処理を施した表面を互
いに内側として、２枚のガラス基板１，１１をほぼ１０
μｍ離して平行に対向させて周囲を封着し、間隙に液晶
１５を封入する。Next, the glass substrate 1 and the glass substrate 11 are each coated with an alignment film 14, and then an alignment treatment is performed by, for example, rubbing. Then, the two glass substrates 1 and 11 are set to approximately 10 with the surfaces subjected to the alignment treatment being inside each other.
The liquid crystal 15 is sealed in the gap by facing each other in parallel and separated by μm.
【００２６】このようにして液晶セルを完成し、出画評
価した結果、成膜工程、エッチング装置に固有と考えら
れていた局部的な特性むらが解消され、画質が大幅に改
良されて、良好な結果を得た。As a result of completing the liquid crystal cell in this way and evaluating the image output, local characteristic unevenness, which was considered to be peculiar to the film forming process and the etching apparatus, was eliminated, the image quality was greatly improved, and it was excellent. I got good results.
【００２７】[0027]
【発明の効果】以上詳述したように、この発明によれ
ば、ＳＦ6 の単位時間当たりの流量をチャンバ−の体積
の０．００１７以下とし、且つ全ガス圧力を１５Ｐａ以
上とすることにより、半導体膜と他の絶縁膜との十分な
エッチング選択比が得られる。As described in detail above, according to the present invention, the flow rate of SF 6 per unit time is 0.0017 or less of the volume of the chamber, and the total gas pressure is 15 Pa or more. A sufficient etching selection ratio between the semiconductor film and another insulating film can be obtained.
【００２８】この発明のエッチング方法をアクティブマ
トリックス型液晶表示装置のＴＦＴアレイ製造工程に適
用することにより、成膜工程，エッチング装置に固有と
考えられた局部的なむらが解消され、画質が大幅に改良
出来た。By applying the etching method of the present invention to the TFT array manufacturing process of the active matrix type liquid crystal display device, the local unevenness considered to be peculiar to the film forming process and the etching device is eliminated, and the image quality is significantly improved. I could improve.
【図１】この発明の一実施例を用いて作成したＴＦＴア
レイ基板を示す断面図。FIG. 1 is a cross-sectional view showing a TFT array substrate manufactured by using an embodiment of the present invention.
【図２】図１のＴＦＴアレイ基板を用いて作成したアク
ティブマトリクス型液晶表示装置を示す断面図。FIG. 2 is a cross-sectional view showing an active matrix type liquid crystal display device produced using the TFT array substrate of FIG.
１…ガラス基板、２…ゲ−ト電極、３…ゲ−ト絶縁膜、
４…半導体膜、５…半導体保護膜、６…低抵抗半導体
膜、７…画素電極、８…ドレイン電極、９…ソ−ス電
極、１０…絶縁膜。1 ... Glass substrate, 2 ... Gate electrode, 3 ... Gate insulating film,
4 ... Semiconductor film, 5 ... Semiconductor protective film, 6 ... Low resistance semiconductor film, 7 ... Pixel electrode, 8 ... Drain electrode, 9 ... Source electrode, 10 ... Insulating film.
Claims (1)
ン又は弗素ラジカルを形成するガスとしてＳＦ6 を使用
し、更に他のガスとして組成の中に塩素又は臭素を含む
ガスを少なくとも有する混合ガスのプラズマを用いて硅
素薄膜と窒化硅素薄膜との選択エッチングを行なうＴＦ
Ｔアレイのエッチング加工方法において、 上記ＳＦ6 の単位時間当たりの流量を上記チャンバ−の
体積の０．００１７以下とし、且つ全ガス圧力を１５Ｐ
ａ以上とすることを特徴とするＴＦＴアレイのエッチン
グ加工方法。1. A mixed gas containing SF 6 as a gas for forming fluorine ions or fluorine radicals in plasma in a chamber and further containing at least a gas containing chlorine or bromine in its composition as another gas. TF for selective etching of silicon thin film and silicon nitride thin film using plasma
In the T array etching method, the flow rate of SF 6 per unit time is 0.0017 or less of the volume of the chamber, and the total gas pressure is 15 P.
A method of etching a TFT array, which is a or more.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2936092A JPH05226654A (en) | 1992-02-17 | 1992-02-17 | Etching processing method for tft array |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2936092A JPH05226654A (en) | 1992-02-17 | 1992-02-17 | Etching processing method for tft array |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05226654A true JPH05226654A (en) | 1993-09-03 |
Family
ID=12274022
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2936092A Pending JPH05226654A (en) | 1992-02-17 | 1992-02-17 | Etching processing method for tft array |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05226654A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5728608A (en) * | 1995-10-11 | 1998-03-17 | Applied Komatsu Technology, Inc. | Tapered dielectric etch in semiconductor devices |
| KR19990075407A (en) * | 1998-03-20 | 1999-10-15 | 윤종용 | Method of manufacturing thin film transistor substrate |
| KR20000039663A (en) * | 1998-12-15 | 2000-07-05 | 김영환 | Method for manufacturing thin film transistor liquid crystal display device |
| US6372535B1 (en) | 1998-02-02 | 2002-04-16 | Samsung Electronics Co., Ltd. | Manufacturing method of a thin film transistor |
| JP2005513785A (en) * | 2001-12-17 | 2005-05-12 | サムスン エレクトロニクス カンパニー リミテッド | Thin film transistor manufacturing method using polycrystalline silicon |
| KR100663291B1 (en) * | 2000-12-20 | 2007-01-02 | 비오이 하이디스 테크놀로지 주식회사 | Method of manufacturing thin film transistor lcd |
| KR100705615B1 (en) * | 2000-12-30 | 2007-04-11 | 비오이 하이디스 테크놀로지 주식회사 | Method for fabricating tft lcd |
| CN100449737C (en) * | 2006-02-28 | 2009-01-07 | 友达光电股份有限公司 | Film transistor array substrate and its manufacturing method |
| JP2010073935A (en) * | 2008-09-19 | 2010-04-02 | Casio Computer Co Ltd | Method of dry etching silicon compound film |
-
1992
- 1992-02-17 JP JP2936092A patent/JPH05226654A/en active Pending
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5895937A (en) * | 1995-10-11 | 1999-04-20 | Applied Komatsu Technology, Inc. | Tapered dielectric etch in semiconductor devices |
| US5728608A (en) * | 1995-10-11 | 1998-03-17 | Applied Komatsu Technology, Inc. | Tapered dielectric etch in semiconductor devices |
| US6372535B1 (en) | 1998-02-02 | 2002-04-16 | Samsung Electronics Co., Ltd. | Manufacturing method of a thin film transistor |
| KR19990075407A (en) * | 1998-03-20 | 1999-10-15 | 윤종용 | Method of manufacturing thin film transistor substrate |
| US6495383B2 (en) | 1998-09-03 | 2002-12-17 | Samsung Electronics Co., Ltd. | Manufacturing method of a thin film transistor |
| KR20000039663A (en) * | 1998-12-15 | 2000-07-05 | 김영환 | Method for manufacturing thin film transistor liquid crystal display device |
| KR100663291B1 (en) * | 2000-12-20 | 2007-01-02 | 비오이 하이디스 테크놀로지 주식회사 | Method of manufacturing thin film transistor lcd |
| KR100705615B1 (en) * | 2000-12-30 | 2007-04-11 | 비오이 하이디스 테크놀로지 주식회사 | Method for fabricating tft lcd |
| JP2005513785A (en) * | 2001-12-17 | 2005-05-12 | サムスン エレクトロニクス カンパニー リミテッド | Thin film transistor manufacturing method using polycrystalline silicon |
| US7229860B2 (en) | 2001-12-17 | 2007-06-12 | Samsung Electronics Co., Ltd. | Method for manufacturing a thin film transistor using poly silicon |
| CN100449737C (en) * | 2006-02-28 | 2009-01-07 | 友达光电股份有限公司 | Film transistor array substrate and its manufacturing method |
| JP2010073935A (en) * | 2008-09-19 | 2010-04-02 | Casio Computer Co Ltd | Method of dry etching silicon compound film |
| JP4596287B2 (en) * | 2008-09-19 | 2010-12-08 | カシオ計算機株式会社 | Method for dry etching of a film containing silicon |
| KR101153679B1 (en) * | 2008-09-19 | 2012-06-18 | 가시오게산키 가부시키가이샤 | Dry etching method of film containing silicon |
| US8394686B2 (en) | 2008-09-19 | 2013-03-12 | Casio Computer Co., Ltd. | Dry etching method of silicon compound film |
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