KR20000003110A - Method of forming a thin film transistor liquid crystal display - Google Patents
Method of forming a thin film transistor liquid crystal display Download PDFInfo
- Publication number
- KR20000003110A KR20000003110A KR1019980024222A KR19980024222A KR20000003110A KR 20000003110 A KR20000003110 A KR 20000003110A KR 1019980024222 A KR1019980024222 A KR 1019980024222A KR 19980024222 A KR19980024222 A KR 19980024222A KR 20000003110 A KR20000003110 A KR 20000003110A
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- ito
- film
- thin film
- film transistor
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
Abstract
Description
본 발명은 박막 트랜지스터 액정표시소자의 제조방법에 관한 것으로, 보다 상세하게는, ITO 금속막의 막 특성을 향상시킬 수 있는 박막 트랜지스터 액정표시소자의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a thin film transistor liquid crystal display device, and more particularly, to a method for manufacturing a thin film transistor liquid crystal display device capable of improving the film characteristics of an ITO metal film.
일반적으로, 액정표시소자(Liquid Crystal Display : 이하, LCD)는 텔레비젼 및 그래픽 디스플레이 등의 표시장치에 이용된다. 특히, 매트릭스 형태로 배열된 각 화소마다 박막 트랜지스터(Thin Film Transistor : 이하, TFT)와 같은 스위칭 소자가 구비되는 액티브 매트릭스형 LCD는 고속 응답 특성을 갖는 잇점과 고화소수에 적합한 잇점 때문에 통상의 디스플레이 장치인 CRT(Cathode Ray Tube)에 필적할만한 표시 화면의 고화질화 및 대형화, 컬러화 등을 실현하고 있다.In general, liquid crystal displays (hereinafter, LCDs) are used in display devices such as televisions and graphic displays. In particular, an active matrix LCD having a switching element such as a thin film transistor (TFT) for each pixel arranged in a matrix form has a high speed response characteristic and a suitable display for a high pixel number. A display screen that is comparable to a CRT (Cathode Ray Tube) is realized in high quality, large size, and color.
이러한 TFT LCD는 통상 TFT 어레이가 형성된 하부기판과, 컬러화를 실현하기 위한 컬러필터가 형성된 상부기판이 소정 간격을 두고 합착되며, 상기 하부기판과 상부기판 사이의 공간에는 액정이 봉입된 형태를 이루고 있다.In such a TFT LCD, a lower substrate on which a TFT array is formed and an upper substrate on which a color filter for realizing color is formed are bonded at predetermined intervals, and a liquid crystal is enclosed in a space between the lower substrate and the upper substrate. .
도 1 은 종래 기술에 따른 TFT LCD의 하부기판을 도시한 단면도로서, 도시된 바와 같이, 유리기판과 같은 절연기판(1) 상에 게이트 전극(2)이 형성되며, 상기 게이트 전극(2)은 절연기판(1)의 전면에 형성되는 게이트 절연막(3)에 의해 피복된다.FIG. 1 is a cross-sectional view illustrating a lower substrate of a TFT LCD according to the prior art. As illustrated, a gate electrode 2 is formed on an insulating substrate 1 such as a glass substrate, and the gate electrode 2 is It is covered by a gate insulating film 3 formed on the entire surface of the insulating substrate 1.
그리고, 게이트 전극(2) 상부의 게이트 절연막(3) 상에는 패턴의 형태로 반도체층(4)이 형성되며, 이 반도체층(4)의 중심부 상에는 패턴의 형태로 에치 스톱퍼층(5)이 형성되고, 또한, 에치 스톱퍼(5) 및 반도체층(4)의 양측면에는 오믹층(6)이 형성되며, 오믹층(6) 상에는 소오스 및 드레인 전극(7A, 7B)이 형성되어 TFT가 완성된다.The semiconductor layer 4 is formed on the gate insulating film 3 on the gate electrode 2 in the form of a pattern, and the etch stopper layer 5 is formed on the center of the semiconductor layer 4 in the form of a pattern. The ohmic layer 6 is formed on both sides of the etch stopper 5 and the semiconductor layer 4, and the source and drain electrodes 7A and 7B are formed on the ohmic layer 6 to complete the TFT.
게다가, 전체 상부에는 폴리이미드(Polyimide), 레진(Resin) 또는 비씨비(BCB : Benzo Cyclo Butyne) 등의 유기절연막으로 이루어진 보호막(8)이 도포되며, 보호막(8) 상에는 화소영역에 해당하는 부분에 ITO(Indium Tin Oxide) 금속으로된 화소전극(9)이 형성되고, 이때, 화소전극(9)은 보호막(8)에 구비된 콘택홀을 통해 소오스 전극(7A)과 콘택된다.In addition, a protective film 8 made of an organic insulating film such as polyimide, resin, or BCB (Benzo Cyclo Butyne) is coated on the entire surface, and a portion corresponding to a pixel region is applied on the protective film 8. A pixel electrode 9 made of indium tin oxide (ITO) metal is formed on the pixel electrode 9, and the pixel electrode 9 is in contact with the source electrode 7A through a contact hole provided in the passivation layer 8.
상기에서, 보호막은 TFT 어레이 기판, 즉, 하부기판의 평탄화를 확보하기 때문에 후속 공정인 배향막 형성 공정을 용이하게 실시할 수 있게 하며, 아울러, 상·하부기판 간의 셀 갭의 균일성을 향상시키기 때문에 TFT LCD의 표시품위는 향상된다.In the above, since the protective film ensures flattening of the TFT array substrate, that is, the lower substrate, the alignment film forming process, which is a subsequent process, can be easily performed, and the uniformity of the cell gap between the upper and lower substrates is improved. The display quality of the TFT LCD is improved.
그러나, 상기와 같은 종래 TFT LCD는 유기절연막으로된 보호막 상에 무기물인 ITO 금속을 증착하기 때문에 상기 ITO 금속막의 막 특성이 저하되는 것으로 인하여 화소전극을 형성하기 위한 ITO 금속막의 식각시에 식각 균일성이 저하되기 때문에 미세 패턴 형성이 곤란하며, 이로 인하여, TFT LCD의 제조수율이 저하되는 문제점이 있었다.However, in the conventional TFT LCD as described above, since the ITO metal, which is an inorganic material, is deposited on the protective film made of the organic insulating film, the etch uniformity during etching of the ITO metal film for forming the pixel electrode due to the deterioration of the film characteristics of the ITO metal film. Because of this decrease, it is difficult to form a fine pattern, which causes a problem that the manufacturing yield of the TFT LCD is lowered.
자세하게, 종래에는 유기절연막 상에 ITO 금속막을 형성하기 위하여 ITO 금속을 상온 또는 저온에서 증착한 후에 고온 어닐링 공정을 실시하는데, 이러한 방법으로 형성된 ITO 금속막에 대한 식각 공정을 실시할 경우에는 유기절연막과 ITO 금속막의 계면에서의 부조화로 인하여 식각 공정시에 임계 치수를 정확하게 디파인하기가 어려우며, 식각 균일성 및 재현성도 저하된다.In detail, in order to form the ITO metal film on the organic insulating film, a high temperature annealing process is performed after depositing the ITO metal at room temperature or low temperature. In the case of performing the etching process on the ITO metal film formed in this manner, Due to the incompatibility at the interface of the ITO metal film, it is difficult to accurately define the critical dimension during the etching process, and the etching uniformity and reproducibility are also deteriorated.
즉, 이러한 현상은 ITO 공정이 외부 변화에 민감하게 변하기 때문인데, ITO 금속막의 형성시에 ITO의 결정화에 대한 결정요소는 O2압력과 플라즈마 파워 또는 기판 온도 등이며, 한 예로, 기판 온도를 증가시키기 위한 고온 공정에서는 결정 사이즈는 커지나, 결정이 너무 크기 때문에 식각 속도 값이 증가되어 공정 적용이 어렵고, 저온 공정에서는 그 반대로 결정 사이즈가 너무 작은 것에 기인하여 식각 속도 값이 커지게 되어 공정 적용이 어렵게 되기 때문이다.In other words, this phenomenon is because the ITO process is sensitive to external changes, the determinants for the crystallization of ITO during the formation of the ITO metal film is O 2 pressure and plasma power or substrate temperature, for example, increase the substrate temperature In the high temperature process, the crystal size becomes large, but because the crystal is too large, the etch rate value increases, making it difficult to apply the process.In the low temperature process, the etch rate value becomes large due to the too small crystal size. Because it becomes.
또한, 유기절연막 상에서 ITO의 성막 공정을 실시함에 있어서, 고온 공정일 경우에는 유기절연막에서의 사이드 체인인 C, H 성분의 분해가 발생되어 ITO 금속의 성막 분위기를 오염시키게 됨으로써 ITO 금속막의 막 특성이 변화된다. 반면에, 저온 공정일 경우에는 막 성장 매카니즘에서 성장 표면이 유기물일 경우에 ITO 증착이 무기물 상에서와는 상이하게 되며, 이때, 식각 속도가 커져 공정이 어렵게 된다.In the ITO film-forming process on the organic insulating film, in the high temperature process, decomposition of C and H components, which are side chains in the organic insulating film, occurs and contaminates the film-forming atmosphere of the ITO metal. Is changed. On the other hand, in the low temperature process, when the growth surface is an organic material in the film growth mechanism, ITO deposition is different from that of the inorganic material. At this time, the etching rate is increased, which makes the process difficult.
따라서, 본 발명은 상기와 같은 문제점을 해결하기 위하여 안출된 것으로서, 무기물인 ITO 금속막과 유기물인 보호막간의 계면 특성을 향상시킴으로써, ITO 금속막의 미세 패턴 형성을 용이하게 실시할 수 있는 TFT LCD의 제조방법을 제공하는데, 그 목적이 있다.Accordingly, the present invention has been made to solve the above problems, by improving the interfacial properties between the inorganic ITO metal film and the protective film of the organic material, manufacturing a TFT LCD that can easily form a fine pattern of the ITO metal film To provide a method, the purpose is.
도 1 은 종래 기술에 따른 박막 트랜지스터 액정표시소자의 제조방법을 설명하기 위한 단면도.1 is a cross-sectional view for explaining a method for manufacturing a thin film transistor liquid crystal display device according to the prior art.
도 2a 및 도 2b는 본 발명의 실시예에 따른 박막 트랜지스터 액정표시소자의 제조방법을 설명하기 위한 공정 단면도.2A and 2B are cross-sectional views illustrating a method of manufacturing a thin film transistor liquid crystal display device according to an exemplary embodiment of the present invention.
(도면의 주요 부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)
20 : 절연기판 22 : 레진막20: insulating substrate 22: resin film
23 : 무기물층 24 : 화소전극23 inorganic layer 24 pixel electrode
상기와 같은 목적을 달성하기 위한 본 발명의 TFT LCD의 제조방법은, 상부면에 박막 트랜지스터가 형성된 절연기판을 제공하는 단계; 상기 절연기판 전면 상에 유기절연막으로된 보호막을 형성하는 단계; UV를 이용하여 상기 보호막의 상부 표면에 대한 클리닝 공정을 실시하는 단계: 상기 클리닝 공정이 완료된 보호막 상부 표면에 대하여 F계열의 가스를 이용한 플라즈마 공정을 실시하는 단계; 상기 플라즈마 공정이 실시된 보호막의 상부 표면 상에 ITO 금속막을 형성하는 단계; 및 상기 ITO 금속막을 식각하여 화소전극을 형성하는 단계를 포함해서 이루어진 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of manufacturing a TFT LCD, including: providing an insulating substrate having a thin film transistor formed on an upper surface thereof; Forming a protective film of an organic insulating film on an entire surface of the insulating substrate; Performing a cleaning process on the upper surface of the protective film using UV: performing a plasma process using an F series gas on the upper surface of the protective film on which the cleaning process is completed; Forming an ITO metal film on an upper surface of the protective film subjected to the plasma process; And etching the ITO metal film to form a pixel electrode.
본 발명에 따르면, 보호막의 상부 표면을 무기물화시킴으로써, 후속 공정인 ITO 금속의 증착시에 상기 보호막과 ITO 금속막간의 계면 특성을 향상시킬 수 있으며, 이에 따라, ITO 금속막에 대한 미세 패턴 형성이 용이하다.According to the present invention, by inorganicizing the upper surface of the protective film, it is possible to improve the interfacial properties between the protective film and the ITO metal film during the deposition of the ITO metal, which is a subsequent process, thereby forming a fine pattern for the ITO metal film It is easy.
이하, 첨부한 도면에 의거하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 및 도 2b는 본 발명의 실시예에 따른 TFT LCD의 제조방법을 설명하기 위한 단면도로서, 우선, 도 2a에 도시된 바와 같이, 공지된 공정을 통해 TFT(도시안됨)가 형성된 절연기판(20) 전면 상에 폴리이미드, 레진 또는 BCB와 같은 유기절연막, 바람직하게는 레진막(22)을 도포한다.2A and 2B are cross-sectional views illustrating a method of manufacturing a TFT LCD according to an embodiment of the present invention. First, as shown in FIG. 2A, an insulating substrate on which a TFT (not shown) is formed through a known process ( 20) An organic insulating film such as polyimide, resin or BCB, preferably a resin film 22, is applied on the entire surface.
그런 다음, 레진막(22)의 상부 표면에 UV를 조사하여 상기 레진막 표면에 존재하는 C를 제거하고, 연속적으로 F계열 가스, 바람직하게는 SF6가스를 이용한 플라즈마 공정을 실시하여, 도 2b에 도시된 바와 같이, 레진막(22)의 상부 표면에 수십 Å의 두께에 걸쳐 F계열의 무기물층(23)을 형성시킨다.Then, the upper surface of the resin film 22 is irradiated with UV to remove C present on the surface of the resin film, and subsequently a plasma process using an F-based gas, preferably SF 6 gas, is performed, and FIG. 2B. As shown in FIG. 6, the F-based inorganic layer 23 is formed on the upper surface of the resin film 22 over a thickness of several tens of micrometers.
이어서, 상부 표면에 수십 Å 두께의 무기물층(23)이 형성된 레진막(22) 상에 공지된 방법으로 ITO 금속막을 형성하고, 상기 ITO 금속막을 식각하여 화소전극(24)을 형성한다. 그리고 나서, 180 내지 220℃ 온도에서 어닐링 공정을 실시하여 ITO의 결정화 정도를 더욱 향상시킨다.Subsequently, an ITO metal film is formed on the resin film 22 having the inorganic layer 23 having a thickness of several tens of micrometers on the upper surface thereof, and the pixel electrode 24 is formed by etching the ITO metal film. Then, an annealing process is performed at a temperature of 180 to 220 ° C. to further improve the degree of crystallization of ITO.
본 발명의 실시예에서는, 레지막(22)의 상부 표면에 전술한 바와 같이 UV를 이용한 클리닝 공정과 SF6가스를 이용한 플라즈마 공정을 통해 수십 Å에 걸쳐 무기물층(23)이 형성되기 때문에, 이러한 무기물층(23) 상에 ITO 금속막을 성막시킬 경우에는 무기물 베이스 상에 무기물 금속막을 형성하는 것에 기인하여 저온 공정에서도 ITO 금속막의 막 특성을 향상시킬 수 있게 된다.In the embodiment of the present invention, since the inorganic layer 23 is formed on the upper surface of the resist film 22 through the cleaning process using UV and the plasma process using SF 6 gas as described above, such an inorganic layer 23 is formed. When the ITO metal film is formed on the inorganic layer 23, the inorganic metal film is formed on the inorganic base, and thus the film characteristics of the ITO metal film can be improved even at a low temperature process.
따라서, ITO 금속막의 막 특성 향상으로 인하여, 상기 ITO 금속막의 식각시에 식각 균일도를 향상시킬 수 있게 되며, 이에 따라, ITO 금속막에 대한 미세 패턴 형성이 용이하게 이루어지고, 아울러, 식각 재현성도 향상시킬 수 있게 된다.Therefore, due to the improvement in the film properties of the ITO metal film, it is possible to improve the etching uniformity during the etching of the ITO metal film, thereby easily forming a fine pattern for the ITO metal film, and also improve the etching reproducibility. You can do it.
한편, 본 발명의 실시예는 UV를 이용한 클리닝 공정과 F계열의 가스를 이용한 플라즈마 공정의 추가로 인하여 공정 시간이 지연될 수도 있는나, 이는 상기 공정들과 ITO 금속막의 형성 공정을 연속적으로 진행함으로써, 공정 시간의 지연을 최소한으로 감소시킬 수 있으며, 이에 따라, 생산성 저하를 방지할 수 있게 된다.On the other hand, the embodiment of the present invention may be delayed due to the addition of the cleaning process using UV and the plasma process using the F-based gas, which is by continuing the process of forming the process and the ITO metal film In addition, the delay of the process time can be reduced to a minimum, and thus, the productivity decrease can be prevented.
이상에서 설명된 바와 같이, 본 발명은 유기절연막으로된 보호막 상에 무기물인 ITO막을 성막시키기 전에 UV를 이용한 보호막 표면의 클리닝 공정과 F계열의 가스를 이용한 플라즈마 공정을 실시하여 상기 보호막의 표면에 무기물층을 형성시킴으로써, 후속 공정인 ITO막의 성막시에 상기 ITO막의 특성을 향상시킬 수 있으며, 이에 따라, ITO막의 균일한 식각 속도를 얻을 수 있음으로 인하여 미세 패턴 형성이 용이하다.As described above, the present invention performs a cleaning process on the surface of the protective film using UV and a plasma process using a gas of F series before depositing the inorganic ITO film on the protective film of the organic insulating film, the inorganic material on the surface of the protective film By forming the layer, it is possible to improve the characteristics of the ITO film during the formation of the ITO film, which is a subsequent step, and thus, it is easy to form a fine pattern because a uniform etching rate of the ITO film can be obtained.
한편, 여기에서는 본 발명의 특정 실시예에 대하여 설명하고 도시하였지만, 당업자에 의하여 이에 대한 수정과 변형을 할 수 있다. 따라서, 이하, 특허청구의 범위는 본 발명의 진정한 사상과 범위에 속하는 한 모든 수정과 변형을 포함하는 것으로 이해할 수 있다.Meanwhile, although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980024222A KR100289649B1 (en) | 1998-06-25 | 1998-06-25 | Manufacturing Method of Thin Film Transistor Liquid Crystal Display Device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980024222A KR100289649B1 (en) | 1998-06-25 | 1998-06-25 | Manufacturing Method of Thin Film Transistor Liquid Crystal Display Device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20000003110A true KR20000003110A (en) | 2000-01-15 |
| KR100289649B1 KR100289649B1 (en) | 2001-05-02 |
Family
ID=19540852
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980024222A KR100289649B1 (en) | 1998-06-25 | 1998-06-25 | Manufacturing Method of Thin Film Transistor Liquid Crystal Display Device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100289649B1 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020091693A (en) * | 2001-05-31 | 2002-12-06 | 주식회사 현대 디스플레이 테크놀로지 | Method for manufacturing thin film transistor lcd |
| KR100518053B1 (en) * | 2001-06-22 | 2005-09-28 | 엔이씨 엘씨디 테크놀로지스, 엘티디. | Method for manufacturing active matrix type liquid crystal display device |
| KR100685947B1 (en) * | 2001-09-08 | 2007-02-23 | 엘지.필립스 엘시디 주식회사 | Method For Fabricating Liquid Crystal Display Device |
| CN105895824A (en) * | 2013-01-11 | 2016-08-24 | 林振坤 | Modified indium tin oxide (ITO) anode |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01248137A (en) * | 1988-03-30 | 1989-10-03 | Toshiba Corp | Production of thin film transistor array for liquid crystal display |
| JPH03116830A (en) * | 1989-09-29 | 1991-05-17 | Toshiba Corp | Etching back method |
-
1998
- 1998-06-25 KR KR1019980024222A patent/KR100289649B1/en not_active IP Right Cessation
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020091693A (en) * | 2001-05-31 | 2002-12-06 | 주식회사 현대 디스플레이 테크놀로지 | Method for manufacturing thin film transistor lcd |
| KR100518053B1 (en) * | 2001-06-22 | 2005-09-28 | 엔이씨 엘씨디 테크놀로지스, 엘티디. | Method for manufacturing active matrix type liquid crystal display device |
| US7277152B2 (en) | 2001-06-22 | 2007-10-02 | Nec Corporation | Method for manufacturing active matrix type liquid crystal display device comprising annealing of the passivation film |
| KR100685947B1 (en) * | 2001-09-08 | 2007-02-23 | 엘지.필립스 엘시디 주식회사 | Method For Fabricating Liquid Crystal Display Device |
| CN105895824A (en) * | 2013-01-11 | 2016-08-24 | 林振坤 | Modified indium tin oxide (ITO) anode |
| CN105895824B (en) * | 2013-01-11 | 2017-12-26 | 陈居 | One kind modification indium-tin oxide anode |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100289649B1 (en) | 2001-05-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20070218576A1 (en) | Method for fabricating polysilicon liquid crystal display device | |
| US7414691B2 (en) | Liquid crystal display device with prevention of defective disconnection of drain/pixel electrodes by forming two conductive layers on top of entire pixel electrode and then removing a portion of both therefrom | |
| KR100289649B1 (en) | Manufacturing Method of Thin Film Transistor Liquid Crystal Display Device | |
| KR20000004422A (en) | Pixel electrode forming method for a liquid crystal display with high aperture rate | |
| KR100336881B1 (en) | Manufacturing Method of Thin Film Transistor Liquid Crystal Display Device | |
| KR100289650B1 (en) | Method of manufacturing thin film transistor liquid crystal display device | |
| KR100303348B1 (en) | Data line formation method of liquid crystal display device | |
| KR20000003174A (en) | Production method of thin film transistor | |
| KR101002470B1 (en) | Method for manufacturing lcd | |
| KR100527086B1 (en) | Method for manufacturing liquid crystal display device | |
| KR100341122B1 (en) | Gate electrode formation method of thin film transistor | |
| KR100590918B1 (en) | Method of manufacturing LCD | |
| KR20010004016A (en) | Method of manufacturing TFT-LCD | |
| KR100928493B1 (en) | Formation method of thin film transistor | |
| KR100590917B1 (en) | Method of manufacturing LCD | |
| KR20000003756A (en) | Thin film transistor and method thereof | |
| KR100279265B1 (en) | Protective film formation method of thin film transistor liquid crystal display device | |
| KR100577777B1 (en) | Method for forming transfer of TFT LCD | |
| KR100375734B1 (en) | Method of manufacturing TFT array substrate | |
| KR20000004412A (en) | Manufacturing method for a liquid crystal display | |
| KR20000003758A (en) | Thin film transistor liquid crystal display | |
| KR100559218B1 (en) | Method of manufacturing TFT array substrate | |
| KR20030021378A (en) | Metnod for manufacturing liquid crystal display panel | |
| KR100658064B1 (en) | Method for manufacturing liquide crystal display device with thin film transistor | |
| KR20020057025A (en) | Method for manufacturing Thin Film Transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20130107 Year of fee payment: 13 |
|
| FPAY | Annual fee payment |
Payment date: 20140116 Year of fee payment: 14 |
|
| FPAY | Annual fee payment |
Payment date: 20150116 Year of fee payment: 15 |
|
| FPAY | Annual fee payment |
Payment date: 20170119 Year of fee payment: 17 |
|
| FPAY | Annual fee payment |
Payment date: 20180118 Year of fee payment: 18 |
|
| EXPY | Expiration of term |