JPH05218037A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH05218037A
JPH05218037A JP1769892A JP1769892A JPH05218037A JP H05218037 A JPH05218037 A JP H05218037A JP 1769892 A JP1769892 A JP 1769892A JP 1769892 A JP1769892 A JP 1769892A JP H05218037 A JPH05218037 A JP H05218037A
Authority
JP
Japan
Prior art keywords
film
gold
resist pattern
wiring
conductive film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP1769892A
Other languages
Japanese (ja)
Inventor
Koji Ishii
弘二 石井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1769892A priority Critical patent/JPH05218037A/en
Publication of JPH05218037A publication Critical patent/JPH05218037A/en
Withdrawn legal-status Critical Current

Links

Abstract

PURPOSE:To obtain a gold wiring of high reliability by forming the wiring and a conductive film in a self-alignment when the film for enhancing adhesive properties is formed between the wiring and an insulating film. CONSTITUTION:After a gold wiring is formed by a plating method, a conductive film 7 for enhancing adhesive properties between gold and an insulating film and a polyamide film 8 are deposited without peeling a resist pattern, the entire surface is etched until the pattern is exposed. Then, the resist is removed, a power supply film 4 and a barrier film 3 are selectively removed, and further the film 8 and the film 7 adhering to the sidewall of a polyamide resin film are removed. Thus, the conductive film can be formed on the gold wiring in a self-alignment.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置の製造方法
に関し、特に、金配線の直上に絶縁膜との密着を高める
膜を形成する方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a film for improving adhesion with an insulating film directly on a gold wiring.

【0002】[0002]

【従来の技術】近年、半導体装置は、微細化、多層化が
進み、配線の信頼性の観点から金配線が使用されはじめ
ている。
2. Description of the Related Art In recent years, semiconductor devices have been miniaturized and multilayered, and gold wiring has begun to be used from the viewpoint of wiring reliability.

【0003】従来の金配線の製造方法を図3を参照しな
がら説明する。図3(a)のようにシリコン酸化膜2上
にまずバリア膜としてチタンタングステン3及びメッキ
用の給電膜として金4を全面に堆積し、次にポジレジス
トを用いたフォトリソグラフィー技術によりレジストパ
ターン5を形成する。次に図3(b)のように前記レジ
ストパターン5をマスクに金メッキを行い所望の膜厚の
金配線6を形成し、その後、レジストパターン5を全面
除去する。次に図3(c)のように、金配線6をマスク
に給電膜4及びバリア膜3を選択的にエッチングする。
次に図3(d)のように全面にチタンもしくはチタンタ
ングステン等の金配線と絶縁膜の密着性を高める導電膜
7を全面に堆積した後、再度フォトリソグラフィー技術
を用いて金配線6上にのみ前記導電膜7を残すように選
択的にエッチング除去する。次に図3(e)のように、
レジストパターン11を除去した後、層間絶縁膜10を
堆積する。
A conventional method for manufacturing gold wiring will be described with reference to FIG. As shown in FIG. 3A, first, titanium tungsten 3 as a barrier film and gold 4 as a power supply film for plating are deposited on the entire surface on the silicon oxide film 2, and then a resist pattern 5 is formed by a photolithography technique using a positive resist. To form. Next, as shown in FIG. 3B, gold plating is performed using the resist pattern 5 as a mask to form a gold wiring 6 having a desired film thickness, and then the resist pattern 5 is entirely removed. Next, as shown in FIG. 3C, the power supply film 4 and the barrier film 3 are selectively etched using the gold wiring 6 as a mask.
Next, as shown in FIG. 3D, a conductive film 7 that enhances the adhesion between the gold wiring such as titanium or titanium tungsten and the insulating film is deposited on the entire surface, and then the photolithography technique is used again to deposit on the gold wiring 6. Only the conductive film 7 is selectively removed by etching so as to remain. Next, as shown in FIG.
After removing the resist pattern 11, the interlayer insulating film 10 is deposited.

【0004】[0004]

【発明が解決しようとする課題】上述の従来の半導体装
置では、金と絶縁膜の密着性は導電膜7によって改善出
来るが、この導電膜7のパターニングと金配線6のパタ
ーニングが、別々のフォトリソグラフィー技術を用いて
いるため、目合せマージンを必要とし、更に、目合せズ
レを生じた場合配線間ショートを引き起こすという問題
点があり、また、給電膜4を金配線6をマスクにエッチ
ング除去する際、金配線6も概ね給電膜4の膜厚と同じ
だけ膜減りするためにあらかじめメッキ時に、膜減り分
厚く金配線を形成する必要があるが、この膜減りが安定
せず金配線の膜厚バラツキの一原因となる問題点もあっ
た。
In the above-mentioned conventional semiconductor device, the adhesion between gold and the insulating film can be improved by the conductive film 7, but the patterning of the conductive film 7 and the patterning of the gold wiring 6 are performed by different photolithography. Since the lithography technique is used, there is a problem that a margin for alignment is required, and if misalignment occurs, a short circuit occurs between the wirings, and the power supply film 4 is removed by etching using the gold wiring 6 as a mask. At this time, since the gold wiring 6 is also thinned by about the same as the thickness of the power supply film 4, it is necessary to form the gold wiring thickly in advance during plating, but this thinning is not stable and the thickness of the gold wiring is not stable. There was also a problem that contributed to the variation.

【0005】[0005]

【課題を解決するための手段】本発明の半導体装置で
は、第1の導電膜としてバリア膜と第2の導電膜として
給電膜を堆積する工程と、金配線を作るためのレジスト
パターンをパターニングする工程と、前記レジストパタ
ーンをマスクに選択的にかつ前記レジストパターンより
も薄い金配線をメッキ法により形成する工程と、全面に
第3の導電膜として金と絶縁膜の密着性を高める導電膜
を堆積する工程と、全面に塗布膜を回転塗布する工程
と、少なくとも前記レジストパターン上の塗布膜と第3
の導電膜が全て除去するまでエッチングする工程と、前
記レジストパターンを除去する工程と、前記第1及び第
2の導電膜を前記金パターン上の前記塗布膜をマスクに
エッチングする工程と、前記塗布膜をマスクに前記第3
の導電膜を等方性エッチングする工程と、前記塗布膜を
除去する工程とを備えている。
In the semiconductor device of the present invention, a step of depositing a barrier film as a first conductive film and a power supply film as a second conductive film, and patterning a resist pattern for forming a gold wiring. And a step of selectively forming a gold wiring thinner than the resist pattern using the resist pattern as a mask by a plating method, and a conductive film for enhancing adhesion between gold and an insulating film as a third conductive film over the entire surface. A step of depositing, a step of spin-coating a coating film on the entire surface, and a coating film on at least the resist pattern and a third step.
Etching until the conductive film is completely removed, a step of removing the resist pattern, a step of etching the first and second conductive films using the coating film on the gold pattern as a mask, and the coating. Using the film as a mask, the third
And a step of removing the coating film.

【0006】[0006]

【実施例】次に本発明について図面を参照して説明す
る。
The present invention will be described below with reference to the drawings.

【0007】図1(a)〜(e)は本発明の第1の実施
例を説明するための工程順に示した半導体装置の断面図
である。
FIGS. 1A to 1E are sectional views of a semiconductor device in the order of steps for explaining the first embodiment of the present invention.

【0008】図1(a)に示すように、半導体素子を形
成した基板1上にシリコン酸化膜2を堆積し、その後、
バリア膜となるチタンタングステン(TiW)3及び給
電膜となる金4を共に1000オングストローム堆積
し、フォトリソグラフィー技術を用いてレジストパター
ンを形成し、選択的に金メッキを行い、0.5μm 厚の
金配線6を形成する。次に図1(b)に示すように全面
に金と絶縁膜の密着性を高める膜としてチタン7を50
0オングストローム程堆積し、更にポリイミド樹脂膜8
を0.5μm 程塗布する。次にレジストパターン5上の
チタン7とポリイミド樹脂膜8が少なくとも全て除去さ
れるようにエッチングする。ここでポリイミド樹脂膜8
はO2 雰囲気のRIE(リアクティブイオンエッチ)
で、チタン7は、CF4 雰囲気のRIEでエッチングす
れば良い。そしてレジストパターン5を除去したものが
図1(c)である。
As shown in FIG. 1A, a silicon oxide film 2 is deposited on a substrate 1 on which a semiconductor element is formed, and then,
Titanium tungsten (TiW) 3 as a barrier film and gold 4 as a power supply film are both deposited to 1000 angstroms, a resist pattern is formed by using photolithography technology, and gold plating is selectively performed to form a gold wiring of 0.5 μm thickness. 6 is formed. Next, as shown in FIG. 1B, 50% titanium 7 is formed on the entire surface as a film for improving the adhesion between the gold and the insulating film.
Deposited about 0 Å and further polyimide film 8
Is applied to about 0.5 μm. Next, etching is performed so that at least the titanium 7 and the polyimide resin film 8 on the resist pattern 5 are removed. Here, the polyimide resin film 8
Is an O 2 atmosphere RIE (reactive ion etch)
Then, the titanium 7 may be etched by RIE in a CF 4 atmosphere. The resist pattern 5 is removed as shown in FIG.

【0009】次に図1の(d)に示すように金4とチタ
ンタングステン3をイオンミリングでポリイミド樹脂膜
8とチタン7をマスクにエッチングする。次に、図1
(e)のように等方性エッチング例えば、弗酸希釈液で
ポリイミド樹脂膜8の側壁部にあるチタン7をエッチン
グし、更にポリイミドをヒドラジン液で全て除去し、そ
の後層間絶縁膜10を堆積する。
Next, as shown in FIG. 1D, gold 4 and titanium tungsten 3 are etched by ion milling using the polyimide resin film 8 and titanium 7 as a mask. Next, FIG.
As shown in (e), isotropic etching, for example, the titanium 7 on the side wall of the polyimide resin film 8 is etched with a dilute solution of hydrofluoric acid, the polyimide is completely removed with a hydrazine solution, and then the interlayer insulating film 10 is deposited. ..

【0010】図2(a)〜(e)は、本発明の第2の実
施例を説明するための工程順に示した半導体装置の断面
図である。
2A to 2E are cross-sectional views of the semiconductor device in the order of steps for explaining the second embodiment of the present invention.

【0011】第1の実施例と異なる点は、金メッキ後に
全面堆積する膜をチタンタングステン12としていて、
バリア膜であるチタンタングステン3のエッチングと前
記チタンタングステン12を同時に過酸化水素水で等方
性エッチングしている(図2(d))。本実施例では、
第1の実施例に比べ、工程が簡略化されるというメリッ
トを有する。
The difference from the first embodiment is that the film deposited over the entire surface after gold plating is titanium tungsten 12,
The titanium-tungsten 3 which is a barrier film and the titanium-tungsten 12 are simultaneously isotropically etched with a hydrogen peroxide solution (FIG. 2D). In this example,
Compared with the first embodiment, there is an advantage that the process is simplified.

【0012】以上、実施例について述べたが、バリア膜
としては、チタンタングステンではなく、窒化チタン、
白金等のバリア性のある膜でも良いが、窒化チタン、白
金を使用する場合は、下の絶縁膜との密着性を高めるた
めにチタンを付け加えると良い。また、給電膜として金
ではなく、バリア膜でもある白金等の膜を使用しても良
い。更に金と絶縁膜の密着性を高める膜としてチタン,
チタンタングステンを使用したが、窒化チタンやクロム
等密着性を高める膜でも良い。更に、塗布膜としてポリ
イミドを使用したが、シリカフィルム,レジスト等でも
良い。
Although the embodiments have been described above, the barrier film is not titanium tungsten but titanium nitride,
A film having a barrier property such as platinum may be used, but when titanium nitride or platinum is used, titanium may be added in order to enhance the adhesion with the insulating film below. Instead of gold, a film of platinum or the like that is also a barrier film may be used as the power supply film. Furthermore, titanium is used as a film to enhance the adhesion between gold and the insulating film.
Although titanium-tungsten is used, a film that enhances the adhesiveness such as titanium nitride or chromium may be used. Further, although polyimide is used as the coating film, a silica film, a resist or the like may be used.

【0013】[0013]

【発明の効果】以上説明したように本発明は、金配線形
成と金配線上の金と絶縁膜の密着性を高める導電膜形成
をセルファラインで作ることが出来、かつ、給電膜とバ
リア膜の選択エッチングの際に金と絶縁膜の密着性を高
める導電膜上に塗布膜をマスクにしているので、絶縁膜
と密着性が良く、しかも、目合せ精度の良い金配線を実
現出来、かつ、金配線の膜厚の制御性も良いという効果
を有する。
As described above, according to the present invention, the gold wiring formation and the conductive film formation for enhancing the adhesion between the gold wiring and the insulating film can be made by self-alignment, and the power feeding film and the barrier film can be formed. Since the coating film is used as a mask on the conductive film that enhances the adhesiveness between the gold and the insulating film during the selective etching of, it is possible to realize the gold wiring that has good adhesiveness to the insulating film and good alignment accuracy. In addition, the controllability of the film thickness of the gold wiring is good.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例を工程順に示した断面図
である。
FIG. 1 is a sectional view showing a first embodiment of the present invention in the order of steps.

【図2】本発明の第2の実施例を工程順に示した断面図
である。
FIG. 2 is a cross-sectional view showing a second embodiment of the present invention in the order of steps.

【図3】従来の実施例を工程順に示した断面図である。FIG. 3 is a sectional view showing a conventional example in the order of steps.

【符号の説明】[Explanation of symbols]

1 基板 2 シリコン酸化膜 3 チタンタングステン、バリア膜 4 金、給電膜 5 レジストパターン 6 金配線 7 チタン、導電膜 8 ポリイミド樹脂膜 10 層間絶縁膜 11 レジストパターン 12 チタンタングステン 1 substrate 2 silicon oxide film 3 titanium tungsten, barrier film 4 gold, power supply film 5 resist pattern 6 gold wiring 7 titanium, conductive film 8 polyimide resin film 10 interlayer insulating film 11 resist pattern 12 titanium tungsten

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 半導体装置の一主面上に、第1の導電膜
と第2の導電膜を堆積する工程と、フォトリソグラフィ
ー技術を用いて金配線を作るためのレジストパターンを
パターニングする工程と、前記レジストパターンをマス
クに選択的にかつ、前記レジストパターンよりも薄くな
るようにメッキを行うことにより金パターンを作る工程
と、前記レジストパターンを剥離せずに全面に第3の導
電膜を堆積する工程と、全面に塗布膜を回転塗布する工
程と、少なくとも前記レジストパターン上の前記塗布膜
と前記第3の導電膜が全て除去するまでエッチングする
工程と、前記レジストパターンを除去する工程と、前記
第1及び第2の導電膜を前記金パターン上の前記塗布膜
をマスクにエッチングする工程と、前記塗布膜をマスク
に前記第3の導電膜を等方性エッチングする工程と、前
記塗布膜を除去する工程とを備えることを特徴とする半
導体装置の製造方法。
1. A step of depositing a first conductive film and a second conductive film on a main surface of a semiconductor device, and a step of patterning a resist pattern for forming a gold wiring by using a photolithography technique. A step of forming a gold pattern by selectively and using the resist pattern as a mask and plating so as to be thinner than the resist pattern; and depositing a third conductive film on the entire surface without peeling the resist pattern. A step of spin-coating a coating film on the entire surface, etching at least until the coating film and the third conductive film on the resist pattern are all removed, and a step of removing the resist pattern, Etching the first and second conductive films using the coating film on the gold pattern as a mask; and the third conductive film using the coating film as a mask. A method of manufacturing a semiconductor device, comprising the steps of: isotropically etching; and a step of removing the coating film.
JP1769892A 1992-02-03 1992-02-03 Manufacture of semiconductor device Withdrawn JPH05218037A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1769892A JPH05218037A (en) 1992-02-03 1992-02-03 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1769892A JPH05218037A (en) 1992-02-03 1992-02-03 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH05218037A true JPH05218037A (en) 1993-08-27

Family

ID=11951020

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1769892A Withdrawn JPH05218037A (en) 1992-02-03 1992-02-03 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH05218037A (en)

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Legal Events

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Effective date: 19990518