JPH05217830A - Wafer - Google Patents
WaferInfo
- Publication number
- JPH05217830A JPH05217830A JP4222582A JP22258292A JPH05217830A JP H05217830 A JPH05217830 A JP H05217830A JP 4222582 A JP4222582 A JP 4222582A JP 22258292 A JP22258292 A JP 22258292A JP H05217830 A JPH05217830 A JP H05217830A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- chamfered
- chamfering
- orientation flat
- outline
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000002093 peripheral effect Effects 0.000 claims description 23
- 238000000034 method Methods 0.000 claims description 8
- 230000007547 defect Effects 0.000 abstract description 19
- 235000012431 wafers Nutrition 0.000 description 90
- 238000005530 etching Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 230000002950 deficient Effects 0.000 description 3
- 238000003672 processing method Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 235000001630 Pyrus pyrifolia var culta Nutrition 0.000 description 1
- 240000002609 Pyrus pyrifolia var. culta Species 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000002223 garnet Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000007723 transport mechanism Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54493—Peripheral marks on wafers, e.g. orientation flats, notches, lot number
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はウエハ特に、ウエハの外
形線とオリエンテーションフラット等の位置決め用除去
部との接合領域のチッピング等の不良を防止することの
できるウエハに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer, and more particularly to a wafer capable of preventing defects such as chipping of a bonding area between a contour line of the wafer and a positioning removing portion such as an orientation flat.
【０００２】[0002]
【従来の技術】一般に、トランジスタ，集積回路（Ｉ
Ｃ）および大規模集積回路（ＬＳＩ）の如き半導体装置
の製造において、シリコン（Ｓｉ）等の半導体材料より
なるウエハに対し、拡散，レジスト塗布，エッチング，
蒸着等の処理を施こす場合、ウエハの表面に微少なゴミ
やチッピング片等の異物が付着すると、ウエハ表面にス
クラッチ傷が付いたり、膜厚の不均一あるいは搬送不良
等の不良発生原因となってしまう。2. Description of the Related Art Generally, transistors, integrated circuits (I
C) and the manufacture of semiconductor devices such as large scale integrated circuits (LSI), diffusion, resist coating, etching, etc. are performed on wafers made of semiconductor materials such as silicon (Si).
When processing such as vapor deposition, if foreign matter such as minute dust or chipping pieces adheres to the surface of the wafer, it may cause scratches on the surface of the wafer, uneven film thickness or defective transfer. Will end up.
【０００３】このような異物の発生の原因は種々のもの
があるが、その１つとして、たとえばウエハの搬送時に
ウエハの外周部が何らかの搬送機構と衝突したりあるい
はウエハどうしが接触することによりそのウエハ外周部
自体の一部が欠損を生じることが知られており、その欠
損によるチッピング片は異物としてウエハ表面に付着し
て各種不良を引き起こす。そこで、従来、この種のウエ
ハ外周部の欠損を防止するため、ウエハ外周部の両主表
面を機械的または化学的手段により面取りすることが提
案されている。There are various causes of the generation of such foreign matter. One of them is, for example, when the outer periphery of the wafer collides with some transport mechanism or the wafers come into contact with each other when the wafer is transported. It is known that a part of the outer peripheral portion of the wafer itself is damaged, and the chipping pieces due to the defect adhere to the surface of the wafer as foreign matter to cause various defects. Therefore, it has been conventionally proposed to chamfer both main surfaces of the outer peripheral portion of the wafer by mechanical or chemical means in order to prevent this kind of damage to the outer peripheral portion of the wafer.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、このよ
うにウエハ外周部の両主表面の面取りを行なうだけでは
ウエハのチッピングを未だ完全に防止することができな
い。However, the chipping of the wafer cannot be completely prevented only by chamfering both main surfaces of the outer peripheral portion of the wafer in this manner.
【０００５】そこで、本発明者等がそのようなチッピン
グの原因追及のために鋭意研究を重ねた結果、次のよう
な重大な事実が判明した。すなわち、ウエハには一般に
その結晶軸方向を示しかつ位置決めを行なうために一部
を直線状に切り取って、オリエンテーションフラット
（主フラット）と呼ばれるフラット部を形成することが
行なわれる。ところが、このようなフラット部の形成に
より、該フラット部とウエハの外形線との接合部に鋭角
的屈曲部が形成されてしまう。その結果、この接合部が
チッピングを起こし易く、ウエハの搬送時に該接合部が
エアベアリングのガイドに衝突したり、他のウエハと接
触したりすることにより、該接合部が欠損してチッピン
グ片を生じることになるものである。Then, as a result of the inventors of the present invention earnestly researching for the cause of such chipping, the following important facts have been found. That is, a wafer is generally cut in a straight line in order to show its crystal axis direction and perform positioning, to form a flat portion called an orientation flat (main flat). However, due to the formation of such a flat portion, an acute-angled bent portion is formed at the joint between the flat portion and the outline of the wafer. As a result, the bonded portion is apt to cause chipping, and when the wafer is transferred, the bonded portion collides with the guide of the air bearing or comes into contact with another wafer, so that the bonded portion is damaged and the chipping piece is removed. It will happen.
【０００６】したがって、本発明の目的は、ウエハ外周
部でのチッピングおよびウエハの外形線とオリエンテー
ションフラットの如きウエハ除去部との接合領域のチッ
ピングによる異物の発生およびその他の各種不良の発生
を防止することのできるウエハを提供することにある。Therefore, it is an object of the present invention to prevent the generation of foreign matters and various other defects due to chipping at the outer peripheral portion of the wafer and chipping of the bonding area between the wafer outline and the wafer removing portion such as the orientation flat. The object is to provide a wafer that can be manufactured.
【０００７】[0007]
【課題を解決するための手段】本願において開示される
発明のうち代表的なものの概要を簡単に説明すれば、下
記のとおりである。The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows.
【０００８】すなわち、ウエハの外形線とオリエンテー
ションフラットとの接合部が面取り加工され、かつウエ
ハの外周部も面取り加工されているウエハとするもので
ある。That is, the joint portion between the outline of the wafer and the orientation flat is chamfered, and the outer peripheral portion of the wafer is also chamfered.
【０００９】[0009]
【作用】上記した手段によれば、ウエハの外形線とオリ
エンテーションフラットとの接合領域及びウエハの外周
部が面取り加工されているためそれらに鋭角的角部また
は屈曲部が存在せず、上記接合部及び外周部はチッピン
グを起こさない。従って、チッピングによる異物の発生
およびその他の各種不良の発生を防止することができ
る。According to the above-mentioned means, since the outer peripheral portion of the wafer and the outer peripheral portion of the wafer where the contour line of the wafer and the orientation flat are joined are chamfered, there are no sharp corners or bent portions. And the outer peripheral portion does not cause chipping. Therefore, it is possible to prevent the generation of foreign matters and various other defects due to chipping.
【００１０】[0010]
【実施例】以下、本発明を図面に示す実施例にしたがっ
て詳細に説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the embodiments shown in the drawings.
【００１１】図１及び図２は本発明によるウエハの一実
施例を示すもので、図１はその平面図、図２は拡大断面
図である。1 and 2 show an embodiment of a wafer according to the present invention. FIG. 1 is its plan view and FIG. 2 is an enlarged sectional view.
【００１２】本実施例のウエハ１はたとえばシリコン
（Ｓｉ）の単結晶をスライスすることにより作られた円
形形状を有し、その一部分は結晶軸の方向を示しかつ各
種処理におけるウエハ１の位置決めを行なうための位置
決め用除去部として主フラットすなわちオリエンテーシ
ョンフラット（Ｏ．Ｆ．）２が直線状に切断形成されて
いる。The wafer 1 of this embodiment has a circular shape formed by slicing a silicon (Si) single crystal, for example, and a part of the wafer shows the direction of the crystal axis and is used for positioning the wafer 1 in various processes. A main flat, that is, an orientation flat (O.F.) 2 is linearly cut and formed as a positioning removing portion for performing.
【００１３】また、ウエハ１の外周部３は図２からわか
るようにたとえば円弧状に面取りされている。この面取
りによりウエハ外周部の欠損を防ぎ、ウエハ外周部での
チッピングを防止している。The outer peripheral portion 3 of the wafer 1 is chamfered, for example, in an arc shape, as can be seen from FIG. This chamfering prevents damage to the outer peripheral portion of the wafer and prevents chipping at the outer peripheral portion of the wafer.
【００１４】さらに、この実施例におけるウエハ１は前
記オリエンテーションフラット２の両端と該ウエハ１の
外形線との接合部４において二点鎖線で示す角部領域を
実線で示す円弧状に面取りされ、この接合部４の角部領
域がウエハ１の各種処理中にチッピングを起こし、欠損
によるチッピング片として異物を発生すること等の不良
を防止するよう構成されている。すなわち、図１の実施
例における接合部４の面取り領域５は二点鎖線とで囲ま
れた領域であり、この面取り領域５の内縁はウエハ１の
外形線とオリエンテーションフラット２とに内接する共
通内接円の円弧により画定されている。Further, the wafer 1 in this embodiment is chamfered in an arc shape in which a corner area indicated by a chain double-dashed line is indicated by a solid line at a joint 4 between both ends of the orientation flat 2 and the outline of the wafer 1. The corner areas of the bonding portion 4 are configured to prevent defects such as chipping occurring during various processing of the wafer 1 and generation of foreign matter as chipping pieces due to chipping. That is, the chamfered region 5 of the bonded portion 4 in the embodiment of FIG. 1 is a region surrounded by a chain double-dashed line, and the inner edge of the chamfered region 5 is inscribed in the contour line of the wafer 1 and the orientation flat 2. It is defined by the arc of a tangent circle.
【００１５】この接合部４の円弧状の面取りを行なう場
合、面取り領域５の好ましい面取り範囲は次のように決
定され、それについて図３に関して詳細に説明する。When carrying out the arc-shaped chamfering of the joint portion 4, the preferable chamfering range of the chamfered region 5 is determined as follows, which will be described in detail with reference to FIG.
【００１６】図３において、ウエハ１の半径はＲであ
り、その中心はＯ1とする。この中心Ｏ1からオリエンテ
ーションフラット２までの距離をｙとし、Ｏ1からオリ
エンテーションフラット２に垂線を下ろすと、その交点
Ｐはオリエンテーションフラット２の中間点であり、該
オリエンテーションフラット２の面取り加工前の全長の
半分すなわち点Ｐから該オリエンテーションフラット２
とウエハ１の外形線との接合部４までの距離はｂとす
る。In FIG. 3, the radius of the wafer 1 is R and its center is O 1 . When the distance from the center O 1 to the orientation flat 2 is y and a perpendicular is drawn from O 1 to the orientation flat 2, the intersection point P is the midpoint of the orientation flat 2 and the total length of the orientation flat 2 before chamfering. Orientation flat 2 from half of
The distance from the outer edge of the wafer 1 to the bonding portion 4 is b.
【００１７】オリエンテーションフラット２の長さおよ
びウエハ１の厚さとウエハの直径との関係はミラーウエ
ハ（鏡面ウエハ）状態で表１に示すようになることがＳ
ＥＭＩ規格において定められている。The relationship between the length of the orientation flat 2 and the thickness of the wafer 1 and the diameter of the wafer may be as shown in Table 1 in a mirror wafer (mirror surface wafer) state.
It is defined in the EMI standard.
【００１８】[0018]
【表１】 [Table 1]
【００１９】一方、オリエンテーションフラット２を利
用してウエハ１の位置合せを行なう必要上、オリエンテ
ーションフラット２には正確な位置合せのために最低限
有していなければならないフラット部の長さがあり、そ
の長さの半分をａとすると、長さａは点Ｐから共通内接
円とオリエンテーションフラット２との内接点ｉ1まで
の距離である。符号６は位置合せ用のローラであるが、
位置合せ手段としてはそれ以外に光電変換素子等を用い
てもよい。On the other hand, because it is necessary to align the wafer 1 by using the orientation flat 2, the orientation flat 2 has a minimum length of a flat portion that must be provided for accurate alignment. If half of the length is a, the length a is the distance from the point P to the inner contact point i 1 between the common inscribed circle and the orientation flat 2. Reference numeral 6 is a roller for alignment,
Other than that, a photoelectric conversion element or the like may be used as the alignment means.
【００２０】また、共通内接円とウエハ１の外形線との
内接点はｉ2とすると、共通内接円の中心Ｏ2はウエハ１
の中心Ｏ1と内接点ｉ1を結ぶ直線上にあり、この直線と
直線Ｏ1Ｐとの角度はθで表わされる。If the inner contact point between the common inscribed circle and the outline of the wafer 1 is i 2 , the center O 2 of the common inscribed circle is the wafer 1
Is on a straight line connecting the center O 1 of the and the inner contact i 1 , and the angle between this straight line and the straight line O 1 P is represented by θ.
【００２１】したがって、ウエハ１の外形線およびオリ
エンテーションフラット２の両方に内接する共通内接円
の半径ｒは次のようにして求められる。Therefore, the radius r of the common inscribed circle inscribed in both the outline of the wafer 1 and the orientation flat 2 is obtained as follows.
【００２２】まず、ローラ６による位置合せのために最
低限有していなければならない長さ、すなわちオリエン
テーションフラット２のうち面取り加工されないフラッ
ト部の長さａ（ａ＝Ｐｉ2）はFirst, the minimum length required for the alignment by the roller 6, that is, the length a (a = Pi 2 ) of the flat portion of the orientation flat 2 which is not chamfered is
【００２３】[0023]
【数２】 [Equation 2]
【００２４】次に、ウエハ１の中心Ｏ1からオリエンテ
ーション２への垂直Ｏ1Ｐの長さｙはNext, the length y of the vertical O 1 P from the center O 1 of the wafer 1 to the orientation 2 is
【００２５】[0025]
【数３】 [Equation 3]
【００２６】また、直角三角形Ｏ1Ｐ４より、ｙ2＝Ｒ2
−ｂ2であるから、From the right triangle O 1 P4, y 2 = R 2
Since it is −b 2 ,
【００２７】[0027]
【数４】 [Equation 4]
【００２８】（数３）式に（数４）式を代入すると、Substituting the equation (4) into the equation (3),
【００２９】[0029]
【数５】 [Equation 5]
【００３０】（数２）式よりFrom the equation (2),
【００３１】[0031]
【数６】 [Equation 6]
【００３２】sin2θ＋cos2θ＝１より、（数５），（数
６）式からFrom sin 2 θ + cos 2 θ = 1, from the equations (5) and (6),
【００３３】[0033]
【数７】 [Equation 7]
【００３４】（数７）式を整理すると、When the equation (7) is arranged,
【００３５】[0035]
【数８】 [Equation 8]
【００３６】したがって、本実施例においては、ウエハ
１の外形線とオリエンテーションフラット２との接合領
域における面取り領域５は図２に斜線で示すように、
（数８）式の半径ｒの共通内接円の円弧またはそれより
も外側の領域内であれば、どのような半径の円弧に沿っ
て面取り加工してもよい。Therefore, in the present embodiment, the chamfered region 5 in the joining region between the outline of the wafer 1 and the orientation flat 2 is as shown by the diagonal lines in FIG.
The chamfering may be performed along an arc of any radius as long as it is within the arc of the common inscribed circle having the radius r of the formula (8) or the region outside thereof.
【００３７】すなわち、ウエハ１の外形線およびオリエ
ンテーションフラット２の両方との共通内接円の半径ｒ
は次式に示す範囲内であればよく、この半径ｒの範囲内
で円弧状に面取り加工すればよい。That is, the radius r of the inscribed circle common to both the outline of the wafer 1 and the orientation flat 2
Is within the range shown by the following equation, and chamfering may be performed in an arc shape within the range of the radius r.
【００３８】[0038]
【数９】 [Equation 9]
【００３９】その結果、本実施例によれば、ウエハ１の
外形線とオリエンテーションフラット２との接合領域に
は、鋭角的な角部または屈曲部が全く存在しないので、
この接合領域がウエハ１の搬送時にたとえばエアベアリ
ングのガイドに衝突したり、他のウエハと接触したりす
ることにより欠損してチッピング片を発生することを防
止できる。また、このようなチッピング片の発生による
異物不良の他に、搬送時に鋭角的角部がエアベアリング
のガイド等に引っ掛ることによる搬送不良、さらにレジ
スト塗布時に鋭角的角部で気流が乱れることによりレジ
ストの膜厚が部分的にばらつくことによるレジスト膜厚
不良等の不良を著しく低減することができ、大径のウエ
ハにとって特に好適である。As a result, according to this embodiment, no sharp corners or bent portions are present in the joining region between the outline of the wafer 1 and the orientation flat 2,
It is possible to prevent a chipping piece from being generated due to the bonding area colliding with, for example, a guide of an air bearing or contact with another wafer when the wafer 1 is transferred. In addition to the foreign matter defect due to the generation of such chipping pieces, the conveyance failure due to the sharp corner being caught by the guide of the air bearing during the conveyance, and the air flow being disturbed at the sharp corner during the resist coating, It is possible to remarkably reduce defects such as defective resist film thickness due to partial variation of the resist film thickness, which is particularly suitable for large-diameter wafers.
【００４０】図４は本発明によるウエハの他の１つの実
施例を示す平面図である。FIG. 4 is a plan view showing another embodiment of the wafer according to the present invention.
【００４１】この実施例においては、ウエハ１の外形線
とオリエンテーションフラット２との接合領域を斜線で
示す面取り領域５の範囲内で直線的に面取り加工する。
この場合、面取り領域５の最大面取り範囲は、図３に関
して前記したように、ウエハ１の外形線およびオリエン
テーションフラット２の両方との共通内接円の内接点ｉ
1とｉ2とを結ぶ直線により画定される。この共通内接円
の半径ｒは前記（数９）式に示すものと同じ範囲内で選
択できる。In this embodiment, the bonding area between the outline of the wafer 1 and the orientation flat 2 is linearly chamfered within a chamfered area 5 indicated by diagonal lines.
In this case, the maximum chamfering range of the chamfered region 5 is, as described above with reference to FIG. 3, the inner contact point i of the common inscribed circle with both the outline of the wafer 1 and the orientation flat 2.
It is defined by the straight line connecting 1 and i 2 . The radius r of this common inscribed circle can be selected within the same range as shown in the above equation (9).
【００４２】本実施例の場合にも、ウエハ１の外形線と
オリエンテーションフラット２との接合部４における鋭
角的角部または屈曲部がなくなるので、チッピング片の
発生による異物不良，搬送不良，レジスト膜厚不良等を
大巾に低減できる。Also in the case of this embodiment, the sharp corners or bent portions at the joint 4 between the outline of the wafer 1 and the orientation flat 2 are eliminated, so that the foreign matter defect due to the generation of chipping pieces, the defective conveyance, the resist film. Defects in thickness can be greatly reduced.
【００４３】なお、本発明による面取り加工は前記実施
例の円弧状または直線上の他、様々な曲線形状または多
角形状等、鋭角的角部をなくすことのできるものであれ
ば、どのような面取り形状にもすることができる。The chamfering process according to the present invention is not limited to the above-described arc shape or straight line, but may be any chamfered shape such as various curved shapes or polygonal shapes as long as it can eliminate sharp corners. It can also be shaped.
【００４４】また、本発明は前記した主フラットすなわ
ちオリエンテーションフラットの他に、副フラットすな
わち第２フラットを設ける場合にも適用できる。すなわ
ち、この場合には、図５に示すようにオリエンテーショ
ンフラット２の両端とウエハ１の外形線との接合領域の
面取り領域５を面取り加工すると共に、第２フラット７
の両端とウエハ１の外形線との接合領域も５ａで示す範
囲の如く、第２フラット７およびウエハ１の外形線の両
方と内接する共通内接円の円弧または内接点どうしを結
ぶ直線に沿ってあるいはその外側の領域において面取り
加工する。The present invention can also be applied to the case where a sub-flat, that is, a second flat is provided in addition to the above-mentioned main flat, that is, the orientation flat. That is, in this case, as shown in FIG. 5, the chamfering region 5 in the joining region between the both ends of the orientation flat 2 and the outline of the wafer 1 is chamfered and the second flat 7 is formed.
The joint area between the both ends of the wafer 1 and the outline of the wafer 1 is also along the straight line connecting the arcs of the common inscribed circle or the internal contacts inscribed with both the outline of the second flat 7 and the outline of the wafer 1 as in the range indicated by 5a. Chamfering is performed on the outside or outside thereof.
【００４５】さらに、オリエンテーションフラット２お
よび第２フラット７の如きフラット部以外に、図５に符
号８で例示するように曲線状の位置決め用切欠きをウエ
ハ１に形成する場合にも本発明を適用することができ
る。すなわち、この場合、位置決め用切欠き８の両端と
ウエハ１の外形線との接合領域を、５ｂで示す範囲の如
く、該位置決め用切欠き８およびウエハ１の外形線の両
方に内接する共通内接円の円弧または内接点どうしを結
ぶ直線に沿ってあるいはその外側の領域において面取り
加工すればよい。Further, in addition to the flat portions such as the orientation flat 2 and the second flat 7, the present invention is also applied to the case where a curved positioning notch is formed on the wafer 1 as illustrated by reference numeral 8 in FIG. can do. That is, in this case, the joint area between the both ends of the positioning notch 8 and the outline of the wafer 1 is inscribed in both the positioning notch 8 and the outline of the wafer 1 as shown by 5b. The chamfering may be performed along the arc of the tangent circle or the straight line connecting the inner contact points or in the area outside thereof.
【００４６】本発明の面取り加工はオリエンテーション
フラット２の形成と同時に行なってもよく、あるいは外
周部３の厚さ方向の面取り加工と同時に行なってもよ
く、このような同時的面取り加工は作業効率的に非常に
良好であるが、別々に面取り加工してもよい。勿論、本
発明はウエハ１の外周部３の厚さ方向の面取り加工は必
ずしも必要とするものではない。The chamfering process of the present invention may be performed simultaneously with the formation of the orientation flat 2 or the chamfering process of the outer peripheral portion 3 in the thickness direction. It is very good, but it may be chamfered separately. Of course, the present invention does not necessarily require chamfering of the outer peripheral portion 3 of the wafer 1 in the thickness direction.
【００４７】なお、本発明により面取り加工を行なう場
合に用いることのできる装置としては様々なものが考え
られるが、図６〜図８にその一例を示す。Various devices are conceivable as a device that can be used for chamfering according to the present invention, and FIGS. 6 to 8 show one example thereof.
【００４８】図６の面取り装置はいわゆる形状倣い型の
もので、直線溝９を持つ砥石８を回転させながら水平方
向および垂直方向に移動させて面取り加工を行ない、ま
たウエハ１の外周部３の厚さ方向の面取り加工も行なう
ことができる。The chamfering device shown in FIG. 6 is of a so-called shape copying type. The grindstone 8 having the linear groove 9 is moved in the horizontal and vertical directions while being rotated to perform the chamfering process. Chamfering in the thickness direction can also be performed.
【００４９】図７の面取り装置はいわゆる形状転写型の
もので、ウエハ１の外周部３の厚さ方向の面取り形状に
合せた湾曲溝１１を有する砥石１０を回転させながら水
平方向に移動させることにより、ウエハ１の外周部３を
図２に示す如く面取り加工する他、図３〜図５に示す面
取り領域５，５ａ，５ｂも面取り加工することができ
る。The chamfering device shown in FIG. 7 is of a so-called shape transfer type, in which the grindstone 10 having the curved groove 11 matching the chamfered shape in the thickness direction of the outer peripheral portion 3 of the wafer 1 is moved horizontally while being rotated. Thus, in addition to chamfering the outer peripheral portion 3 of the wafer 1 as shown in FIG. 2, chamfering regions 5, 5a and 5b shown in FIGS. 3 to 5 can be chamfered.
【００５０】このように、図６および図７の面取り装置
は面取り領域５，５ａ，５ｂの面取り加工およびウエハ
１の外周部３の面取り加工のいずれも行なうことができ
るので、これらの機械的面取り加工は別々に行なっても
よいが、同時に行なうのが効率的である。As described above, the chamfering apparatus of FIGS. 6 and 7 can perform both the chamfering processing of the chamfering regions 5, 5a and 5b and the chamfering processing of the outer peripheral portion 3 of the wafer 1. The processing may be performed separately, but it is efficient to perform them simultaneously.
【００５１】また、図８の面取り装置は化学的に面取り
加工を行なうもので、多数のウエハ１を回転支持体１２
に挾んでエッチング槽１３内のエッチング液１４中に沈
め、回転支持体１２と共に回転させながらエッチング液
１４でウエハ１の外周部のエッチングを行なう。この場
合には、面取り領域５，５ａ，５ｂのみの面取り加工を
行なうためにはウエハ１の他の外周部をエッチング液１
４に触れないようマスクする必要があるが、面取り領域
５，５ａ，５ｂを予め機械的研削で面取り加工した後、
エッチング液で外周部全体の角部を厚さ方向に化学的に
面取り加工してもよい。図８の場合はウエハ１に対する
機械的衝撃を軽減できる。Further, the chamfering device of FIG. 8 chemically chamfers, and a large number of wafers 1 are supported by the rotary support 12.
The outer peripheral portion of the wafer 1 is etched by the etching solution 14 while being immersed in the etching solution 14 in the etching bath 13 while being rotated together with the rotary support 12. In this case, in order to perform the chamfering process only on the chamfered regions 5, 5a and 5b, the other outer peripheral portion of the wafer 1 is etched with the etching solution 1.
Although it is necessary to mask so as not to touch 4, the chamfered regions 5, 5a and 5b are chamfered by mechanical grinding in advance,
The corners of the entire outer peripheral portion may be chemically chamfered in the thickness direction with an etching solution. In the case of FIG. 8, the mechanical impact on the wafer 1 can be reduced.
【００５２】なお、本発明はシリコン（Ｓｉ）よりなる
ウエハに限らず、ゲルマニウム（Ｇｅ）、あるいはガリ
ウム・砒素（ＧａＡｓ），ガリウム・ガーネットの如き
各種化合物半導体材料よりなるウエハにも適用できる。The present invention is not limited to wafers made of silicon (Si) but can be applied to wafers made of germanium (Ge) or various compound semiconductor materials such as gallium arsenide (GaAs) and gallium garnet.
【００５３】[0053]
【発明の効果】以上説明したように、本発明によれば、
ウエハの位置決め用除去部とウエハの外形線との接合領
域及びウエハの外周部に鋭角的角部または屈曲部が存在
しないので、ウエハのチッピングによる異物不良，搬送
不良，レジスト膜厚不良の如き、鋭角的角部または屈曲
部の存在に起因する不良を著しく低減できる。As described above, according to the present invention,
Since there are no sharp corners or bent portions in the joining area between the wafer positioning removal portion and the outer shape of the wafer and the outer peripheral portion of the wafer, foreign matter defects due to chipping of the wafer, conveyance defects, resist film thickness defects, etc. It is possible to significantly reduce defects caused by the presence of sharp corners or bent portions.
【図１】本発明によるウエハの一実施例の平面図。FIG. 1 is a plan view of an embodiment of a wafer according to the present invention.
【図２】図１のウエハの拡大断面図。FIG. 2 is an enlarged sectional view of the wafer shown in FIG.
【図３】図１のウエハにおける面取り領域の決定につい
て説明するための平面図。FIG. 3 is a plan view for explaining determination of a chamfered area in the wafer of FIG.
【図４】本発明によるウエハの他の１つの実施例の平面
図。FIG. 4 is a plan view of another embodiment of the wafer according to the present invention.
【図５】本発明のさらに他の実施例を示す平面図。FIG. 5 is a plan view showing still another embodiment of the present invention.
【図６】本発明によるウエハの加工方法を実施するため
に使用できる面取り装置の例を示す図。FIG. 6 is a view showing an example of a chamfering device that can be used for carrying out the wafer processing method according to the present invention.
【図７】本発明によるウエハの加工方法を実施するため
に使用できる面取り装置の例を示す図。FIG. 7 is a view showing an example of a chamfering device that can be used for carrying out the wafer processing method according to the present invention.
【図８】本発明によるウエハの加工方法を実施するため
に使用できる面取り装置の例を示す図である。FIG. 8 is a diagram showing an example of a chamfering device that can be used to carry out the wafer processing method according to the present invention.
１…ウエハ、２…オリエンテーションフラット、３…外
周部、４…面取り加工前のウエハの外形線とオリエンテ
ーションフラットとの接合部、５，５ａ，５ｂ…面取り
領域、６…位置決め用のローラ、７…第２フラット、８
…位置決め用切欠き。DESCRIPTION OF SYMBOLS 1 ... Wafer, 2 ... Orientation flat, 3 ... Peripheral part, 4 ... Joining part of the wafer outline and orientation flat before chamfering, 5, 5a, 5b ... Chamfering area, 6 ... Positioning roller, 7 ... 2nd flat, 8
… Notches for positioning.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 江頭 悦郎 山梨県中巨摩郡竜王町西八幡（無番地）株 式会社日立製作所武蔵工場甲府分工場内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Etsuo Egashira Nishihachiman, Ryuo-cho, Nakakoma-gun, Yamanashi (No.) No. Ltd. Hitachi, Ltd. Musashi Factory Kofu Branch Factory
Claims (4)
オリエンテーションフラットまたその他の位置決め用除
去部との接合領域及びウエハ外周部の両主面が面取り加
工されていることを特徴とするウエハ。1. A wafer, characterized in that a bonding area between an outline of a wafer and an orientation flat with respect to the outline of the wafer or other positioning removing portion and both main surfaces of the outer peripheral portion of the wafer are chamfered.
位置決め用除去部の共通内接円に沿ってまたはそれより
も外側の領域において曲線状に行なわれていることを特
徴とする請求項１記載のウエハ。2. The chamfering process is performed in a curved shape along a contour line of the wafer and along a common inscribed circle of the positioning removal portion or in a region outside thereof. The described wafer.
位置決め用除去部の共通内接円の内接点間を結ぶ線に沿
ってまたはそれよりも外側の領域において直線状に行な
われることを特徴とする請求項１記載のウエハ。3. The chamfering process is performed linearly along a line connecting the outer contour line of the wafer and the inner contact points of the common inscribed circle of the positioning removal portion, or in a region outside thereof. The wafer according to claim 1, wherein
を特徴とする請求項２又は３記載のウエハ。 【数１】 ｒ＝内接円の半径 Ｒ＝ウエハの半径 ａ＝位置決め用除去部の面取り加工しない部分（フラッ
ト部）の長さの半分。 ｂ＝位置決め用除去部の面取り加工前の全長の半分。4. The wafer according to claim 2, wherein the radius of the inscribed circle is represented by the following equation. [Equation 1] r = radius of inscribed circle R = radius of wafer a = half the length of a portion (flat portion) of the removal portion for positioning which is not chamfered. b = half of the entire length of the positioning removal portion before chamfering.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22258292A JPH0777187B2 (en) | 1992-08-21 | 1992-08-21 | Wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22258292A JPH0777187B2 (en) | 1992-08-21 | 1992-08-21 | Wafer |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57131949A Division JPH0624199B2 (en) | 1982-07-30 | 1982-07-30 | Wafer processing method |
Related Child Applications (3)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP378195A Division JPH07201692A (en) | 1995-01-13 | 1995-01-13 | Wafer |
| JP7003783A Division JP2892959B2 (en) | 1995-01-13 | 1995-01-13 | Wafer processing method |
| JP7003782A Division JP2892958B2 (en) | 1995-01-13 | 1995-01-13 | Wafer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05217830A true JPH05217830A (en) | 1993-08-27 |
| JPH0777187B2 JPH0777187B2 (en) | 1995-08-16 |
Family
ID=16784731
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22258292A Expired - Lifetime JPH0777187B2 (en) | 1992-08-21 | 1992-08-21 | Wafer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0777187B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11121312A (en) * | 1997-10-13 | 1999-04-30 | Mitsui Eng & Shipbuild Co Ltd | Silicon carbide wafer |
| WO2014125844A1 (en) * | 2013-02-13 | 2014-08-21 | Ｍｉｐｏｘ株式会社 | Method for producing circular wafer by means of using grinding tape to grind edge of wafer comprising crystalline material and having notched section such as orientation flat |
| WO2016038980A1 (en) * | 2014-09-08 | 2016-03-17 | 住友電気工業株式会社 | Silicon carbide single crystal substrate and method for producing same |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5351591A (en) * | 1976-10-22 | 1978-05-11 | Hitachi Ltd | Method of removing sharpened portions from the peripheral corners of a plate |
| JPS53111277A (en) * | 1977-12-21 | 1978-09-28 | Hitachi Ltd | Semiconductor wafer and its fabricating method |
| JPS55121643A (en) * | 1979-03-13 | 1980-09-18 | Toshiba Corp | Fabricating method of semiconductor element |
| JPS5613728A (en) * | 1979-07-13 | 1981-02-10 | Nagano Denshi Kogyo Kk | Grinding method for semiconductor wafer |
| JPS5823430A (en) * | 1981-08-04 | 1983-02-12 | Nec Kyushu Ltd | Semiconductor wafer |
-
1992
- 1992-08-21 JP JP22258292A patent/JPH0777187B2/en not_active Expired - Lifetime
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5351591A (en) * | 1976-10-22 | 1978-05-11 | Hitachi Ltd | Method of removing sharpened portions from the peripheral corners of a plate |
| JPS53111277A (en) * | 1977-12-21 | 1978-09-28 | Hitachi Ltd | Semiconductor wafer and its fabricating method |
| JPS55121643A (en) * | 1979-03-13 | 1980-09-18 | Toshiba Corp | Fabricating method of semiconductor element |
| JPS5613728A (en) * | 1979-07-13 | 1981-02-10 | Nagano Denshi Kogyo Kk | Grinding method for semiconductor wafer |
| JPS5823430A (en) * | 1981-08-04 | 1983-02-12 | Nec Kyushu Ltd | Semiconductor wafer |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11121312A (en) * | 1997-10-13 | 1999-04-30 | Mitsui Eng & Shipbuild Co Ltd | Silicon carbide wafer |
| WO2014125844A1 (en) * | 2013-02-13 | 2014-08-21 | Ｍｉｐｏｘ株式会社 | Method for producing circular wafer by means of using grinding tape to grind edge of wafer comprising crystalline material and having notched section such as orientation flat |
| JP2014151418A (en) * | 2013-02-13 | 2014-08-25 | Mipox Corp | Method for manufacturing circular wafer by polishing circumferential edge of wafer made of crystal material and having notch part such as orientation flat by using polishing tape |
| US9496129B2 (en) | 2013-02-13 | 2016-11-15 | Mipox Corporation | Method for manufacturing a circular wafer by polishing the periphery, including a notch or orientation flat, of a wafer comprising crystal material, by use of polishing tape |
| WO2016038980A1 (en) * | 2014-09-08 | 2016-03-17 | 住友電気工業株式会社 | Silicon carbide single crystal substrate and method for producing same |
| JPWO2016038980A1 (en) * | 2014-09-08 | 2017-06-15 | 住友電気工業株式会社 | Silicon carbide single crystal substrate and method for manufacturing the same |
| CN110660840A (en) * | 2014-09-08 | 2020-01-07 | 住友电气工业株式会社 | Silicon carbide single crystal substrate and method for producing same |
| JP2020025104A (en) * | 2014-09-08 | 2020-02-13 | 住友電気工業株式会社 | Silicon carbide single crystal substrate and manufacturing method thereof |
| US10872759B2 (en) | 2014-09-08 | 2020-12-22 | Sumitomo Electric Industries, Ltd. | Silicon carbide single crystal substrate and method for manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0777187B2 (en) | 1995-08-16 |
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