JPH0521596A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0521596A JPH0521596A JP19487591A JP19487591A JPH0521596A JP H0521596 A JPH0521596 A JP H0521596A JP 19487591 A JP19487591 A JP 19487591A JP 19487591 A JP19487591 A JP 19487591A JP H0521596 A JPH0521596 A JP H0521596A
- Authority
- JP
- Japan
- Prior art keywords
- film
- thin film
- field oxide
- channel stopper
- film portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Landscapes
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、フィールド酸化膜及び
チャネルストッパによって素子分離が行われている半導
体装置の製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device in which element isolation is performed by a field oxide film and a channel stopper.
【0002】[0002]
【従来の技術】モノリシックICでは、一つの半導体チ
ップ上に配置する多数の素子同士を電気的に分離する必
要がある。この様な素子分離技術の一つに誘電体分離が
あり、誘電体分離の代表的な技術がLOCOS法による
フィールド酸化膜によって素子分離を行う方法である。2. Description of the Related Art In a monolithic IC, it is necessary to electrically separate a large number of elements arranged on one semiconductor chip. One of such element isolation techniques is dielectric isolation, and a typical technique of dielectric isolation is a method of performing element isolation by a field oxide film by the LOCOS method.
【0003】更に、フィールド酸化膜の下をチャネル領
域とする寄生MOSトランジスタの閾値電圧をフィール
ド酸化膜上の配線の電位よりも高くして、ICの動作電
圧の範囲でこの寄生MOSトランジスタを完全にカット
オフし、これによって素子分離を完全にするために、半
導体基板と同一導電型の高濃度不純物拡散層であるチャ
ネルストッパをフィールド酸化膜の下に形成している。Further, the threshold voltage of the parasitic MOS transistor whose channel region is below the field oxide film is set higher than the potential of the wiring on the field oxide film, and the parasitic MOS transistor is completely operated within the operating voltage range of the IC. In order to cut off and thereby complete element isolation, a channel stopper, which is a high-concentration impurity diffusion layer of the same conductivity type as the semiconductor substrate, is formed under the field oxide film.
【0004】ところで、この様なチャネルストッパの形
成方法の一つに、フィールド酸化膜の形成前にチャネル
ストッパ形成用の不純物を半導体基板にイオン注入して
おく方法がある。この方法では、フィールド酸化膜を形
成する際の耐酸化膜をマスクにして不純物をイオン注入
しておき、熱酸化時の熱でこの不純物を拡散させて、フ
ィールド酸化膜の形成と同時にチャネルストッパも形成
する。By the way, one of the methods of forming such a channel stopper is a method of ion-implanting an impurity for forming a channel stopper into a semiconductor substrate before forming a field oxide film. In this method, impurities are ion-implanted by using the oxidation resistant film when forming the field oxide film as a mask, and the impurities are diffused by the heat at the time of thermal oxidation, so that the channel stopper is formed simultaneously with the formation of the field oxide film. Form.
【0005】しかし、この方法では、チャネルストッパ
が活性領域にまで拡がり、チャネルストッパとは逆導電
型の不純物拡散層を活性領域に形成した場合に、この不
純物拡散層とチャネルストッパとが接する。このため、
不純物拡散層とチャネルストッパとの間の接合容量が増
大したり接合耐圧が低下したりする。この結果、活性領
域に形成した素子の動作速度が低下し、信頼性も低下す
る。However, in this method, when the channel stopper spreads to the active region and an impurity diffusion layer having a conductivity type opposite to that of the channel stopper is formed in the active region, the impurity diffusion layer and the channel stopper are in contact with each other. For this reason,
The junction capacitance between the impurity diffusion layer and the channel stopper increases or the junction breakdown voltage decreases. As a result, the operating speed of the element formed in the active region is reduced and the reliability is also reduced.
【0006】そこで、チャネルストッパのもう一つの形
成方法として、フィールド酸化膜の形成後に不純物をイ
オン注入する方法が考えられている。この方法では、フ
ィールド酸化膜の形成後に活性領域をフォトレジストで
覆い、このフォトレジストをマスクにしてフィールド酸
化膜の上から不純物をイオン注入するという所謂フィー
ルドイオン打込みを行う。Therefore, as another method of forming the channel stopper, a method of ion-implanting impurities after forming the field oxide film is considered. In this method, so-called field ion implantation is performed in which the active region is covered with a photoresist after the field oxide film is formed, and impurities are ion-implanted from above the field oxide film using the photoresist as a mask.
【0007】[0007]
【発明が解決しようとする課題】しかし、この方法で
も、リソグラフィ工程でマスクに位置合わせずれがあっ
て、フォトレジストがフィールド酸化膜に対して位置ず
れすると、活性領域の不純物拡散層とチャネルストッパ
とがやはり接してしまう。従って、従来の何れの方法で
も、動作速度が速く且つ信頼性が高い半導体装置を容易
には製造することができなかった。However, even in this method, when the photoresist is misaligned with respect to the field oxide film due to misalignment of the mask in the lithography process, the impurity diffusion layer in the active region and the channel stopper are not formed. Will still come into contact. Therefore, it has not been possible to easily manufacture a semiconductor device having a high operating speed and high reliability by any of the conventional methods.
【0008】そこで、本発明は、動作速度が速く且つ信
頼性が高い半導体装置を容易に製造することができる半
導体装置の製造方法を提供することを目的とする。Therefore, an object of the present invention is to provide a method of manufacturing a semiconductor device which can easily manufacture a semiconductor device having a high operation speed and high reliability.
【0009】[0009]
【課題を解決するための手段】本発明による半導体装置
の製造方法は、活性領域に挟まれている領域の中央部に
位置し膜厚が相対的に薄い薄膜部とこの薄膜部の両側に
位置し膜厚が相対的に厚い厚膜部とを有するフィールド
酸化膜を半導体基板の表面に形成し、前記厚膜部のうち
で前記薄膜部に連なる一部分と前記薄膜部とに対応する
開口を有するマスクを前記半導体基板上に形成し、前記
開口から前記半導体基板にチャネルストッパ形成用の不
純物をイオン注入する。According to the method of manufacturing a semiconductor device according to the present invention, a thin film portion having a relatively thin film thickness is formed at a central portion of a region sandwiched between active regions, and a thin film portion is formed on both sides of the thin film portion. A field oxide film having a thick film portion having a relatively thick film thickness is formed on the surface of the semiconductor substrate, and has a portion corresponding to the thin film portion of the thick film portion and an opening corresponding to the thin film portion. A mask is formed on the semiconductor substrate, and an impurity for forming a channel stopper is ion-implanted into the semiconductor substrate through the opening.
【0010】[0010]
【作用】本発明による半導体装置の製造方法では、例え
ばフィールド酸化膜のうちの薄膜部の膜厚がほぼ投影飛
程になる様にチャネルストッパ形成用の不純物をイオン
注入することにより、半導体基板上に形成したマスクの
みならずフィールド酸化膜の厚膜部もイオン注入時のマ
スクになる。しかも、マスクの開口は、厚膜部の全部で
はなく薄膜部に連なる一部分と薄膜部とにのみ対応して
いる。In the method of manufacturing a semiconductor device according to the present invention, the impurity for forming the channel stopper is ion-implanted on the semiconductor substrate so that the film thickness of the thin film portion of the field oxide film becomes approximately the projection range. The thick film portion of the field oxide film as well as the mask formed in step 2 serves as a mask during ion implantation. Moreover, the opening of the mask corresponds not to the entire thick film portion but to only a part connected to the thin film portion and the thin film portion.
【0011】このため、マスクがフィールド酸化膜に対
して多少位置ずれしても、フィールド酸化膜の中央部の
下にのみ自己整合的にチャネルストッパを形成すること
ができる。従って、チャネルストッパとは逆導電型の不
純物拡散層を活性領域に形成した場合に、この不純物拡
散層とチャネルストッパとが離間しており、これらの間
の接合容量が少なく接合耐圧も高い。Therefore, even if the mask is slightly displaced from the field oxide film, the channel stopper can be formed in a self-aligning manner only under the central portion of the field oxide film. Therefore, when an impurity diffusion layer having a conductivity type opposite to that of the channel stopper is formed in the active region, the impurity diffusion layer and the channel stopper are separated from each other, and the junction capacitance between them is small and the junction breakdown voltage is high.
【0012】[0012]
【実施例】以下、本発明の一実施例を、図1を参照しな
がら説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG.
【0013】本実施例では、図1(a)に示す様に、P
型のSiウェハ11の表面にパッド用のSiO2 膜12
を形成し、このSiO2 膜12上にSi3 N4 膜13を
堆積させる。そして、Si3 N4 膜13をパターニング
して、活性領域のパターンのSi3 N4 膜13aと、活
性領域に挟まれている素子分離領域の中央部に沿うパタ
ーンのSi3 N4 膜13bとを形成する。In this embodiment, as shown in FIG.
Type SiO 2 film 12 for pad on the surface of Si wafer 11
And a Si 3 N 4 film 13 is deposited on the SiO 2 film 12. Then, the Si 3 N 4 film 13 is patterned to form a Si 3 N 4 film 13a having a pattern in the active region and a Si 3 N 4 film 13b having a pattern along the central portion of the element isolation region sandwiched between the active regions. To form.
【0014】次に、この状態で熱酸化を行う。すると、
図1(b)に示す様に、Si3 N4 膜13が耐酸化膜に
なり、Siウェハ11のうちでこのSi3 N4 膜13に
覆われていない部分が選択的に酸化され、フィールド酸
化膜であるSiO2 膜14がSiウェハ11の表面に形
成される。Next, thermal oxidation is performed in this state. Then,
As shown in FIG. 1B, the Si 3 N 4 film 13 becomes an oxidation resistant film, and a portion of the Si wafer 11 which is not covered with the Si 3 N 4 film 13 is selectively oxidized, resulting in a field. A SiO 2 film 14 which is an oxide film is formed on the surface of the Si wafer 11.
【0015】しかし、この様な選択酸化(LOCOS)
法では、Si3 N4 膜13の端部にSiO2 膜14が横
方向へ食い込んで、バーズビークが発生する。このた
め、Si3 N4 膜13bの下にも両側からバーズビーク
が食い込み、この部分にも膜厚の薄いSiO2 膜14が
形成される。However, such selective oxidation (LOCOS)
In the method, the SiO 2 film 14 bites laterally in the end portion of the Si 3 N 4 film 13 to generate bird's beak. Therefore, bird's beaks also bite into the bottom of the Si 3 N 4 film 13b from both sides, and the thin SiO 2 film 14 is formed also in this portion.
【0016】従って、Si3 N4 膜13bの下に位置す
る薄膜部14aと、この薄膜部14aの両側に位置する
厚膜部14bと、これらの厚膜部14bに連なるバーズ
ビーク14cとから成り、中央部がくぼんでいるSiO
2 膜14が、フィールド酸化膜として形成される。Therefore, the thin film portion 14a located under the Si 3 N 4 film 13b, the thick film portions 14b located on both sides of the thin film portion 14a, and the bird's beak 14c connected to these thick film portions 14b, SiO with a hollow center
The 2 film 14 is formed as a field oxide film.
【0017】なお、Si3 N4 膜13bの幅を狭くする
と、このSi3 N4 膜13bの下に両側から食い込むバ
ーズビーク同士の重なりが大きくなって、薄膜部14a
の膜厚が厚くなる。また逆に、Si3 N4 膜13bの幅
を広くすると、上記の重なりが少なくなって、薄膜部1
4aの膜厚が薄くなる。従って、Si3 N4 膜13bの
幅によって、薄膜部14aの膜厚を調整することができ
る。If the width of the Si 3 N 4 film 13b is narrowed, the bird's beaks that bite from both sides below the Si 3 N 4 film 13b will be overlapped with each other, and the thin film portion 14a.
Becomes thicker. On the contrary, when the width of the Si 3 N 4 film 13b is widened, the above-mentioned overlap is reduced and the thin film portion 1
The film thickness of 4a becomes thin. Therefore, the film thickness of the thin film portion 14a can be adjusted by the width of the Si 3 N 4 film 13b.
【0018】次に、図1(c)に示す様に、Si3 N4
膜13を除去した後、フォトレジスト15を塗布し、厚
膜部14bの中央部近傍の上にフォトレジスト15の開
口15aの端縁が位置する様に、フォトレジスト15を
パターニングする。Next, as shown in FIG. 1C, Si 3 N 4
After removing the film 13, a photoresist 15 is applied, and the photoresist 15 is patterned so that the edge of the opening 15a of the photoresist 15 is located above the central portion of the thick film portion 14b.
【0019】次に、図1(d)に示す様に、フォトレジ
スト15をマスクにして、開口15a内のSiO2 膜1
4の上から、例えばSiO2 膜14のうちの薄膜部14
aの膜厚がほぼ投影飛程になる様なエネルギーで、ホウ
素等のP型の不純物16をSiウェハ11にイオン注入
する。Next, as shown in FIG. 1D, with the photoresist 15 as a mask, the SiO 2 film 1 in the opening 15a is formed.
4 from above, for example, the thin film portion 14 of the SiO 2 film 14
P-type impurities 16 such as boron are ion-implanted into the Si wafer 11 with such energy that the film thickness of “a” becomes approximately the projection range.
【0020】これによって、薄膜部14aの下、つまり
SiO2 膜14の中央部の下に、チャネルストッパにな
るP+ 拡散層17が形成される。その後、フォトレジス
ト15及びSiO2 膜12を除去し、SiO2 膜14に
囲まれている活性領域に、MOSトランジスタ等の素子
を形成する。As a result, the P + diffusion layer 17 serving as a channel stopper is formed below the thin film portion 14a, that is, below the central portion of the SiO 2 film 14. Then, the photoresist 15 and the SiO 2 film 12 are removed, and an element such as a MOS transistor is formed in the active region surrounded by the SiO 2 film 14.
【0021】[0021]
【発明の効果】本発明による半導体装置の製造方法で
は、チャネルストッパ形成用の不純物をイオン注入する
際のマスクがフィールド酸化膜に対して位置ずれして
も、チャネルストッパとは逆導電型の不純物拡散層を活
性領域に形成した場合に、この不純物拡散層とチャネル
ストッパとが離間しており、これらの間の接合容量が少
なく接合耐圧も高い。従って、動作速度が速く且つ信頼
性が高い半導体装置を容易に製造することができる。According to the method of manufacturing the semiconductor device of the present invention, even if the mask for ion-implanting the impurity for forming the channel stopper is displaced with respect to the field oxide film, the impurity of the conductivity type opposite to that of the channel stopper is used. When the diffusion layer is formed in the active region, the impurity diffusion layer and the channel stopper are separated from each other, and the junction capacitance between them is small and the junction breakdown voltage is high. Therefore, a semiconductor device having a high operating speed and high reliability can be easily manufactured.
【図1】本発明の一実施例を順次に示す側断面図であ
る。FIG. 1 is a side sectional view sequentially showing an embodiment of the present invention.
11 Siウェハ 14 SiO2 膜 14a 薄膜部 14b 厚膜部 15 フォトレジスト 15a 開口 16 不純物 17 P+ 拡散層11 Si Wafer 14 SiO 2 Film 14a Thin Film Part 14b Thick Film Part 15 Photoresist 15a Opening 16 Impurity 17 P + Diffusion Layer
Claims (1)
位置し膜厚が相対的に薄い薄膜部とこの薄膜部の両側に
位置し膜厚が相対的に厚い厚膜部とを有するフィールド
酸化膜を半導体基板の表面に形成し、前記厚膜部のうち
で前記薄膜部に連なる一部分と前記薄膜部とに対応する
開口を有するマスクを前記半導体基板上に形成し、前記
開口から前記半導体基板にチャネルストッパ形成用の不
純物をイオン注入する半導体装置の製造方法。Claim: What is claimed is: 1. A thin film portion, which is located in the central portion of the region sandwiched by the active regions and has a relatively thin film thickness, and a thin film portion, which is located on both sides of this thin film portion, and is relatively thick A field oxide film having a thick film portion is formed on a surface of a semiconductor substrate, and a mask having an opening corresponding to a portion of the thick film portion connected to the thin film portion and the thin film portion is formed on the semiconductor substrate. Then, a method of manufacturing a semiconductor device in which an impurity for forming a channel stopper is ion-implanted into the semiconductor substrate from the opening.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19487591A JPH0521596A (en) | 1991-07-09 | 1991-07-09 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19487591A JPH0521596A (en) | 1991-07-09 | 1991-07-09 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0521596A true JPH0521596A (en) | 1993-01-29 |
Family
ID=16331769
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19487591A Withdrawn JPH0521596A (en) | 1991-07-09 | 1991-07-09 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0521596A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08130253A (en) * | 1994-10-31 | 1996-05-21 | Nec Corp | Semiconductor integrated circuit device and fabrication thereof |
-
1991
- 1991-07-09 JP JP19487591A patent/JPH0521596A/en not_active Withdrawn
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08130253A (en) * | 1994-10-31 | 1996-05-21 | Nec Corp | Semiconductor integrated circuit device and fabrication thereof |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19981008 |