JPH05182969A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH05182969A
JPH05182969A JP7292A JP7292A JPH05182969A JP H05182969 A JPH05182969 A JP H05182969A JP 7292 A JP7292 A JP 7292A JP 7292 A JP7292 A JP 7292A JP H05182969 A JPH05182969 A JP H05182969A
Authority
JP
Japan
Prior art keywords
aluminum
film
wiring
alloy
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7292A
Other languages
Japanese (ja)
Inventor
Kotaro Izawa
光太郎 伊澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Yamagata Ltd
Original Assignee
NEC Yamagata Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Yamagata Ltd filed Critical NEC Yamagata Ltd
Priority to JP7292A priority Critical patent/JPH05182969A/en
Publication of JPH05182969A publication Critical patent/JPH05182969A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To prevent an uneven part from being produced on a sidewall by a heat treatment after an aluminum interconnection having a layer structure has been formed. CONSTITUTION:After an aluminum interconnection has been formed, a high- pressure steam treatment and a heat treatment are executed or an oxygen plasma treatment is executed; time sidewall of an aluminum or aluminum-alloy film 4 is covered with an alumina film 6. Consequently, it is possible to prevent than uneven part from being produced on the surface of the sidewall of the aluminum or aluminum-alloy film due to the alumina film.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置の構造に係わ
り、特に金属配線の構造に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device structure, and more particularly to a metal wiring structure.

【0002】[0002]

【従来の技術】従来の半導体装置の配線構造は図2に示
すように半導体基板1および絶縁膜2の上に例えばPV
D法によりチタン金属の薄い膜3、アルミニウム−シリ
コン−銅合金の厚い膜4,上層にタングステン−シリコ
ン化合物の薄い膜5の順に成膜した後、例えばホトリソ
グラフィー法で各膜を同一平面形状にパターンニングし
て形成された構造となっていた。
2. Description of the Related Art As shown in FIG. 2, a conventional wiring structure of a semiconductor device has, for example, PV on a semiconductor substrate 1 and an insulating film 2.
After the titanium metal thin film 3, the aluminum-silicon-copper alloy thick film 4, and the tungsten-silicon compound thin film 5 are formed in this order by the D method, the respective films are formed into the same plane shape by, for example, a photolithography method. The structure was formed by patterning.

【0003】[0003]

【発明が解決しようとする課題】この従来の半導体装置
の配線構造は、側壁にアルミニウムもしくはアルミニウ
ム合金の主配線材料となる厚い膜の側壁が剥き出しの状
態となっているため、配線形成後に配線上に絶縁保護膜
を成長させたり、電気特性を安定化させるために熱処理
を行うと、アルミニウムもしくはアルミニウム合金の剥
き出した面にアルミニウムの原子移動によりヒロック・
消失といった凹凸が生じ、配線巾,配線間隔がサブミク
ロンになるとアルミニウムもしくはアルミニウム合金層
の断線や、隣の配線との接触によって、配線の抵抗大、
オープンや配線間のリーク,ショートを引き起こすとい
う問題があった。
In the conventional wiring structure of the semiconductor device, since the side wall of the thick film, which is the main wiring material of aluminum or aluminum alloy, is exposed on the side wall, the wiring is formed on the wiring after the wiring is formed. When an insulating protective film is grown on or a heat treatment is performed to stabilize the electrical characteristics, hillocks are transferred to the exposed surface of aluminum or aluminum alloy due to the migration of aluminum atoms.
When unevenness such as disappearance occurs and the wiring width and wiring spacing become submicron, the resistance of the wiring is large due to the disconnection of the aluminum or aluminum alloy layer or the contact with the adjacent wiring.
There was a problem that it caused an open circuit, a leak between wirings, and a short circuit.

【0004】[0004]

【課題を解決するための手段】半導体基板または該半導
体基板上の絶縁膜の上にアルミニウムもしくはアルミニ
ウム合金から成る厚い膜を主配線材料としその上下に、
タングステン、チタン等の高融点金属、該高融点金属の
合金もしくは該高融点金属とシリコン、窒素等の非金属
との化合物から成る薄い膜を形成して複数層状構造と
し、これをパターンニングして形成された配線構造にお
いて、上記アルミニウムもしくはアルミニウム合金から
成る厚い膜の側壁がアルミナで被覆されている半導体装
置にある。
A thick film made of aluminum or an aluminum alloy is used as a main wiring material on a semiconductor substrate or an insulating film on the semiconductor substrate, and a thick film is formed above and below the main wiring material.
A thin film made of a refractory metal such as tungsten or titanium, an alloy of the refractory metal or a compound of the refractory metal and a non-metal such as silicon or nitrogen is formed into a multi-layered structure, which is patterned. In the formed wiring structure, there is a semiconductor device in which the side wall of the thick film made of aluminum or aluminum alloy is covered with alumina.

【0005】[0005]

【実施例】次に本発明について図面を参照して説明す
る。図1は本発明の一実施例の断面図である。半導体基
板1および絶縁膜2の上に例えばP(プラズマ)−CV
D法によりチタン金属膜3を膜厚約100nm,アルミ
ニウム−シリコン−銅合金からなる主配線材料となる厚
い膜4を膜厚1000nm,最上層にタングステン−シ
リコン化合物膜5を膜厚100nm成膜し、例えばフォ
トリソグラフィー法で各膜を同じ平面形状にパターンニ
ングし、配線を形成する。この配線の形成された半導体
装置を数百℃の高圧水蒸気中にさらした後、数百℃の熱
処理を行うか、または低温酸素プラズマ中にさらす等に
より、アルミニウム−シリコン−銅合金膜4の側壁を数
十〜数百nmのアルミナ膜6で被覆する。
The present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of an embodiment of the present invention. On the semiconductor substrate 1 and the insulating film 2, for example, P (plasma) -CV
A titanium metal film 3 having a thickness of about 100 nm, a thick film 4 made of an aluminum-silicon-copper alloy as a main wiring material having a thickness of 1000 nm, and a tungsten-silicon compound film 5 having a thickness of 100 nm are formed by the D method. For example, each film is patterned into the same plane shape by a photolithography method to form wiring. The semiconductor device on which the wiring is formed is exposed to high-pressure steam of several hundreds of degrees Celsius and then subjected to heat treatment of several hundreds of degrees of Celsius, or exposed to low-temperature oxygen plasma, to form a sidewall of the aluminum-silicon-copper alloy film 4. Is coated with an alumina film 6 having a thickness of several tens to several hundreds nm.

【0006】[0006]

【発明の効果】以上説明したように本発明は、半導体基
板および絶縁膜上に形成されたアルミニウムもしくはア
ルミニウム合金、高融点金属および合金またはその非金
属との化合物による層構造の配線の中のアルミニウムも
しくはアルミニウム合金層の側壁が、アルミナで被膜さ
れた構造となっているため、配線形成後の熱処理によっ
てアルミニウムの原子移動が起きても凹凸が生じにく
く、配線巾、配線間隔が0.5μm程度では配線の抵抗
大異常や配線間ショートを従来の1/10以下にできる
という効果を有する。
As described above, according to the present invention, aluminum in an aluminum or aluminum alloy formed on a semiconductor substrate and an insulating film, a metal having a high melting point and an alloy or a compound of the nonmetal with aluminum in a layered structure is used. Alternatively, since the side wall of the aluminum alloy layer has a structure coated with alumina, unevenness is less likely to occur even if atomic transfer of aluminum occurs due to heat treatment after the wiring is formed, and the wiring width and the wiring interval are about 0.5 μm. This has the effect of making it possible to reduce abnormalities in the resistance of the wiring and short circuits between wirings to 1/10 or less of the conventional level.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例の断面図。FIG. 1 is a sectional view of an embodiment of the present invention.

【図2】従来例の断面図。FIG. 2 is a sectional view of a conventional example.

【符号の説明】[Explanation of symbols]

1 半導体基板 2 絶縁膜 3 チタン金属膜 4 アルミニウム−シリコン−銅合金膜 5 タングステン−シリコン化合物膜 6 アルミナ膜 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Insulating film 3 Titanium metal film 4 Aluminum-silicon-copper alloy film 5 Tungsten-silicon compound film 6 Alumina film

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板または該半導体基板上の絶縁
膜の上にアルミニウムもしくはアルミニウム合金から成
る厚い膜を主配線材料としその上下に、タングステン、
チタン等の高融点金属、該高融点金属の合金もしくは該
高融点金属とシリコン、窒素等の非金属との化合物から
成る薄い膜を形成して複数層状構造とし、これをパター
ンニングして形成された配線構造において、上記アルミ
ニウムもしくはアルミニウム合金から成る厚い膜の側壁
がアルミナで被覆されていることを特徴とする半導体装
置。
1. A thick film made of aluminum or aluminum alloy is used as a main wiring material on a semiconductor substrate or an insulating film on the semiconductor substrate, and tungsten is provided above and below the main wiring material.
It is formed by forming a thin film of a refractory metal such as titanium, an alloy of the refractory metal or a compound of the refractory metal and a nonmetal such as silicon or nitrogen into a multi-layered structure, and patterning this. In the above wiring structure, the side wall of the thick film made of the above aluminum or aluminum alloy is covered with alumina.
JP7292A 1992-01-06 1992-01-06 Semiconductor device Pending JPH05182969A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7292A JPH05182969A (en) 1992-01-06 1992-01-06 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7292A JPH05182969A (en) 1992-01-06 1992-01-06 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH05182969A true JPH05182969A (en) 1993-07-23

Family

ID=11463975

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7292A Pending JPH05182969A (en) 1992-01-06 1992-01-06 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH05182969A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5943549A (en) * 1982-09-03 1984-03-10 Fujitsu Ltd Method of forming aluminum wiring layer
JPS6444045A (en) * 1987-08-11 1989-02-16 Nec Corp Wiring structure of semiconductor device
JPS6480044A (en) * 1987-09-21 1989-03-24 Sharp Kk Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5943549A (en) * 1982-09-03 1984-03-10 Fujitsu Ltd Method of forming aluminum wiring layer
JPS6444045A (en) * 1987-08-11 1989-02-16 Nec Corp Wiring structure of semiconductor device
JPS6480044A (en) * 1987-09-21 1989-03-24 Sharp Kk Semiconductor device

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Effective date: 19980331