JPH0434939A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH0434939A JPH0434939A JP14069790A JP14069790A JPH0434939A JP H0434939 A JPH0434939 A JP H0434939A JP 14069790 A JP14069790 A JP 14069790A JP 14069790 A JP14069790 A JP 14069790A JP H0434939 A JPH0434939 A JP H0434939A
- Authority
- JP
- Japan
- Prior art keywords
- metal
- film
- wiring
- intermetallic compound
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000010408 film Substances 0.000 claims abstract description 25
- 229910052751 metal Inorganic materials 0.000 claims abstract description 22
- 239000002184 metal Substances 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 229910000765 intermetallic Inorganic materials 0.000 claims abstract description 12
- 239000010409 thin film Substances 0.000 claims abstract description 9
- 238000002844 melting Methods 0.000 claims abstract description 7
- 230000008018 melting Effects 0.000 claims abstract description 7
- 229910052723 transition metal Inorganic materials 0.000 claims abstract description 5
- 150000003624 transition metals Chemical class 0.000 claims abstract description 5
- 238000000151 deposition Methods 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 7
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 6
- 239000010703 silicon Substances 0.000 abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 4
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 abstract description 3
- 235000011114 ammonium hydroxide Nutrition 0.000 abstract description 3
- 229910052786 argon Inorganic materials 0.000 abstract description 3
- 229940125898 compound 5 Drugs 0.000 abstract description 3
- 239000007789 gas Substances 0.000 abstract description 3
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 3
- 238000001755 magnetron sputter deposition Methods 0.000 abstract description 2
- 239000000203 mixture Substances 0.000 abstract description 2
- VZGDMQKNWNREIO-UHFFFAOYSA-N tetrachloromethane Chemical compound ClC(Cl)(Cl)Cl VZGDMQKNWNREIO-UHFFFAOYSA-N 0.000 abstract 2
- 238000004544 sputter deposition Methods 0.000 description 8
- 230000035882 stress Effects 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 230000005012 migration Effects 0.000 description 4
- 238000013508 migration Methods 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 102220043690 rs1049562 Human genes 0.000 description 2
- 241001663154 Electron Species 0.000 description 1
- 229910018594 Si-Cu Inorganic materials 0.000 description 1
- 229910008465 Si—Cu Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000006355 external stress Effects 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 239000013077 target material Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装１に関し、特に高信頼度の配線構造を
有する半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device 1, and particularly to a semiconductor device having a highly reliable wiring structure.
半導体集積回路の配線は、アルミニウム（Ａｆｆｌ）を
主成分とするターゲツト材をスパッタ法により堆積して
から、選択エツチングする方法が一般的である。Wiring in semiconductor integrated circuits is generally formed by depositing a target material mainly composed of aluminum (Affl) by sputtering and then selectively etching it.
半導体基板上に形成されたＡ（配線において、配線に含
まれているＡ（がシリコン基板中に異常拡散するアロイ
スパイクと称する不良モードがあり、つぎのような防止
法が実用化されている６Ａ、Ｃ中に１％前後のＳｉを予
め混合したターゲットを用いて、ＤＣマグネトロンスパ
ッタ法によりＳｉ基板表面に配線金属をスパッタする方
法がある。There is a failure mode called alloy spike in which A (contained in the wiring) abnormally diffuses into the silicon substrate formed on a semiconductor substrate, and the following prevention method has been put into practical use. There is a method of sputtering wiring metal onto the surface of a Si substrate by DC magnetron sputtering using a target in which approximately 1% Si is mixed in C in advance.
Ｓｉ基板表面にＣＶＤ法によりポリシリコン薄膜を成長
させ、さらにその上に純粋のＡＪをスパッタする方法が
ある。There is a method of growing a polysilicon thin film on the surface of a Si substrate by the CVD method, and then sputtering pure AJ thereon.
さらにエレクトロマイグレーションと称する不良モード
を防止して、配線の寿命を伸ばすため数％の銅を混合し
たターゲットを用いるスパッタ法（１，Ａｍｅｓ、 Ｆ
、Ｍ、ｄ’Ｈｅｕｒｌｅ、 Ｒ，Ｅ、Ｈｏｒｓｔｍａｎ
ｎ、 ＩＢＭ Ｊｏｕｒｎａｌ ｏｆ Ｒｅ５ｅａｒｃ
ｈ ａｎｄ Ｄｅｖｅｌｏｐｍｅｎｔ、 ｐｐ、４６１
゜ＪｕＩｙ、 １９７０）がある。Furthermore, in order to prevent a failure mode called electromigration and extend the life of the wiring, a sputtering method (1, Ames, F
, M. d'Heurle, R.E. Horstman
n, IBM Journal of Re5earc
h and Development, pp, 461
゜JuIy, 1970).
ＡＪの表面にＴｉなどの高融点金属薄膜積層させる構造
（Ｄ、Ｓ、Ｇａｒｄｎｅｒ、 Ｒ，Ｂ、Ｂｅｙｅｒｓ、
Ｔ、Ｌ、ＭｉｃｈａＩｋａ、に、Ｃ，Ｓａｒａｓｗａ
ｔ、 Ｊ、Ｐ、ＭｃＶｉｔｔｉｅ ａｎｄ Ｊ、Ｄ、Ｍ
ｅｉｎｄｌ、 ＩＥＥＥ Ｔｒａｎｓ、 ｏｎ Ｅｌｅ
ｃｔｒｏｎ Ｄｅｖｉｃｅｓ、 ＥＤ−３２（２）、Ｆ
ｅｂ、１９８５ ）がある。A structure in which a thin film of a high melting point metal such as Ti is laminated on the surface of the AJ (D, S, Gardner, R, B, Beyers,
T., L., Michaika, and C., Saraswa.
T, J, P, McVittie and J, D, M
eindl, IEEE Trans, on Ele
ctron Devices, ED-32(2), F
eb, 1985).
基板シリコンとＡＪとの間にバリアメタルとしてＴ ｉ
−Ｗ膜をはさむ方法（Ｒ，Ｂ、Ｇｈａｔｅ、 Ｊ、Ｂ、
ＢＩａｉｒ、 Ｃ，Ｒ，Ｆｕｌｌｅｒ、 Ｇ、Ｅ、Ｍｃ
ｇｕｉｒｅ、 Ｔｈ１ｎ ５ｏｌｉｄ Ｆｉｌｍｓ、
５３．１１７．（１９７８） ）が提案されている。Ti as a barrier metal between the substrate silicon and AJ
- Method of sandwiching W film (R, B, Ghate, J, B,
B.I.air, C.R., Fuller, G.E., Mc.
guire, Th1n 5olid Films,
53.117. (1978)) have been proposed.
半導体集積回路の高速化、高集積化に伴なうパターンの
微細化により、配線の電流密度の増大によるエレクトロ
マイグレーションや、絶縁膜にはさまれた配線の応力に
よるストレスマイグレーションなどによる電極配線の劣
化が問題になっている。As semiconductor integrated circuits become faster and more highly integrated, patterns become finer, resulting in deterioration of electrode wiring due to electromigration due to increased current density in wiring, stress migration due to stress on wiring sandwiched between insulating films, etc. has become a problem.
サブミクロンサイズの配線にはエレクトロマイグレーシ
ョン耐性、ストレスマイグレーション耐性、微細加工性
を備えた構造が求められている。Submicron-sized interconnects require structures that have electromigration resistance, stress migration resistance, and microfabricability.
本発明の半導体装１は、半導体基板の一主面に絶縁膜を
介して第１の金属からなる薄膜配線が形成され、第２の
高融点金属と遷移金属とのうち１つと前記第１の金属と
からなる金属間化合物が、前記配線の上面と側面とに自
己整合的に形成されているものである。In the semiconductor device 1 of the present invention, a thin film wiring made of a first metal is formed on one principal surface of a semiconductor substrate via an insulating film, and one of a second high melting point metal and a transition metal and the first An intermetallic compound made of metal is formed in a self-aligned manner on the upper surface and side surface of the wiring.
第１の金属からなる配線の上面と側面とに、第１の金属
と第２の高融点金属または遷移金属との金属間化合物が
自己整合的に形成されているため、機械的、熱的に安定
した金属間化合物により第１の金属からなる配線金属が
外部応力から守られ、表面から発生し易い亀裂に起因す
る断線を抑制することができる。Since an intermetallic compound of the first metal and the second high melting point metal or transition metal is formed in a self-aligned manner on the top and side surfaces of the wiring made of the first metal, it is mechanically and thermally The stable intermetallic compound protects the wiring metal made of the first metal from external stress, and can suppress disconnection due to cracks that tend to occur from the surface.
本発明の第１の実施例について、第１図（ａ）〜（ｃ）
を参照して説明する。Regarding the first embodiment of the present invention, FIGS. 1(a) to (c)
Explain with reference to.
はじめに第１図（ａ）に示すように、Ｐ型シリコン基板
１の表面にシリコン酸化膜２を形成し、ＤＣマグネトロ
ンスパッタにより、アルゴンプラズマ中でＡ！２ターゲ
ット（図示せず）をスパッタして、厚さ５０００人のＡ
ｌ膜を堆積する。First, as shown in FIG. 1(a), a silicon oxide film 2 is formed on the surface of a P-type silicon substrate 1, and A! 2 targets (not shown) were sputtered to a thickness of 5000 mm.
Deposit the l film.
つぎにフォトレジストをマスクとして、ＣＣｌＩ４ガス
を用いてＡｌ膜をドライエツチングしてＡ１配線３を形
成する。Next, using the photoresist as a mask, the Al film is dry etched using CClI4 gas to form the A1 wiring 3.
つぎに第１図（ｂ）に示すように、基板温度を３００℃
に保ってアルゴンプラズマ中でＴｉターゲット（図示せ
ず）をスパッタして、厚さ５００人のＴｉ膜４を堆積す
る。Next, as shown in Figure 1(b), the substrate temperature was increased to 300°C.
A Ti film 4 having a thickness of 500 nm is deposited by sputtering a Ti target (not shown) in an argon plasma at a constant temperature.
このときＡＪ２配線３の表面（上面および側面）に自己
整合的にＡＪ３ Ｔｉの金属間化合物５が形成される。At this time, an intermetallic compound 5 of AJ3 Ti is formed on the surface (upper surface and side surface) of the AJ2 wiring 3 in a self-aligned manner.
そのあと第１図（ｃ）に示すように、ＮＨ４ＯＨ： Ｈ
２０２： Ｈ２０＝１ ： ５ ： ５の混合液を用い
て、未反応のＴｉを選択的にエツチングする。Then, as shown in Figure 1(c), NH4OH: H
202: Unreacted Ti is selectively etched using a mixture of H20=1:5:5.
つぎに本発明の第２の実施例について、第２図（ａ）〜
（ｄ）を参照して説明する。Next, regarding the second embodiment of the present invention, FIGS.
This will be explained with reference to (d).
はじめに第２図（ａ）に示すように、Ｐ型シリコン基板
１の表面に酸化シリコン膜２を形成し、ＤＣマグネトロ
ンスパッタ法により、基板温度を２００℃に保ってアル
ゴンプラズマ中でＴｉターゲット（図示せず）をスパッ
タすることにより、厚さ５００人のＴｉ膜４を形成し、
引き続いて同一スパッタ装置内でＡ１−１％５ｔ−０，
５％ＣＵターゲット（図示せず）をスパッタして、厚さ
０．５ミクロンのＡＪ−３ｉ−Ｃｕ膜６を形成する。First, as shown in Fig. 2(a), a silicon oxide film 2 is formed on the surface of a P-type silicon substrate 1, and a Ti target (Fig. A Ti film 4 with a thickness of 500 nm is formed by sputtering (not shown).
Subsequently, A1-1%5t-0,
A 0.5 micron thick AJ-3i-Cu film 6 is formed by sputtering a 5% CU target (not shown).
つぎに第２図（ｂ）に示すように、フォトレジスト（図
示せず）をマスクとして、ＣＣｊｌ、ガスを用いてＡＪ
−３Ｌ−Ｃｕ膜６をドライエツチングしてＡＪ−Ｓｔ−
Ｃｕ配線６ａを形成する。Next, as shown in FIG. 2(b), using a photoresist (not shown) as a mask, AJ is applied using CCjl and gas.
-3L-Cu film 6 is dry etched to AJ-St-
A Cu wiring 6a is formed.
つぎに第２図（ｃ）に示すように、ＤＣマグトロンスパ
ッタ法により、基板温度を２００℃に保って全面に厚さ
５００人のＴｉ膜７を堆積する。Next, as shown in FIG. 2(c), a Ti film 7 with a thickness of 500 nm is deposited over the entire surface by DC magtron sputtering while keeping the substrate temperature at 200°C.
このときＡＪ−５ｉ−Ｃｕ配線６ａの表面（上面、側面
、下面）に自己整合的に厚さ１０００人のＡＪ３Ｔｉの
金属間化合物５が形成される。At this time, an AJ3Ti intermetallic compound 5 having a thickness of 1000 layers is formed in a self-aligned manner on the surface (upper surface, side surface, and lower surface) of the AJ-5i-Cu wiring 6a.
このあと第２図（ｄ）に示すように、ＮＨ４ＯＨ：Ｈ２
０□；Ｈ２０＝１：５：５の混合液を用いて、未反応の
Ｔｉを選択的にエツチングする。After this, as shown in Figure 2(d), NH4OH:H2
0□: Unreacted Ti is selectively etched using a mixed solution of H20=1:5:5.
本発明の配線は、融点が高く高温でも安定で、機械的に
も強い金属間化合物に被覆されている。The wiring of the present invention is coated with an intermetallic compound that has a high melting point, is stable even at high temperatures, and is mechanically strong.
そのためエレクトロマイグレーションやストレスマイグ
レーションに強いアルミ配線構造を得ることができた。As a result, we were able to obtain an aluminum wiring structure that is resistant to electromigration and stress migration.
さらに金属間化合物が自己整合的に形成されるので、サ
ブミクロンサイズの微細構造にも対応できる塑性変形の
起りにくい配線を形成することができる。Furthermore, since the intermetallic compound is formed in a self-aligned manner, it is possible to form wiring that is resistant to plastic deformation and can accommodate submicron-sized microstructures.
半導体集積回路の高速化、高集積化に伴なう配線の微細
化による電流密度の増大に起因するエレクトロマイグレ
ーションや、多層配線などの絶縁膜にはさまれた配線の
応力によるストレスマイグレーションなどの問題を解決
して電極配線の信頼性を向上させ、超高集積回路の実現
に役立つことが期待される。Problems such as electromigration caused by increased current density due to the miniaturization of interconnects as semiconductor integrated circuits become faster and more highly integrated, and stress migration caused by stress in interconnects sandwiched between insulating films such as multilayer interconnects. It is expected that this method will improve the reliability of electrode wiring and help realize ultra-highly integrated circuits.
第１図（ａ）〜（Ｃ）は本発明の第１の実施例を工程順
に示す断面図、第２図（ａ）〜（ｄ）は本発明の第２の
実施例を工程順に示す断面図である。
１・・・Ｐ型シリコン基板、２・・・酸化シリコン膜、
３・・・Ａ１配線、４・・・Ｔｉ膜、５・・・Ａｊ１３
Ｔｉ金属間化合物、６−Ａ ｆｆｌ −１％５ｉ−０，
５％Ｃｕ膜６ａ・−ＡＩ−Ｓｉ−Ｃｕ配線、７−Ｔ ｉ
膜。FIGS. 1(a) to (C) are cross-sectional views showing the first embodiment of the present invention in the order of steps, and FIGS. 2(a) to (d) are cross-sectional views showing the second embodiment of the present invention in the order of steps. It is a diagram. 1... P-type silicon substrate, 2... silicon oxide film,
3...A1 wiring, 4...Ti film, 5...Aj13
Ti intermetallic compound, 6-A ffl-1%5i-0,
5% Cu film 6a・-AI-Si-Cu wiring, 7-Ti
film.
Claims (1)
らなる薄膜配線が形成され、第２の高融点金属と遷移金
属とのうち１つと前記第１の金属とからなる金属間化合
物が、前記配線の上面と側面とに自己整合的に形成され
ていることを特徴とする半導体装置。 ２、半導体基板の一主面に形成された絶縁膜の上に、第
１の金属からなる薄膜配線を形成する工程と、全面に第
２の高融点金属と遷移金属とのうち１つからなる薄膜を
堆積する工程と、前記半導体基板を熱処理して前記薄膜
配線の上面と側面とに前記第１の金属と前記第２の金属
とからなる金属間化合物を形成する工程と、前記絶縁膜
上の前記第２の金属膜を選択的に除去する工程とからな
ることを特徴とする半導体装置の製造方法。[Claims] 1. A thin film wiring made of a first metal is formed on one main surface of a semiconductor substrate via an insulating film, and one of a second high melting point metal and a transition metal and the first A semiconductor device characterized in that an intermetallic compound made of a metal is formed in a self-aligned manner on an upper surface and a side surface of the wiring. 2. Forming a thin film wiring made of a first metal on an insulating film formed on one main surface of the semiconductor substrate, and forming a thin film wiring made of a second high melting point metal or a transition metal on the entire surface. a step of depositing a thin film; a step of heat-treating the semiconductor substrate to form an intermetallic compound consisting of the first metal and the second metal on the top and side surfaces of the thin film wiring; selectively removing the second metal film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14069790A JPH0434939A (en) | 1990-05-30 | 1990-05-30 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14069790A JPH0434939A (en) | 1990-05-30 | 1990-05-30 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0434939A true JPH0434939A (en) | 1992-02-05 |
Family
ID=15274641
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14069790A Pending JPH0434939A (en) | 1990-05-30 | 1990-05-30 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0434939A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08181139A (en) * | 1994-12-26 | 1996-07-12 | Nec Corp | Semiconductor device and manufacture thereof |
| US6224942B1 (en) * | 1999-08-19 | 2001-05-01 | Micron Technology, Inc. | Method of forming an aluminum comprising line having a titanium nitride comprising layer thereon |
| JP2009011745A (en) * | 2007-07-09 | 2009-01-22 | Toshiba Consumer Electronics Holdings Corp | Drawer type kitchen equipment drier |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6373646A (en) * | 1986-09-17 | 1988-04-04 | Toshiba Corp | Semiconductor device |
| JPH0370137A (en) * | 1989-07-20 | 1991-03-26 | Hyundai Electron Ind Co Ltd | Element linking metal wiring layer in semiconductor integrated circuit and manufacture thereof |
-
1990
- 1990-05-30 JP JP14069790A patent/JPH0434939A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6373646A (en) * | 1986-09-17 | 1988-04-04 | Toshiba Corp | Semiconductor device |
| JPH0370137A (en) * | 1989-07-20 | 1991-03-26 | Hyundai Electron Ind Co Ltd | Element linking metal wiring layer in semiconductor integrated circuit and manufacture thereof |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08181139A (en) * | 1994-12-26 | 1996-07-12 | Nec Corp | Semiconductor device and manufacture thereof |
| US6224942B1 (en) * | 1999-08-19 | 2001-05-01 | Micron Technology, Inc. | Method of forming an aluminum comprising line having a titanium nitride comprising layer thereon |
| JP2009011745A (en) * | 2007-07-09 | 2009-01-22 | Toshiba Consumer Electronics Holdings Corp | Drawer type kitchen equipment drier |
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