JPS6265344A - Formation of multilayer interconnection - Google Patents

Abstract

PURPOSE:To reduce a through-hole resistance in a multilayer interconnection by a method wherein, when the lower interconnection and the upper interconnection are connected through the penetrated hole of the interlayer insulating film, the surface of the lower interconnection is first etched on condition that sputter-etching takes place, subsequently the upper interconnection is formed on condition that the upper interconnection is deposited. CONSTITUTION:A through hole 5 is opened in an organic coated film 4 by a normal photo etching method and a second layer Al film is formed using an Al bias sputtering device. In this case, the situation that Al is deposited comes varying according to whether it is etched or deposited by bias voltage of a power source (b) is first made larger to perform sputter-etching on the surface of the first layer Al electrode 3 of the through hole part on the side of an electrode B. Subsequently, when the bias voltage (b) [or the bias at a power source (a)] is dropped, the Al is transferred to the condition that it is deposited, the Al from a sputter etching electrode A is sputter to the side of the electrode B and the Al is deposited on the surface of the first layer Al electrode 3 to form a second layer Al interconnection 9.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a method for forming multilayer wiring in a semiconductor device.

[Background technology]

In semiconductor integrated circuit devices such as ICJP LSI, as the number of elements per chip increases, the Al (aluminum) wiring that connects the elements cannot be formed in a single layer structure. structure has been adopted. An insulating film is interposed between the two or more layers of wiring, and electrical continuity between the upper and lower wirings is achieved through a through hole formed in the insulating film.

For the insulating coating, a highly heat-resistant polyimide polymer resin, such as polyimide-in-indolo-quinazolinedione, which is advantageous for surface flattening, is used.

Such an organic resin interlayer insulating film is formed by forming the lower layer wiring, applying a resin face on the substrate, and curing it with heat. Then, through holes are formed using conventional photolithography and f-ng techniques.

The through-hole portion formed in this manner has deteriorated heat resistance and a reaction layer is present on the side surface, and an undesired insulating film is formed on the surface of the lower wiring. Therefore, if A1 is formed for the upper layer wiring on top of this, the electrical resistance at the through-hole portion, that is, the RTH (through-hole) resistance will increase, causing a defect that prevents the semiconductor device from operating normally. Occur.

As a method to solve this problem, the present inventor formed a through hole in a highly heat-resistant organic film such as a polyimide resin formed on the lower layer Al wiring, and then etched and removed the through hole by sputtering. After that, it is proposed to perform continuous Al sputtering to form upper layer wiring without breaking the vacuum. JP 55-59741 Accordingly, when the wiring width becomes 4 .mu.m or less and the through-hole diameter of the interlayer coating becomes 3 .mu.m or less, the through-hole resistance increases rapidly, and the above-mentioned technique 1 is insufficient to solve the problem.

[Purpose of the invention]

The present invention has been made to overcome the above-mentioned problems. One object of the present invention is to provide a technique for reducing through-hole resistance in multilayer wiring.

Another object of the present invention is to provide a technique for forming multilayer wiring using bias sputtering technique. The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief summary of typical inventions disclosed in this application is as follows.

That is, a lower layer A wiring is formed on the substrate, a highly heat-resistant organic film is formed as an interlayer film on top of the wiring, a through hole is made in this organic film, and the wire is inserted into an A1 bias sputtering device. First, the surface of the lower layer 1 wiring is etched under conditions where Al is sputtered, and then the A1 wiring is connected to the lower layer Affl wiring through the through hole under sputtering conditions where A1 is deposited, thereby forming the A1 wiring between the A stone layers. The through-hole resistance is reduced without the presence of foreign matter, thereby achieving higher integration of semiconductor devices and improved yields.

〔Example〕

1 to 7 are process cross-sectional views of an A42 layer wiring forming process showing one implementation of the present invention.

Each step will be explained below.

(1) Affl is sputtered (vaporized N) onto the surface of the Si substrate 10 through two oxide (Si01) films, and the required patterning is performed by a normal photoetching method to form a first pattern as shown in FIG. Layer A! Form arrangement 11!3.

(2) A southern coating for an interlayer insulating film on the first layer Al wiring 3;
For example, form a polyimide isoindolo quinazolinedione film 4 and heat cure it by annealing. (Fig. 2) (3) Drill through holes 5 in the organic film 4 using the usual photoetching method. This photoetching may be performed by either wet etching or dry etching. (Fig. 3) (4) Using A Novias sputtering equipment
A two-layer It film is formed. As shown in FIG. 4, this i-bias sputtering apparatus has an upper St electrode A installed in a grounded vacuum container 6 as A-e, and an Si substrate 1 installed on the opposing lower electrode B, and one side of the container. While Ar is injected from the lower part of the electrode and vacuum is suctioned from the other port 8, high frequency power supply voltages a and b are applied to the upper electrode A and the lower electrode, respectively.

In this case, the Si substrate is installed and a negative self-bias is applied to the electrode B in terms of direct current by the power source.

Due to this arrangement, Ar+ is not only at l of electrode A, but also at
Since the first layer A4 powder is also sputtered, the formation of the second layer Al and the etching of the first layer 8 can proceed at the same time. (FIG. 5) In this case, the state in which AA is deposited changes to either etch or deposit depending on the bias voltage, as shown in FIG. That is,
If the bias voltage is set high, the surface of the A1 layer on the sample side (lower electrode) B side will be etched, and if the bias voltage is set low, AA from the electrode A will be deposited on the bottom electrode B side.

Therefore, at first, as shown in Figure 4, under the etching conditions, the bias voltage of the power source was increased (and the electrode B
On the side, the surface of the first layer AI3 electrode in the through-hole portion is sputter-etched.

(51 pulls, then (A- & without taking out the material from the bias sputtering device) bias voltage (b)
(or the bias at the power supply a), the condition shifts to the condition where A1 is deposited as shown in FIG. 6, and A! By depositing A stone on the surface of the first layer A4'lC pole 3 on the semiconductor chip, the first layer Al wiring (electrode) 9? :Form. (@Figure 7) [Effects] According to the present invention, which has been explained in the examples above, the following effects can be obtained.

Using a bias sputter etch system, it is possible to continuously transition from sputter etch to sputter deposit in one system, eliminating the need to change the substrate placement location between etch and deposit, eliminating contamination on the A4 surface. This eliminates oxidation and through-hole resistance, making it possible to reduce through-hole resistance even in finer through-holes.

By reducing the through-hole resistance in this manner, it is possible to improve the yield of ICs and reduce the chip size.

The invention made by the present inventor has been specifically described above based on Examples. However, the present invention is not limited to the above-mentioned Examples and can be modified in various ways without departing from the gist thereof. For example, the bias power source is a high frequency power source (a, b
) Instead, the Affl deposit and etch conditions can be changed by using a DC power supply and switching them at any time.

In addition, as a wiring material, AA or Al3 alloy (A-g-8
i.

A-6-8i-Cu) or A! It may be a laminated wiring (AA/Ta/Al?) with another metal (Ta), or a gold FA (W, ws 11 ) wiring other than Al.

[Application field].

The present invention uses an organic film such as a polyimide resin.
It is most effective when applied to multilayer wiring formation VC.

The present invention can be applied to general multilayer wiring formation for ICs and LSIs.

[Brief explanation of drawings]

1 to 3, FIG. 5, and FIG. 7 are process cross-sectional views showing a part of the process of forming multilayer wiring on a semiconductor chip in one embodiment of the present invention. FIGS. 4 and 6 are process cross-sectional views showing a form in which bias sputtering is performed in one embodiment of the present invention. FIG. 8 is a curve diagram showing the relationship between bias voltage and time in bias sputtering processing. l...Si substrate, 2...Si2. Film, 3... First layer Al wiring, 4... Organic film, 5... Through hole,
6... Vacuum container, 7... Inlet, 8... Outlet, 9...
...Second layer Al wiring. Agent: Patent Attorney Katsuo Ogawa, -1, 1st
Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure

Claims (1)

[Claims] 1. When connecting lower layer wiring and upper layer wiring on a substrate through a hole in an interlayer insulating film, the substrate is placed in a bias sputtering apparatus with a hole in the interlayer insulating film. , a multilayer method characterized by first etching the surface of the lower layer interconnection (through-hole portion) under conditions that cause sputter etching, and then forming an upper layer interconnection that connects to the lower layer interconnection under conditions that the upper layer interconnection film is deposited. How to form wiring. 2. The method for forming a multilayer wiring according to claim 1, wherein a polyimide resin is used for the interlayer insulating film. 3. As the above wiring, Al or Al alloy film or Al
Alternatively, the method for forming a multilayer wiring according to claim 1, using a wiring material made of a laminated film of an Al alloy and another metal or metal compound. 4. Formation of multilayer interconnection according to claim 1, in which the sputter etching occurs by increasing the bias voltage on the electrode side on which the substrate is placed, and the depositing condition is by decreasing the same bias voltage. Method.