JP3021768B2 - Multilayer wiring semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring semiconductor device, and more particularly, to a structure of an aluminum wiring contact when a buried contact is used.

[0002]

2. Description of the Related Art A conventional technique will be described with reference to the drawings.
FIG. 4 is a longitudinal sectional view of a semiconductor chip showing a buried contact and an aluminum-based wiring layer formed by a conventional technique.

A case of a two-layer aluminum wiring structure will be described below. On a silicon substrate 101 having a first insulating layer 102 formed on its surface, an aluminum film is deposited to a thickness of 0.6 μm by sputtering and patterned into a predetermined shape by photolithography to form a first wiring layer 103 by plasma CVD. A silicon oxide film is formed on the second insulating layer 10
Then, a SOG film is formed as the third insulating layer 105, and then a contact hole is opened by photolithography.

A contact hole is buried by selective growth of tungsten silicide (buried member 106), the whole is etched back, and the buried member 106 and the SOG film (1) are etched.
05) The surface is formed to be substantially the same plane, and then an aluminum film is deposited to a thickness of 0.6 μm by a sputtering method, and is patterned into a predetermined shape by photolithography.
This is the wiring layer 109.

[0005]

The conventional aluminum-based wiring structure on the buried contact has a problem that the aluminum-based wiring layer is disconnected near the contact hole due to electromigration.

For example, when tungsten silicide is used as a buried material, the resistivity is about 1 × 10 ⁻⁴ Ω-c.
m, the diameter of the contact hole is 0.5 μm,
When the depth is 1 μm, a series resistance of about 5Ω is generated in the contact hole. When the film thickness of the first wiring layer 103 and the second wiring layer 109 is 0.6 μm and the width is 0.8 μm, if the current density is 1 × 10 ⁵ A / cm ² , the current is 0.48
mA. 0.48m for one contact hole
When the current of A flows, the loss at the embedded member 106 in the above-described contact hole is 0.012 W, and local heat generation corresponding to the amount of loss occurs. When both the first wiring layer 103 and the second wiring layer 109 are aluminum films, the contact area between the embedded member 16 that generates heat and the second wiring layer 109 is 2.0 × 10 ⁻⁹ × 2 cm ² , Assuming that the second insulating layer 104 and the third insulating layer 105 are silicon dioxide layers, the contact area between the embedded member 16 that generates heat and the silicon dioxide layer is 3.14 × 10 ⁻⁸ cm ² . (The shape of the buried member 16 is assumed to be a cylinder.) The contact area is about one order of magnitude larger for a silicon dioxide film, but the thermal conductivity coefficient is about 240 W / (m · m) for aluminum.
K), SiO ₂ is 1.5 to 2.0 W / (m · K) for SiO _2, which is about two orders of magnitude larger than aluminum, so that much of the generated heat will conduct to aluminum.

Therefore, the temperature of the aluminum wiring near the contact hole is locally increased each time the current passes, and the aluminum wiring is exposed to a temperature-accelerated state as compared with the aluminum wiring located at a position distant from the contact hole. If the wiring width and film thickness are the same, disconnection of the aluminum wiring due to electromigration will occur first near the contact hole.

Therefore, conventionally, in order to prevent disconnection due to electromigration, the aluminum wiring width is increased in the vicinity of the contact hole in a planar layout, thereby lowering the current density and preventing disconnection of aluminum. However, this method has another problem that the area required for the aluminum wiring is increased, which leads to an increase in chip size.

[0009]

According to the present invention, there is provided a multilayer wiring semiconductor device in which an upper aluminum-based wiring layer and a lower wiring layer are connected by a contact hole provided in an interlayer insulating film. It comprises a recess provided on the aluminum-based wiring layer side and a through-hole provided at the bottom of the recess, and the recess and the through-hole are filled with an aluminum-based material and a material having lower electrical conductivity than the aluminum-based material, respectively. And said
Before being embedded in the upper aluminum-based wiring layer and the depression
It is formed in a different process from the aluminum-based material.
It is characterized in that it is.

[0010]

FIG. 1A is a plan view of a semiconductor chip showing a first embodiment of the present invention, and FIG.
It is a line sectional view.

In this embodiment, an upper aluminum-based wiring layer (second wiring layer 109) and a lower wiring layer (first wiring layer 10) are used.
3) is an interlayer insulating film (the second insulating film 104 and the third insulating film 1).
In the multi-layer wiring semiconductor device connected by the contact hole provided in the stacked film with the first wiring layer 05, the above-mentioned contact hole is formed by the depression 107 provided on the second wiring layer 109 side.
a and through hole 108 provided at the bottom of recess 107a
The recess 107a and the through hole 108 are filled with an aluminum-based material (aluminum-silicon-copper alloy) and a material (tungsten silicide) having lower electric conductivity than the aluminum-based material, respectively.

Next, the manufacturing method of this embodiment will be described.

First, as shown in FIG. 2A, a 0.6 μm-thick aluminum-silicon-copper alloy film is deposited on a silicon substrate 101 having a first insulating film 102 formed on its surface by sputtering. The first wiring film 103 is patterned into a predetermined shape by photolithography. Next, a 0.2 μm silicon dioxide film is deposited by a plasma CVD method, and subsequently, an SOG film is formed to be a second insulating film 104 and a third insulating film 105, respectively.

Subsequently, as shown in FIG. 2B, a recess 107a having a depth of 200 nm is formed on the first wiring layer 103 of the third insulating film by photolithography, and a through hole 108 is formed at the bottom thereof. . Next, tungsten silicide is deposited by a selective CVD method to a thickness necessary to fill the through hole 108, the third insulating film 105 is exposed in a flat portion by anisotropic dry etching, and the bottom of the recess 107 is formed. By etching back until the surface is exposed, the through hole 108 is formed in the first embedded member 106a.

Next, an aluminum-silicon-copper alloy is deposited by a bias sputtering method until the depression 107 is sufficiently filled, and the excess is removed by isotropic dry etching or a phosphoric acid-based etchant. (C)
The recess 107 is embedded with the second embedding member 106b as shown in FIG. Subsequently, an aluminum-silicon-copper alloy is deposited to a thickness of 0.6 μm by a sputtering method, and is patterned into a predetermined shape by photolithography as shown in FIG. 1 to form a second wiring layer 109.

Since the volume of the second wiring layer is increased by the amount of the second buried member 106b in the contact hole portion between the first wiring layer 103 and the second wiring layer 109, the first buried member 106a having a low electric conductivity is provided. Can reduce the influence of heat generation.

Next, a second embodiment of the present invention will be described along its manufacturing steps.

This embodiment is suitable for a case where an intermediate wiring layer is laid out near a contact hole.

As shown in FIG. 3A, the first insulating film 10
2 and the first wiring layer 103 are formed, and the second
Insulating film 104, intermediate wiring layer 110, and third insulating film 10
3 on the silicon substrate 101 on which
As shown in (b), a recess 107b and a contact hole 108 are formed in a portion of the third insulating film between the intermediate wiring layers 110 by photolithography. At this time, the depression 107b is formed by dipping in a hydrofluoric acid-based etchant, and the contact hole 108 is formed by anisotropic dry etching.

Subsequently, tungsten silicide is deposited by a selective CVD method to a thickness required to fill the contact hole 108, and the third insulating film 105 and the recess 10 are formed.
7b is etched back, and the first embedding member 10
6a, the through hole 108 is buried.

Next, an aluminum-silicon-copper alloy is deposited to a thickness of 0.5 μm by a bias sputtering method, and the excess on the third insulating film 105 is isotropically dry-etched or
3C, the recess 107b is filled with a second embedding member 106c.
Further, an aluminum-silicon-copper alloy is deposited to a thickness of 0.6 μm by a sputtering method, and the second wiring layer 109 is formed by patterning.

Since the recess 107b having the inclined side surface is formed, it is possible to prevent the intermediate wiring layer 110 and the second embedded member from being too close to each other.

In the above, the case where the upper wiring is an aluminum-silicon-copper alloy film has been described. In addition, an aluminum-based wiring such as an aluminum metal film, an aluminum-silicon alloy film, and an aluminum-copper alloy film is generally used. The present invention can be applied to those having the following.

FIGS. 5 and 6 are plan views showing examples of a plane layout in the multilayer wiring semiconductor device according to the present invention and the prior art, respectively.

In the present invention, aluminum is buried in the recess 107 to improve electromigration resistance. Therefore, the width of the aluminum wiring as the second wiring layer 109 should be uniform in the contact hole 108 and other parts. Can be. On the other hand, conventionally, in order to improve the electromigration resistance in the vicinity of the contact hole 108, the width of the aluminum wiring as the second wiring layer 109 is increased. Here, when the minimum interval 111 is 0.
Assuming that the flat portion wiring width 113 is 8 μm and the flat portion wiring width 113 is 0.8 μm, the wiring pitch 112a is 1.6 μm,
In the case shown in FIG. 5, even if the width in the vicinity of the contact hole 108 is 0.1 μm on one side, the wiring pitch 112b is 1.8 μm.

As described above, the present invention can improve the electromigration resistance without increasing the area occupied by the aluminum wiring layer.

[0027]

As described above, according to the present invention, since the aluminum-based buried member is provided by forming a depression in the region including the contact hole portion and its vicinity of the interlayer insulating film, the contact hole portion and its vicinity are provided. In the region including, the cross-sectional area of the upper aluminum-based wiring layer is substantially increased. Therefore, the situation in which electromigration is likely to occur due to heat generation in the through-hole filled with the lower low-conductivity material is counteracted by the aforementioned reduction in current density due to the increase in cross-sectional area, and the electromigration resistance of the upper aluminum-based wiring layer is reduced. Can be made uniform without depending on the position.

[Brief description of the drawings]

FIG. 1 is a plan view (FIG. 1) showing a first embodiment of the present invention;
(A)) and sectional drawing.

FIG. 2A is a view for explaining a manufacturing method according to a first embodiment;
FIG. 3 is a cross-sectional view separately shown in FIGS.

FIGS. 3A to 3C are cross-sectional views for explaining a second embodiment of the present invention along its manufacturing process.

FIG. 4 is a sectional view showing a conventional example.

FIG. 5 is a plan view showing one example of a planar layout of the multilayer wiring semiconductor device according to the present invention.

FIG. 6 is a plan view showing an example of a planar layout of a conventional multilayer wiring semiconductor device.

[Explanation of symbols]

 101 silicon substrate 102 first insulating film 103 first wiring layer 104 second insulating film 105 third insulating film 106 embedded member 106a first embedded member 106b, 106c second embedded member 107, 107a, 107b recess 108 through hole 109 second Wiring layer 110 Intermediate wiring layer 111 Minimum spacing 112a, 112b Wiring pitch 113 Flat wiring width

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/28-21/288 H01L 21/3205-21/3213 H01L 21/768

Claims (2)

(57) [Claims] 1. A multilayer wiring semiconductor device in which an upper aluminum wiring layer and a lower wiring layer are connected by a contact hole provided in an interlayer insulating film, wherein the contact hole is provided on the upper aluminum wiring layer side. And a through hole provided at the bottom of the depression, wherein the depression and the through hole are filled with an aluminum-based material and a material having lower electrical conductivity than the aluminum-based material, respectively, and the upper aluminum-based wiring layer
And the aluminum-based material embedded in the depression
A multilayer wiring semiconductor device formed by different processes . 2. The multilayer wiring semiconductor device according to claim 1, wherein the upper aluminum-based wiring layer is made of any one of aluminum metal, aluminum-silicon alloy, aluminum-copper alloy or aluminum-silicon-copper alloy.