JPH05166373A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To decrease an operating current in ordinary read or write mode of a dynamic RAM, etc., to lower the power consumption of the dynamic RAM, etc., with an high-speed operation, to improve an information holding characteristic and to stabilize the operation of the dynamic RAM, etc. CONSTITUTION:A column selection MOSFET Qc which turns on selectively by means of column selection signals YCO-YCn is provided in a memory cell such as the dynamic RAM, etc. Drive selection MOSFETs Q1 and Q6 which turn on selectively by means of the column selection signals YC0-YCn is provided between unit amplifier circuit USAO-USAn in a sense amplifier SA and common source lines SP and SN. Ordinary read and write modes are started by a CAS-before-RAS cycle, a column selection Y address signal is inputted prior to a row selection X address signal and a refreshing mode is started by a RAS-before-CAS cycle.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a technique particularly effective for use in a dynamic RAM (random access memory) having a normal read mode, a write mode and a refresh mode. ..

[0002]

2. Description of the Related Art A memory array including word lines and bit lines arranged orthogonally and dynamic type memory cells arranged in a lattice at intersections of the word lines and bit lines, and a memory array provided corresponding to the bit lines. And a normal read mode and write mode for selectively executing a read or write operation of stored data with respect to a designated one or a predetermined number of memory cells. There is a dynamic RAM having a refresh mode for refreshing the data held in the memory cells in word line units.

The dynamic RAM is described in, for example, Japanese Patent Application Laid-Open No. 60-185291.

[0004]

In the conventional dynamic RAM, the number of memory cells in the memory array in the memory array that are simultaneously selected in the normal read mode and write mode, that is, the sense amplifiers that are simultaneously activated. The number Nn of unit amplifier circuits is set to be the same as the number Nr of unit amplifier circuits which are activated in the column direction in the refresh mode, that is, the number Nr of unit amplifier circuits which are simultaneously activated, and the storage capacity of the dynamic RAM is M When the number of bits and its refresh cycle number are Nrs, Nn = Nr = M / Nrs. The Nn memory cells that are simultaneously selected are normally arranged in an address space in the column direction, and a column address strobe signal CASB (here, a so-called inversion signal that is selectively brought to a low level when it is enabled). Etc. are designated by adding B to the end of the name. The same applies hereinafter), and are further selectively designated according to the Y address signal supplied in synchronization with the falling edge.

However, it has become clear by the present inventors that the dynamic RAM as described above has the following problems as its capacity and speed are increased. That is, the number Nn of memory cells that are simultaneously selected in the normal read mode and write mode is such that the read or write operation of the stored data is finally executed only for one or several memory cells. Despite this, for example, when the memory capacity M of the dynamic RAM is 64 megabits and the refresh cycle number Nrs is 4096 cycles, 16384
Reach even individual. Therefore, the charge and discharge currents applied to each bit line via the unit amplifier circuit increase, which hinders the reduction in power consumption of the dynamic RAM and increases the operating current of the dynamic RAM, thereby increasing the substrate. The temperature rises, and the information retention characteristic of the memory cell deteriorates.

An object of the present invention is to provide a semiconductor memory device such as a dynamic RAM in which the operating current in the normal read mode and write mode is reduced. Another object of the present invention is to improve the information retention characteristics of a dynamic RAM or the like and to speed up the operation thereof.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. That is, a column selection MOSFET that is selectively turned on according to a column selection signal is provided in a memory cell such as a dynamic RAM, and the column selection signal is provided between each unit amplifier circuit of a sense amplifier and a common source line according to the column selection signal. Drive selection MOSFET selectively turned on
To provide. In addition, the normal read mode and write mode are activated by the CAS before RAS cycle, the Y address signal for column selection is input prior to the X address signal for row selection, and the refresh mode is set to RAS.
Start by before CAS cycle.

[0009]

According to the above means, since the specifications in the normal read mode and the write mode can be set independently of the specifications in the refresh mode, the column direction of the memory cells that are simultaneously selected in the normal read mode and the write mode. , That is, the number of unit amplifier circuits of the sense amplifiers activated at the same time can be reduced to one or several. As a result, the operating current in the normal read mode and write mode is significantly reduced, and the dynamic R
It is possible to achieve low power consumption and high speed of AM and the like, suppress heat generation on the semiconductor substrate surface, and improve the information retention characteristics of the memory cell. Further, when a plurality of memory cells are simultaneously selected, by avoiding the memory cells arranged at adjacent column addresses, the coupling noise between the bit lines can be suppressed and the operation of the dynamic RAM or the like can be stabilized. ..

[0010]

FIG. 1 is a block diagram of a first embodiment of a dynamic RAM to which the present invention is applied. Further, FIG. 2 shows a circuit diagram of an embodiment of the memory array MARY and the sense amplifier SA included in the dynamic RAM of FIG. Further, FIG. 3 shows a signal waveform diagram of one embodiment in the normal read mode or write mode of the dynamic RAM of FIG. 1, and FIG. 4 shows a signal waveform diagram of one embodiment in the refresh mode. Has been done. Based on these drawings, an outline of the structure and operation of the dynamic RAM of this embodiment and its features will be described. The circuit elements of FIG. 2 and the circuit elements of each block of FIG. 1 are formed on a single semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique. Further, in FIG. 1, a MOSFET (metal oxide semiconductor field effect transistor. In this specification, a MOSFET (metal oxide semiconductor type field effect transistor) is generally referred to as an insulated gate field effect transistor) in which an arrow is added to its channel (back gate) portion. Is a P-channel type, N-channel MOSFE without arrow
It is shown separately from T.

The dynamic RAM of this embodiment has a read mode and a write mode for selectively executing a read or write operation of stored data for one designated memory cell, and data held in the memory cell. And a refresh mode for refreshing in a word line unit.

In a normal read or write mode,
In the dynamic RAM, as shown in FIG. 3, the column address strobe signal CASB is set to the low level before the row address strobe signal RASB.
Fired by the S-before RAS cycle. At this time, the dynamic RAM has the write enable signal W.
The read or write mode is selectively set according to the EB. Further, Y address signals AY0 to AYi for designating the Y address Yq, for example, are supplied to the address input terminals A0 to Ai in synchronization with the falling edges of the column address strobe signal CASB, and the row address strobe signal RASB rises. For example, an X address signal AX0 for designating the X address Xp in synchronization with the falling edge
~ AXi is supplied. In the normal read or write mode, the cycle time t _RC of the dynamic RAM is relatively short, about 110 ns (nanosecond: 10 ⁻⁹ seconds).

On the other hand, in the refresh mode, the dynamic RAM is activated by the RAS before CAS cycle in which the row address strobe signal RASB is set to the low level prior to the column address strobe signal CASB, as shown in FIG. At this time,
To the address input terminals A0 to Ai, for example, the X address Xp, that is, the word line W to be refreshed is synchronized with the falling edge of the row address strobe signal RASB.
Only X address signals AX0 to AXi for designating p are supplied. In this refresh mode, the cycle time t _RC of the dynamic RAM is 1 μs (microsecond: 10 ⁻⁶⁾ depending on the information retention characteristics of the memory cell.
Seconds) is relatively long.

In FIG. 1, the basic structure of the dynamic RAM of this embodiment is a memory array MARY which occupies most of the semiconductor substrate surface. As shown in FIG. 2, the memory array MARY has m + 1 word lines W0 to Wm arranged in parallel in the vertical direction and n + 1 sets of complementary bit lines B0 arranged in parallel in the horizontal direction.
* To Bn * (here, for example, the non-inverted bit line B0 and the inverted bit line B0B are collectively denoted by an asterisk such as a complementary bit line B0 *. The same applies hereinafter). An information storage capacitor Cs, a row selection MOSFET Qr, and a column selection MOSFET are provided at the intersections of these word lines and complementary bit lines.
(M + 1) × (n + 1) dynamic memory cells of Qc are arranged in a grid.

Of these, the gates of the row selection MOSFETs Qr of the n + 1 memory cells arranged in the same row are commonly coupled to the corresponding word lines W0 to Wm. Also, the column selection MO of m + 1 memory cells arranged in the same column
The drains of the SFETs have corresponding complementary bit lines B0 * ...
It is commonly coupled to a non-inverted or inverted signal line of Bn *, and corresponding column selection signals YC0 to YCn (first column selection signal) are commonly supplied to the gates thereof from the Y address decoder YD. A predetermined plate voltage HV is commonly supplied to the other electrodes of the information storage capacitors Cs of all the memory cells forming the memory array MARY. Here, the column selection signals YC0 to YCn are not particularly limited, but are set to a low level like the ground potential of the normal circuit, and when the dynamic RAM is in the selected state in the normal read or write mode, it is shown in FIG. As described above, it is alternatively set to the high level at a predetermined timing and in accordance with the Y address signals AY0 to AYi. Dynamic RAM
When the column selection signals YC0 to YCn are selected in the refresh mode, the column selection signals YC0 to YCn are simultaneously set to a high level at a predetermined timing as shown in FIG.

The word lines W0 to Wm forming the memory array MARY are coupled to the X address decoder XD and are alternatively set to the selected state. The X address decoder XD is supplied with the internal address signals X0 to Xi of i + 1 bits from the X address buffer XB and the internal control signal XDG from the timing generation circuit TG. The X address buffer XB has address input terminals A0 to Ai.
X address signals AX0 to AXi are time-divisionally supplied through the timing control circuit TG and the internal control signal XL.
Is supplied. Here, as shown in FIGS. 3 and 4, the internal control signal XDG is set to a normal low level, the row address strobe signal RASB is set to a low level, and a predetermined time has elapsed since the dynamic RAM was selected. At this time, it is selectively set to the high level.

The X address decoder XD is selectively activated by setting the internal control signal XDG to a high level. In this operating state, the X address decoder XD decodes the internal address signals X0 to Xi,
The corresponding word lines W0 to Wm of the memory array MARY are selectively set to the high level selected state. The X address buffer XB converts the X address signals AX0 to AXi supplied via the address input terminals A0 to Ai into the internal control signal X.
The address is fetched and held in accordance with L, and internal address signals X0 to Xi are formed based on these X address signals and supplied to the X address decoder XD.

When, for example, the word line Wp is alternatively set to the high level by the X address decoder XD, the row selection MOSFET Qr of the corresponding n + 1 memory cells is turned on in the memory array MARY. At this time,
When the dynamic RAM is selected in the normal read or write mode and, for example, the column selection signal YCq is alternatively set to the high level, the column selection MOSFET Qc of the corresponding m + 1 memory cells is turned on in the memory array MARY. To be in a state. As a result, the row selection MOSFET Qr and the column selection MOSFET Qc are simultaneously turned on in one memory cell arranged at the intersection of the high level word line Wp and the column selection signal YCq. As a result, as shown in FIG. 3, only the minute read signal of this memory cell is alternatively output to the corresponding complementary bit line Bq *. On the other hand, at this time, the dynamic RAM
Are selected in the refresh mode and the column selection signal YC is selected.
When 0 to YCn are simultaneously set to the high level, in the memory array MARY, the column selection MOSFs of all memory cells are selected.
ETQc is turned on all at once. As a result, in the n + 1 memory cells coupled to the high-level word line Wp, the row selection MOSFET Qr and the column selection M are selected.
The OSFET Qc is simultaneously turned on. as a result,
As shown in FIG. 4, minute read signals of these memory cells are simultaneously output to the corresponding complementary bit lines B0 * to Bn *.

Next, the complementary bit lines B0 * to Bn * forming the memory array MARY are, as shown in FIG.
It is coupled to the corresponding unit circuit of the sense amplifier SA. These unit circuits are P-channel MOSFET Q2 and N-channel MOSFET Q4 or P-channel M.
It includes unit amplifier circuits USA0 to USAAn in which a pair of CMOS inverters composed of an OSFET Q3 and an N-channel MOSFET Q5 are cross-coupled. The non-inverting and inverting input / output nodes of each unit amplifier circuit are connected to the memory array MAR.
The corresponding complementary bit lines B0 * to Bn * of Y are respectively coupled to the non-inverted or inverted signal lines. Further, the commonly-coupled sources of the P-channel MOSFETs Q2 and Q3 constituting these unit amplifier circuits are coupled to the common source line SP (first common source line) via the corresponding P-channel type drive selection MOSFET Q1. , N-channel MOSFETs Q4 and Q5 are commonly coupled sources corresponding to N-channel drive select MOSFETs Q
6 is coupled to the common source line SN (second common source line). Here, the common source lines SP and S
As shown in FIGS. 3 and 4, N is an intermediate level between the power supply voltage and the ground potential of the normal circuit and corresponds to the minute read signal of the memory cell coupled to the selected word line of the memory array MARY. When they are established on the complementary bit lines, they are set to a high level such as the power supply voltage of the circuit or a low level such as the ground potential of the circuit. The gate of the drive selection MOSFET Q6 is supplied with the corresponding column selection signals YC0 to YCn from the Y address decoder YD, and the gate of the P-channel type drive selection MOSFET Q1 is supplied with the inverter N1 of the corresponding column selection signals YC0 to YCn. An inverted signal is supplied.

As a result, the unit amplifier circuits USA0 to USAn of the sense amplifier SA are connected to the common source lines SP and S.
It is selectively activated on condition that the power supply voltage and the ground potential of the circuit are supplied to N and the corresponding column selection signals YC0 to YCn are set to the high level. As described above, the column selection signals YC0 to YCn are dynamic RA
When M is selected in the normal read or write mode, the internal address signals Y0 to Y0
According to Yi, it is alternatively set to the high level, and when the dynamic RAM is selected in the refresh mode, it is simultaneously set to the high level. However, when the dynamic RAM is selected in the normal read or write mode, in the sense amplifier SA, for example, only the unit amplifier circuit USAq corresponding to the high level column selection signal YCq is selectively activated, and the dynamic When the type RAM is selected in the refresh mode, all the unit amplifier circuits USA0 to USAAn are activated all at once.

Unit amplifier circuit USA0 of sense amplifier SA
~ Memory array MARY when USAn is activated
The minute read signals output to the corresponding complementary bit lines B0 * to Bn * of the corresponding unit amplifier circuits USA0 to U
The signal is amplified by SAn, and becomes a high level or low level binary read signal as shown in FIGS. At this time, a charge or discharge current is supplied to the non-inverted and inverted signal lines of the complementary bit lines B0 * to Bn * via the common source line SP or SN and the corresponding unit amplifier circuits USA0 to USAAn. As described above, when the dynamic RAM is selected in the normal read or write mode, the complementary bit lines B0 * ...
A read signal of the memory cell is alternatively output to Bn *, and the unit amplifier circuits USA0 to USAn are selectively activated. Therefore, the operating current of the dynamic RAM in the normal read or write mode is significantly reduced, and the power consumption of the dynamic RAM is reduced. The dynamic RA is reduced by reducing the operating current in the normal read or write mode.
The amount of heat generated by M on the surface of the semiconductor substrate is correspondingly reduced, which improves the information retention characteristics of the memory cell. In addition, the read signal of the memory cell is the complementary bit line B0 * to
The complementary bit lines adjacent to the selected complementary bit line are both fixed to the intermediate level by being selectively output to Bn * and by selectively activating the unit amplifier circuits USA0 to USAn of the sense amplifier SA. To be done. As a result, the coupling noise between the complementary bit lines is suppressed, and thereby the read and write operations of the dynamic RAM are also stabilized.

The sense amplifier SA further includes an N-channel type n + 1 pair of switch MOSFs provided corresponding to the complementary bit lines B0 * to Bn * of the memory array MARY.
Includes ETQ7 and Q8. These switch MOSFE
One of the Ts is coupled to the non-inverted or inverted signal line of the corresponding complementary bit line B0 * to Bn *, and the other is commonly coupled to the non-inverted or inverted signal line of the complementary common data line CD *. The gates of the switch MOSFETs of each pair are commonly coupled, and corresponding column selection signals YS0 to YSn (second column selection signal) are supplied from the Y address decoder YD. Here, the column selection signals YS0 to YSn are normally set to a low level, and when the dynamic RAM is set to a normal read or write mode, as shown in FIG. 3, the column selection signals YC0 to YCn are slightly delayed. Moreover, it is alternatively set to the high level in accordance with the Y address signals AY0 to AYi. When the dynamic RAM is set to the refresh mode, the column selection signals YS0 to YSn are set as shown in FIG.
All remain low level, as shown in.

The dynamic RAM is set to the selected state in the normal read or write mode and the column selection signals YS0 to YS are selected.
When n is alternatively set to the high level, the sense amplifier S
At A, the corresponding switch MOSFETs Q7 and Q8 are selectively turned on. As a result, the memory array M
Complementary bit lines B0 * to Bn * corresponding to ARY, that is, unit amplifier circuits USA0 to U corresponding to sense amplifier SA.
SAn and the complementary common data line CD * are selectively connected.

The Y address decoder YD has an i + 1 bit internal address signal Y0 from the Y address buffer YB.
To Yi, and the timing generation circuit TG supplies the internal control signals MD and YDG1 and YDG2. Further, the Y address buffer YB has Y address signals AY0 to AYi via address input terminals A0 to Ai.
Are supplied in a time division manner, and the internal control signal YL is supplied from the timing generation circuit TG. Here, the internal control signal M
As shown in FIGS. 3 and 4, D is normally set to the low level, and when the dynamic RAM is selected in the refresh mode, it is selectively set to the high level at a relatively early timing. On the other hand, the internal control signal YDG1
Is set to a high level at a predetermined timing when the dynamic RAM is selected in the normal read or write mode, and the internal control signal YDG2 is selected in the normal read or write mode for the dynamic RAM. When it is turned on, it is set to the high level with some delay from the internal control signal YDG1.

The Y address decoder YD is selected on condition that the internal control signal MD is at the low level when the internal control signal YDG1 is at the high level, in other words, the dynamic RAM is selected in the normal read or write mode. The column address signals YC0 to YCn are decoded by decoding the internal address signals Y0 to Yi on condition that they are brought into the state.
Is alternatively set to the high level. Then, the internal control signal Y
When DG2 is set to high level, the internal signals Y0 to Y
According to the decoding result of i, the column selection signals YS0 to YSn
Is alternatively set to the high level. On the other hand, dynamic type R
When the AM is selected in the refresh mode and the internal control signal MD is set to the high level, the Y address decoder Y
D simultaneously sets the column selection signals YC0 to YCn to the high level regardless of the internal address signals Y0 to Yi.

The Y address buffer YB is supplied with Y address signal AY via address input terminals A0 to Ai.
0 to AYi are fetched and held according to the internal control signal YL, and internal address signals Y0 to Yi are formed based on these Y address signals, and the Y address decoder Y
Supply to D.

Next, complementary common data line CD * is coupled to data input / output circuit IO. Data input / output circuit IO
Includes a write amplifier and a main amplifier, and a data input buffer and a data output buffer. Of these, the input terminal of the write amplifier is coupled to the output terminal of the data input buffer, and the output terminal is connected to the complementary common data line CD.
Bound to * Further, the input terminal of the main amplifier is coupled to the complementary common data line CD *, and the output terminal thereof is coupled to the input terminal of the data output buffer. The input terminal of the data input buffer is coupled to the data input terminal Din, and the output terminal of the data output buffer is coupled to the data output terminal Dout.

The data input buffer of the data input / output circuit IO fetches the write data supplied via the data input terminal Din and transmits it to the write amplifier when the dynamic RAM is in the normal write mode. This write data is converted into a predetermined complementary write signal by the write amplifier, and is written in the selected one memory cell of the memory array MARY via the complementary common data line CD *. On the other hand, the main amplifier of the data input / output circuit IO is output from one selected memory cell of the memory array MARY via the complementary common data line CD * when the dynamic RAM is set to the normal read mode. The read signal is further amplified and transmitted to the data output buffer. This read signal is sent to the outside from the data output buffer via the data output terminal Dout.

The timing generation circuit TG forms the above various internal control signals based on the row address strobe signal RASB, the column address strobe signal CASB, and the write enable signal WEB which are externally supplied as a start control signal, and dynamically Supply to each part of the type RAM.

By applying the present invention to a semiconductor memory device such as a dynamic RAM as shown in this embodiment, the following operational effects can be obtained. (1) A column selection MOSF which is selectively turned on in accordance with a column selection signal in a memory cell such as a dynamic RAM.
ET is provided, and a drive selection MOSFET that is selectively turned on in accordance with the column selection signal is provided between each unit amplifier circuit of the sense amplifier and the common source line. In addition, the normal read mode and write mode are set to CAS Before R
It is activated by the AS cycle, the Y address signal for column selection is input prior to the X address signal for row selection, and the refresh mode is activated by the RAS before CAS cycle. As a result, the specifications in the normal read mode and write mode can be set independently of the specifications in the refresh mode, so that the number of memory cells in the column direction that are simultaneously selected in the normal read mode and write mode, that is, activated simultaneously. It is possible to reduce the number of unit amplifier circuits of the sense amplifier to be reduced to one or several.

(2) According to the above item (1), the operating current in the normal read mode and the write mode can be significantly reduced, and the power consumption and speed of the dynamic RAM can be reduced. .. (3) According to the above item (2), the amount of heat generated on the surface of the semiconductor substrate can be reduced, and the information retention characteristics of the memory cell can be improved. (4) According to the above item (1), it is possible to suppress the coupling noise between the bit lines and selectively stabilize the operation of the dynamic RAM or the like by selectively setting the bit lines. Be done.

The invention made by the present inventor has been specifically described above based on the embodiments. However, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in this embodiment, only one memory cell is selected and only one corresponding unit amplifier circuit is activated. However, for example, four memory cells are simultaneously selected and corresponding four units are selected. The amplifier circuit can be activated at the same time. In this case, as four memory cells that are simultaneously selected, those that are coupled to adjacent complementary bit lines are avoided to suppress coupling noise between bit lines,
The stable operation of the dynamic RAM can be maintained. In addition, in this embodiment, the nibble mode and the like can be easily realized by sequentially shifting and executing the read or write operation of the stored data for the selected four memory cells.

Switching between the number of selected memory cells in the normal read or write mode and the number of activated unit amplifier circuits and the selected number in the refresh mode is performed, for example, as shown in FIG. 5, a plurality of memory mats MAT0.
To MATs are provided, and these memory mats are provided with mat selection signals M0 to M output from the memory mat selection circuit MS.
It can also be realized by selectively activating according to s. In this case, the mat selection signals M0 to Ms are alternatively set to the high level according to the internal address signals Yk + 1 to Yi when the dynamic RAM is selected in the normal read or write mode, and the dynamic RAM is refreshed. When the selected state is selected, the signal is simultaneously set to the high level regardless of these internal address signals.
In this embodiment, it is not necessary to provide a column selection MOSFET in each memory cell, and the chip area of the dynamic RAM can be reduced.

Further, the dynamic RAM does not require the address multiplex method, and the block configuration of the dynamic RAM shown in FIGS. 1 and 5 is not restricted by these embodiments.
Further, the specific configurations of the memory array MARY and the sense amplifier SA shown in FIGS. 2 and 3 and 4, the combination of the start control signal and the internal control signal, the polarity of the power supply voltage, the conductivity type of the MOSFET and the like are various. The embodiment of can be adopted.

In the above description, the case where the invention made by the present inventor is mainly applied to the dynamic RAM which is the field of application which is the background of the invention has been described.
However, the present invention is not limited to this, and can be applied to, for example, a multi-port memory having a dynamic RAM as a basic configuration and various digital integrated circuit devices including these memories. The present invention can be widely applied to a semiconductor memory device having at least a normal read / write mode and a refresh mode, and a semiconductor device incorporating such a semiconductor memory device.

[0036]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, a column selection MOSFET that is selectively turned on according to a column selection signal is provided in a memory cell such as a dynamic RAM, and the column selection signal is provided between each unit amplifier circuit of a sense amplifier and a common source line according to the column selection signal. Drive selection MOSFE selectively turned on
Provide T. In addition, the normal read mode and write mode are activated by the CAS before RAS cycle, the Y address signal for column selection is input prior to the X address signal for row selection, and the refresh mode is set to RA.
It is activated by the S-before CAS cycle. As a result, the specifications in the normal read mode and write mode can be set independently of the specifications in the refresh mode, so that the number of memory cells in the column direction that are simultaneously selected in the normal read mode and write mode, that is, activated simultaneously. Number of unit amplifier circuits of sense amplifier
It can be reduced to one or several. As a result, the operating current in the normal read mode and the write mode can be reduced, power consumption and speed of the dynamic RAM can be reduced, heat generation on the semiconductor substrate surface can be suppressed, and information of the memory cell can be retained. The characteristics can be improved. Further, when a plurality of memory cells are simultaneously selected, avoiding the memory cells arranged at adjacent column addresses can suppress the coupling noise between the bit lines and stabilize the operation of the dynamic RAM or the like. ..

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a dynamic RAM to which the present invention is applied.

2 is a circuit diagram showing an embodiment of a memory array and a sense amplifier included in the dynamic RAM of FIG.

3 is a signal waveform diagram showing an example of a normal read mode and a normal write mode of the dynamic RAM of FIG.

FIG. 4 is a signal waveform diagram showing an example of a refresh mode of the dynamic RAM of FIG.

FIG. 5 is a block diagram showing a second embodiment of a dynamic RAM to which the present invention is applied.

[Explanation of symbols]

MARY ... Memory array, SA ... Sense amplifier, XD ... X address decoder, YD ... Y address decoder, XB ... X address buffer, YB.
..Y address buffer, IO ... Data input / output circuit, TG ... Timing generation circuit W0-Wm ...
Word line, B0 * to Bn * ... Complementary bit line, Cs
..Information storage capacitors, Qr ... Row selection MOSFE
T, Qc ... Column selection MOSFET, USA0 to USA
n ... Unit amplifier circuit, Q1 to Q3 ... P channel MOSFET, Q4 to Q8 ... N channel MOSF
ET. MAT0 to MATs ... Memory mat, MAR
Y0 to MARYs ... Memory array, SA0 to SAs
... Sense amplifier, XD0 to XDs ... X address decoder, YD0 to YDs ... Y address decoder,
MS: Memory mat selection circuit.

Claims (3)

[Claims] 1. A memory array including word lines and bit lines arranged orthogonally and dynamic memory cells arranged in a lattice at intersections of the word lines and bit lines, and a memory array corresponding to the bit lines. A sense amplifier including a unit amplifier circuit provided, and the number of the dynamic type memory cells in the column direction in the selected state in the normal read mode or the write mode and the number of the unit amplifier circuits in the activated state are A semiconductor memory device, which is different from the number of the dynamic type memory cells in the column direction in the selected state and the number of the unit amplifier circuits in the activated state in the refresh mode. 2. Each of the dynamic memory cells includes a column selection MOSFET that is selectively turned on according to a first column selection signal, and the sense amplifier includes:
A drive selection MOSFET that is provided between each of the unit amplifier circuits and the first and second common source lines and that is selectively turned on in accordance with the first column selection signal, and the bit line. A switch MOSFET that is provided and is selectively turned on in accordance with a second column selection signal that is formed later than the first column selection signal to selectively connect a designated bit line and a common data line. 2. The semiconductor memory device according to claim 1, further comprising: 3. The read mode and write mode are:
The CAS before R in which the column address strobe signal is set to the low level prior to the row address strobe signal.
3. The refresh mode is activated by an AS cycle, and the refresh mode is activated by a RAS before CAS cycle in which a row address strobe signal is set to a low level prior to a column address strobe signal. Semiconductor memory device.