JPH1131384A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stabilize the operation of a dynamic type RAM and the like adopting a hierarchical word line system and a negative word line system without degrading high speed performance and low cost performance by increasing the speed of level variation of a sub-word line in which internal voltage of a negative potential is its final potential without increasing supply capability of an internal voltage generating circuit, and suppressing potential variation of internal voltage associated with the level variation of the sub-word line. SOLUTION: When a sub-word line SWL0 and the like making high voltage VHH its selection level is transmitted to its non-selection level, that is, internal voltage VLL of a negative potential, after its potential is first varied making a potential which is externally supplied and for which sufficient supply wirings are prepared, for example, ground potential VSS as a target potential, a non- selection level having small supply capability, that is, a negative potential of internal voltage VLL is varied as a target potential utilizing a period in which pre-charge operation of complementary bit lines B0*-Bm* is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a dynamic RAM (random access memory) employing a hierarchical word line system and a negative word line system, and particularly for use in stabilizing the operation thereof. Regarding effective technology.

[0002]

2. Description of the Related Art A memory array including word lines and complementary bit lines arranged orthogonally and dynamic memory cells arranged in a lattice at the intersections of these word lines and complementary bit lines is a basic component thereof. There is a dynamic RAM. Also, by setting the low level of the read signal on the complementary bit line after amplification to the ground potential VSS and the non-selection level of the word line to a predetermined negative potential lower than the ground potential VSS, the leakage current of the memory cell is suppressed,
A so-called negative word line system capable of improving the refresh cycle of a dynamic RAM is known.

On the other hand, as one means for increasing the speed of a dynamic RAM or the like, a memory array and its immediate peripheral portion are divided into a plurality of memory mats at least in the direction in which word lines extend, and word lines are divided into main word lines and sub-words. There is a so-called hierarchical word line system in which lines are hierarchized. In the dynamic RAM adopting the hierarchical word line system, for example, a sub-word line driving circuit for selectively setting a corresponding sub-word line to a selection level based on a main word line and a mat selection signal is provided.

[0004]

Prior to the present invention, the present inventors have developed a dynamic RAM which employs the above-mentioned hierarchical word line system and adopts a negative word line system. Faced the point. That is, as illustrated in FIG. 6, the dynamic RAM includes a sub-word line drive circuit SWD0 provided corresponding to the sub-memory array SML0, and the sub-word line drive circuit includes the sub-word line SWL0 and the sub-word line SWL0 of the sub-memory array SML0. It includes unit sub-word line drive circuits UWD0 and UWD1 provided corresponding to SWL1. The unit sub-word line drive circuits UWD0 and UWD1 are connected to the sub-word line SWL0 or SW corresponding to the mat select signal line RX0.
P-channel type driving MOSF provided between L1 and L1
ET (Metal Oxide Semiconductor Field Effect Transistor; in this specification, a MOSFET is used as a generic term for an insulated gate field effect transistor) P5 or P6, and between the sub-word line SWL0 or SWL1 and the internal voltage supply point VLL N-channel type drive MOSFET NE provided in
Or NF. Drive MOSFET P5 forming unit sub-word line drive circuits UWD0 and UWD1
And NE and the gates of P6 and NF are commonly coupled to the corresponding main word line MW0 or MW1.

The internal voltage VLL is generated by an internal voltage generating circuit built in the dynamic RAM, and has a negative potential such as -1.0 (volt) V, for example. The mat selection signal RX0 is, for example, + 3.8V
Is set to the selected level, and 0V, that is, the ground potential VSS is set to the non-selected level. further,
The main word lines MW0 and MW1 are connected to the internal voltage VLL.
Is the selected level, and the high voltage VHH is the non-selected level.

When the dynamic RAM is set to the non-selected state, the mat select signal RX0 is set to a non-selected level such as the ground potential VSS, and the main word lines MW0 and MW are set.
1 are both set to a non-selection level such as the high voltage VHH. Therefore, in the unit sub-word line drive circuits UWD0 and UWD1 of the sub-word line drive circuit SWD0, the drive M
OSFETs P5 and P6 are turned off and drive MOS
When the FETs NE and NF are turned on, the sub-word lines SWL0 and SWL1 of the sub-memory array SML0 become
Both are set to a non-selection level like the internal voltage VLL.
At this time, in the sense amplifier SA (not shown), the complementary bit line B0 * (here, the non-inverted bit B0T and the inverted bit line B0B are put together like a complementary bit line B0 *)
And is represented by Further, a so-called non-inverted signal or the like which is selectively set to a high level when it is set to a valid level is indicated by adding a T to the end of its name, and selectively set to a low level when set to a valid level. Inverted signals and the like to be performed are indicated by adding B to the end of their names. The same applies hereinafter), and the non-inverted and inverted signal lines are set to a precharge potential such as +1.0 V.

On the other hand, when the dynamic RAM is selected, the mat select signal RX0 corresponding to the designated memory mat is set to a selection level such as the high voltage VHH at a predetermined timing, and the designated row address is set to the designated level. The corresponding main word line MW0 is set to a selection level such as internal voltage VLL. At this time, the unspecified main word line MW1 is kept at an unselected level such as the high voltage VHH, and the precharge operation for the complementary bit line B0 * is stopped in the sense amplifier SA (not shown). In the unit sub-word line drive circuit UWD0 of the sub-word line drive circuit SWD0, the drive MOSFET P5 is turned on in response to the selection level of the main word line MW0, and the drive MO
SFETNE is turned off. For this reason, the sub word line SWL0 is set to a selection level such as the high voltage VHH,
The address selection MOSFET Qa of the memory cell coupled to the sub-word line SWL0 of the sub-memory array SML0 is turned on, and a minute read signal according to the retained data is output to the corresponding complementary bit line B0 *. These minute read signals are respectively amplified by the corresponding unit amplifier circuits of the sense amplifier SA.
This is a binary read signal in which 0V is at a high level and the ground potential VSS is at a low level.

Next, when the dynamic RAM is returned from the selected state to the non-selected state, the mat selection signal RX0 is returned to a non-selection level such as the ground potential VSS, and the main word line MW0 is also changed to the internal voltage VLL. Returned to unselected level. Therefore, in the unit sub-word line driving circuit UWD0 of the sub-word line driving circuit SWD0, the driving MOSF
ETP5 is turned off, and the drive MOSFET is replaced.
NE is turned on, and sub-word line SWL0 is set to a non-selection level such as internal voltage VLL. In the sense amplifier SA, the precharge operation for the complementary bit line B0 * is restarted, and the non-inverted and inverted signal lines are set to the precharge potential.

However, as the capacity and integration of the dynamic RAM increase, the parasitic capacitance Cw of the sub-word line SWL0 increases, and at the time of transition from the selected level to the non-selected level, the supply source of the internal voltage VLL is increased. Causes a relatively large charge flow. As described above, the internal voltage VLL is formed by a built-in internal voltage generation circuit, and is distributed to the sub-word line drive circuit SWD0 and the like via the supply wiring arranged over a relatively long distance in the semiconductor substrate. Therefore, when the internal voltage generating circuit does not have a sufficient supply capability and the width of the supply line is not sufficiently large, the potential of the internal voltage VLL is increased by a relatively large charge flow starting from the parasitic capacitance Cw of the sub-word line SWL0. There is a possibility that the voltage temporarily rises and exceeds the ground potential VSS and becomes a positive potential. As a result, the potential of, for example, the sub-word line SWL1, which should be in the non-selected state, rises, and the address selection MOSFET Qa of the memory cell coupled thereto becomes weakly on, deteriorating the disturb characteristics of the dynamic RAM.

On the other hand, if the supply capacity of the internal voltage generation circuit for generating the internal voltage VLL is increased and the width of the supply wiring is made sufficiently large in order to cope with this, the required layout area of the related portion increases. The chip size becomes large, and cost reduction of the dynamic RAM is hindered. Further, if the sub-word line SWL0 is slowly changed from the selection level, ie, the high voltage VHH, to the non-selection level, ie, the internal voltage VLL, and the floating of the internal voltage VLL is suppressed, the time required to reach the non-selection level increases. The cycle time of the dynamic RAM becomes slow.

An object of the present invention is to speed up a level change of an internal signal line having an internal voltage generated by the internal voltage generation circuit as its ultimate potential without increasing the supply capability of the internal voltage generation circuit. An object of the present invention is to suppress a potential change of an internal voltage due to a level change of a signal line. Another object of the present invention is to stabilize the operation of a dynamic RAM or the like employing a hierarchical word line system and a negative word line system without impairing its high speed and low cost.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0013]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, in a dynamic RAM or the like employing a hierarchical word line system and a negative word line system, when a sub-word line having a predetermined high voltage as its selection level is transited to a non-selection level of a predetermined negative potential, its potential is changed to: First, a ground potential, which is externally supplied and a sufficient supply wiring is prepared, is changed as a target potential, and then a non-selection level of a negative potential having a small supply capability is used by utilizing a period in which the precharge operation of the complementary bit line is performed. Is changed as a target potential.

According to the above means, the selection level of the sub-word line is first changed to the ground potential at a relatively high speed via the ground potential supply path having a large supply capacity, and then the negative level of the relatively small supply capacity is changed. It can be slowly changed to the non-selection level via the potential supply path.
As a result, the level change of the sub-word line in which the negative potential formed by the internal voltage generating circuit is set to the non-selection level is accelerated without increasing the supply capability of the internal voltage generating circuit for generating the negative potential, and It is possible to suppress a potential change of the negative potential due to the level change. This makes it possible to stabilize the operation of a dynamic RAM or the like employing the hierarchical word line system and the negative word line system without impairing its high speed and low cost.

[0015]

FIG. 1 is a block diagram showing one embodiment of a dynamic RAM to which the present invention is applied. First, an outline of the configuration and operation of the dynamic RAM according to this embodiment will be described with reference to FIG. FIG.
The circuit elements constituting each block are not particularly limited, but are formed on a single semiconductor substrate surface such as single crystal silicon by a known CMOS (complementary MOS) integrated circuit manufacturing technique.

Referring to FIG. 1, the dynamic RAM of this embodiment has a memory array MARY arranged so as to occupy most of the surface of a semiconductor substrate as its basic component. Memory array MARY includes a predetermined number of word lines arranged in parallel in the horizontal direction in the figure, and a predetermined number of sets of complementary bit lines arranged in parallel in the vertical direction. At the intersections of these word lines and complementary bit lines, a large number of dynamic memory cells composed of information storage capacitors and address selection MOSFETs are arranged in a grid.

In this embodiment, the memory array MAR
Y represents eight memory mats MAT0 to MAT7 including a sense amplifier SA and a Y address decoder YD to be described later.
These memory mats are divided into mat selection signals RXP0 to RXP supplied from a mat selection circuit MS.
7, are selectively activated according to RXN0 to RXN7 and PA0 to PA7. Dynamic type R
AM adopts a hierarchical word line system, and a memory array MARY
Are hierarchized into a pair of main word lines shared by all memory mats and sub-word lines provided for each memory mat. Therefore, each of the memory mats MAT0 to MAT7 has a main word line and mat select signals RXP0 to RXP7 and R
A sub-word line driving circuit is provided which receives XN0 to RXN7 and selectively sets a specified sub-word line of each memory mat to a selected level. The specific structure of the hierarchical word line structure and the memory mats MAT0 to MAT7 will be described later in detail.

The word lines constituting the memory array MARY, that is, the main word lines of each pair, have X on the left side thereof.
It is coupled to an address decoder XD and is alternatively set to a predetermined selection level. The X address decoder XD has, for example, i-2 except the upper 3 bits from the X address buffer XB.
Bit complementary internal address signals X0 * to Xi-3 * are supplied. Further, the X address buffers AX have X address signals AX0 through AX through address input terminals A0 through Ai.
AXi are supplied in a time-division manner and the timing generation circuit TG
Supplies the internal control signal XL.

The X address buffer XB is provided with an X address signal AX supplied through address input terminals A0 to Ai.
0 to AXi are captured and held according to the internal control signal XL, and complementary internal address signals X0 * to Xi * are formed based on these X address signals. this house,
Upper 3 bits of complementary internal address signals Xi-2 * to Xi
* Is supplied to the mat selection circuit MS, and the remaining i-2 bits of complementary internal address signals X0 * to Xi-3 * are supplied to the X address decoder XD.

X address decoder XD is provided with complementary internal address signal X0 * supplied from X address buffer XB.
To Xi-3 * to selectively set a corresponding pair of main word lines of the memory array MARY to a predetermined selection level. The mat selection circuit MS decodes the upper 3 bits of the complementary internal address signals Xi-2 * to Xi * supplied from the X address buffer XB, and corresponding mat selection signals RXP0 to RXP7, RXN0 to RXN.
N7 and PA0 to PA7 are alternatively set to a predetermined selection level. These main word lines and mat select signals are combined by a sub-word line drive circuit of each memory mat, whereby the designated sub-word line of the designated memory mat is alternatively set to the selected level.

In this embodiment, a dynamic RA
M employs a negative word line system, and a sub-word line constituting a memory mat has a high voltage VHH such as +3.8 V as its selection level and a negative potential internal voltage VLL such as -1.0 V for example. The non-selection level is set. Therefore, the main word line and the mat selection signal are also set to a predetermined selection level or a non-selection level corresponding to the main word line and the mat selection signal. This will be described later in detail.

Next, the complementary bit lines constituting the memory array MARY are coupled to the sense amplifier SA below the memory array MARY, and are alternatively connected to the complementary common data line CD * via the sense amplifier. The sense amplifier SA has Y
A bit line selection signal of a predetermined bit is supplied from the address decoder YD, and mat selection signals PA0 to PA7 are supplied from the mat selection circuit MS. Also, Y
Address decoder YD receives complementary internal address signals Y0 * to Yi * of i + 1 bits from Y address buffer YB.
Is supplied. Further, in the Y address buffer YB,
Y address signal A via address input terminals A0-Ai
Y0 to AYi are supplied in a time-division manner, and an internal control signal YL is supplied from a timing generation circuit TG.

The Y address buffer YB is provided with a Y address signal AY supplied via address input terminals A0 to Ai.
0 to AYi are captured and held in accordance with the internal control signal YL, and complementary internal address signals Y0 * to Yi * are formed based on these Y address signals and supplied to a Y address decoder YD. The Y address decoder YD decodes the complementary internal address signals Y0 * to Yi *, and selectively sets the corresponding bit of the bit line selection signal to a high level selection state.

The sense amplifier SA is connected to the memory array MAR
Y includes a predetermined number of unit circuits provided corresponding to respective complementary bit lines of Y. Each of these unit circuits includes a bit line precharge circuit in which three precharge MOSFETs are connected in series and parallel, and a pair of unit circuits. A unit amplifier circuit formed by cross-coupled CMOS inverters and a pair of switches MO
And an SFET. Among them, a precharge MOS constituting a bit line precharge circuit of each unit circuit
The internal control signal PC is supplied to the FET from the timing generation circuit TG. The source of the P-channel and N-channel MOSFETs constituting the unit amplifier circuit of each unit circuit is connected to a high potential side operation such as the internal voltage VDL via an unillustrated common source line from an internal voltage generating circuit VG described later. A power supply and a low-potential-side operation power supply such as the ground potential VSS are selectively supplied, and a corresponding bit line selection signal is commonly supplied from the Y address decoder YD to the switch MOSFET pair of each unit circuit.

The precharge MOSFET of each unit circuit of the sense amplifier SA is selectively and simultaneously turned on in response to the high level of the internal control signal PC, and the non-inversion and inversion of the corresponding complementary bit line of the memory array MARY. The signal line is precharged to an intermediate potential between the internal voltage VDL and the ground potential VSS, that is, the internal voltage VDH. Also, the unit amplifier circuits of each unit circuit are selectively and simultaneously activated by the supply of the internal voltage VDL and the ground potential VSS via the corresponding common source line, and the memory array M
The small read signals output from a predetermined number of memory cells coupled to the selected word line of ARY via the corresponding complementary bit lines are respectively amplified to set the internal voltage VDL to high level and the ground potential VSS to low level. To be a binary read signal. Furthermore, the switch M of each unit circuit
The OSFETs are alternatively turned on when a corresponding bit line selection signal is set to a high level, and a corresponding set of complementary bit lines and a complementary common data line CD * of the memory array MARY, that is, data input / output. The connection with the circuit IO is alternatively set.

Complementary data line CD * is coupled to data input / output circuit IO. The data input / output circuit IO includes one write amplifier and one main amplifier, and a data input buffer and a data output buffer. Among these, the output terminal of the write amplifier and the input terminal of the main amplifier are commonly connected to a complementary common data line CD *. The input terminal of the write amplifier is coupled to the output terminal of the data input buffer, and the input terminal of the data input buffer is coupled to the data input terminal Din. Further, the output terminal of the main amplifier is coupled to the input terminal of the data output buffer, and the output terminal of the data output buffer is connected to the data output terminal D.
out.

When the dynamic RAM is selected in the write mode, the data input buffer of the data input / output circuit IO takes in the write data input through the data input terminal Din and transmits it to the write amplifier. At this time, the write amplifier operates the timing generation circuit T
Upon receiving the high level of the internal control signal WP supplied from the G, the operation mode is selectively activated, and the write data transmitted from the data input buffer is converted into a predetermined complementary write signal, and then, via the complementary common data line CD *. Memory array M
Write to the selected one memory cell of ARY.

On the other hand, when the dynamic RAM is selected in the read mode, the main amplifier of the data input / output circuit IO selects the selected one of the memory arrays MARY.
The binary read signal output from the memory cells via the complementary common data line CD * is further amplified and transmitted to the data output buffer. At this time, the data input / output circuit I
The O data output buffer is selectively activated in response to a high level of an internal control signal OC (not shown), and outputs read data transmitted from the main amplifier to an external access device via a data output terminal Dout.

The timing generation circuit TG selectively selects the various internal control signals based on a row address strobe signal RASB, a column address strobe signal CASB, and a write enable signal WEB supplied as an activation control signal from an external access device. And supply it to each part of the dynamic RAM.

In this embodiment, a dynamic RA
M is supplied with a power supply voltage VCC of, for example, +2.5 V via an external terminal VCC, and 0 V via an external terminal VSS.
Is supplied with the ground potential VSS. As described above, the dynamic RAM adopts the hierarchical word line system, and the memory array MARY and its immediate peripheral part are divided into eight memory mats, and the memory array MARY is divided into eight memory mats.
Are hierarchized into a main word line and a sub word line. Further, the dynamic RAM adopts a negative word line system, and the sub-word line uses the high voltage VHH as its selection level and the negative internal voltage VLL.
Is the non-selection level.

On the other hand, the dynamic RAM of this embodiment
In this case, the amplified high level of the read signal in each complementary bit line of the memory array MARY is set to the internal voltage VDL such as +2.0 V, and the low level is set to 0 V, that is, the ground potential VSS. The non-inverted and inverted signal lines of these complementary bit lines are connected to an internal voltage VDH such as an intermediate potential between the internal voltage VDL and the ground potential VSS, that is, +1.0 V when the dynamic RAM is set to the non-selected state. Precharged. Therefore, the dynamic RAM includes an internal voltage generation circuit VG that generates the above various internal voltages based on the power supply voltage VCC and the ground potential VSS.

The internal voltage generating circuit VG has an external terminal VCC.
Alternatively, based on the power supply voltage VCC and the ground potential VSS supplied via VSS, the high voltage VHH, the internal voltage VDL,
VDH, VLL and a substrate voltage VBB are generated and supplied to each part of the dynamic RAM. not to mention,
The power supply voltage VCC and the ground potential VSS have a relatively large wiring width, and are supplied to the dynamic RAM via a power supply voltage supply line or a ground potential supply line extending around the semiconductor substrate surface on which the dynamic RAM is formed. It is supplied to each part. In this embodiment, the power supply voltage VCC is +2.5 V, although not particularly limited, and the ground potential VSS is obviously 0 V (third potential). The high voltage VHH is set to +3.8 V (second potential), and the internal voltage VDL is set to +2.0 V (fourth potential). Internal voltage VDH is set to an intermediate potential between internal voltage VDL and ground potential VSS, that is, +1.0 V. Further, internal voltage VLL is set to a negative potential such as -1.0 V (first potential), and substrate voltage VBB is also set to -1.0 V. The substrate voltage VBB is supplied as a substrate potential to a P-type semiconductor substrate or a well region where a dynamic RAM is formed.

FIG. 2 is a block diagram showing one embodiment of the memory array MARY included in the dynamic RAM of FIG. 1 and its immediate peripheral part. Also, in FIG.
A circuit diagram of one embodiment of the sub-word line drive circuit SWD0, the sub-memory array SML0, the sense amplifier SAL0, and the sense amplifier drive circuit SAD0 included in the memory mat MAT0 of FIG. 2 is shown, and FIG. 4 shows the sub-word line of FIG. A circuit diagram of one embodiment of the unit sub-word line drive circuit UWD0 included in the drive circuit SWD0 is shown. FIG. 5 shows a signal waveform diagram of an embodiment of the memory array MARY of FIG. 2 and its immediate peripheral portion. With reference to these drawings, the specific configuration and operation of the memory array MARY of the dynamic RAM of this embodiment and its immediate peripheral portion, and the features thereof will be described.

In the following circuit diagrams, MOSFETs having an arrow at the channel (back gate) portion are of the P-channel type, and are distinguished from N-channel MOSFETs without the arrow. Further, in the following description, the sub-word line driving circuits SWD0, SWD7 and the sub-memory arrays SML0 are provided by using the sub-word line driving circuit SWD0, the sub-memory array SML0, the sense amplifier SAL0 and the sense amplifier driving circuit SAD0 of FIG.
SML7 and SMR0 to SMR7, sense amplifier S
AL0 to SAL7, SAR0 to SAR7, and the sense amplifier drive circuits SAD0 to SAD7 will be described, and the unit subword line drive circuits UWD0 to UWDk will be described using the unit subword line drive circuit UWD0 in FIG.

First, referring to FIG.
The M memory array MARY is divided into eight memory mats MAT0 to MAT7 including its direct peripheral portion, and each of these memory mats is arranged in a pair with the corresponding sub-word line drive circuits SWD0 to SWD7 interposed therebetween. Sub memory arrays SML0 and SMR0 to SML
7 and SMR7, and a pair of sense amplifiers SAL0 and SAR0 provided corresponding to these sub-memory arrays.
Or SAL7 and SAR7. Sense amplifier S
Sense amplifier drive circuits SAD0 to SAD7 are provided between AL0 and SAR0 to SAL7 and SAR7. The sub word line drive circuits SWD0 to SWD7 are
Main word lines MWA0 to MWAk and MWB0
In addition to being coupled to X address decoder XD via MWBk, corresponding mat select signals RXP0 to RXP7 and RXN0 to RXN7 are supplied from mat select circuit MS, respectively. In addition, the sense amplifiers SAL0 to SAL
AL7 and SAR0 to SAR7 are coupled to data input / output circuit IO via complementary common data line CD *, and internal control signal PC from timing generation circuit TG.
Is supplied. Further, the sense amplifier driving circuit SAD0
To SAD7 are supplied with corresponding mat selection signals PA0 to PA7 from the mat selection circuit MS.

Here, the memory mats MAT0-MAT7
The sub memory arrays SML0 to SML7 and SMR0 to SMR7 forming the sub memory array SM shown in FIG.
As represented by L0, k + 1 sub-word lines SWL0 to SWL arranged in parallel in the horizontal direction in the drawing
and m + 1 pairs of complementary bit lines B0 * to Bm * arranged in parallel in the vertical direction. At the intersection of these sub-word lines and complementary bit lines, an information storage capacitor Cs
And (k + 1) .times. (M + 1) dynamic memory cells comprising N-channel type address selection MOSFETs Qa are arranged in a lattice. Sub memory array SML
0 of one of the information storage capacitors Cs of the (k + 1) memory cells arranged in the same column of the corresponding complementary bit line B0 via the corresponding address selection MOSFET Qa.
* To Bm * are alternately arranged on the non-inverted or inverted signal lines with a predetermined regularity. The gates of the address selection MOSFETs Qa of the (m + 1) memory cells arranged on the same row of the memory array MARY are commonly coupled to the corresponding sub-word lines SWL0 to SWLk. The internal voltage VDH of +1.0 V is commonly supplied to the other electrodes of the information storage capacitors Cs of all the memory cells constituting the memory array MARY.

Complementary bit lines B0 * to Bm * forming sub memory array SML0 are respectively connected to corresponding unit circuits of sense amplifier SAL0 below. The sense amplifier SAL0 is connected to the sub memory array SML
It has m + 1 unit circuits provided corresponding to the 0 complementary bit lines B0 * to Bm *, and each of these unit circuits has three N-channel precharge MOSFETs N7 as illustrated in the figure. -N9 is connected in series and parallel, and a P-channel MO
SFET P2 and N-channel MOSFET N2 and P-channel MOSFET P3 and N-channel MO
It includes a unit amplifier circuit in which a pair of CMOS inverters composed of SFET N3 are cross-coupled, and a pair of N-channel type switch MOSFETs NA and NB.

Of these, the precharge MOSFET N7
To N9 are commonly supplied with an internal control signal PC from a timing generation circuit TG.
An internal voltage VDH of +1.0 V is commonly supplied from an internal voltage generation circuit VG to the commonly coupled sources of ETN8 and N9. With this, the precharge MOSFET
N7 to N9 are selectively and simultaneously turned on by the internal control signal PC being set to the high level, and the corresponding complementary bit lines B0 * to Bm * of the sub memory array SML0.
Non-inverting and inverting signal lines are connected to an internal voltage VDH of +1.0 V.
That is, it is precharged to an intermediate potential between the internal voltage VDL and the ground potential VSS.

On the other hand, MOSF constituting each unit amplifier circuit
The sources of ETP2 and P3 are commonly coupled to a common source line CSP, and the sources of MOSFETs N2 and N3 are commonly coupled to a common source line CSN. Common source line C
SP is coupled to internal voltage supply point VDL via P-channel MOSFET P1 of sense amplifier drive circuit SAD0, and common source line CSN is connected to its N-channel MO.
It is coupled to ground potential VSS via SFET N1. M
The gate of the OSFET N1 is supplied with the mat selection signal PA0 from the mat selection circuit MS, and the gate of the MOSFET P1 is supplied with the inverted signal of the inverter V1. Thereby, each unit amplifier circuit of the sense amplifier SAL0 is selectively and simultaneously turned on by setting the mat select signal PA0 to the high level and supplying the internal voltage VDL or the ground potential VSS to the common source lines CSP and CSN. And amplifies the small read signals output from the (m + 1) memory cells coupled to the selected sub-word line of the sub-memory array SML0 to the complementary bit lines B0 * to Bm *, respectively, to a high level such as the internal voltage VDL or It is a low level binary read signal such as the ground potential VSS.

The gates of the switch MOSFETs NA and NB of each unit circuit of the sense amplifier SAL0 are commonly connected, and corresponding bit line selection signals YSL0 to YSLm are supplied from the Y address decoder YD. Thereby, the switch MOSFETNA and NB of each unit circuit
Are selectively turned on when the corresponding bit line selection signals YSL0 to YSLm are alternatively set to a high level, and a corresponding set of complementary bit lines and complementary common data lines CD * of the sub memory array SML0 are provided. That is, the connection with the data input / output circuit IO is selectively set.

The sense amplifier driving circuit SAD0 is
Further, three N-channel precharge MOs provided in a series-parallel manner between the common source lines CSP and CSN.
SFETs N4 to N5 are included. These precharge MOs
The internal control signal PC is supplied to the gate of the SFET, and the internal voltage VDH is supplied to the commonly coupled sources of the precharge MOSFETs N5 and N6. Thereby, the precharge MOSFETs N4 to N6 are selectively turned on in response to the high level of the internal control signal PC when the dynamic RAM is set to the non-selected state, and the common source lines CSP and CSN are set to the internal voltage VDH.
Precharge to.

Next, sub-word lines SWL0-SWLk forming sub-memory array SML0 are coupled to the corresponding unit sub-word line drive circuits UWD0-UWDk of sub-word line drive circuit SWD0 on the right side. These unit sub word line drive circuits UWD0 to UW
The corresponding sub-word lines SWR0 to SWRk of the paired sub-memory arrays SMR0 are commonly coupled to Dk, respectively.
The description will proceed with a focus on only.

The sub-word line drive circuit SWD0 is connected to the sub-word lines SWL0 to SWLk of the sub-memory array SML0.
, And (k + 1) unit sub-word line drive circuits UWD0 to UWDk. These unit sub-word line driving circuits correspond to the corresponding main word lines MWA0 to MWA0.
It is bound to MWAk and MWB0 to MWBk, respectively. Also, the unit sub-word line drive circuits UWD0 to UWD
Dk is supplied with the corresponding mat selection signals RXP0 and RXN0 from the mat selection circuit MS and the internal voltage VLL from the internal voltage generation circuit VG.

The unit sub-word line driving circuits UWD0 to UWDk constituting the sub-word line driving circuit SWD0 are shown in FIG.
, A P-channel drive MOSFET P4 provided between the mat select signal RXP0 and an internal signal line, that is, a sub-word line SWL0, a sub-word line SWL0 and an external voltage supply point. That is, an N-channel type drive MOSFET NC (first switch means) provided between the ground potential VSS and an N-channel type drive MOSFET NC provided between the sub-word line SWL0 and the internal voltage supply point, that is, the negative internal voltage VLL. And another driving MOSFET ND (second switch means). Of these, the drive MO
The gates of SFETs P4 and NC are coupled to the corresponding main word line MWA0 or MWB0, respectively, and drive M
The corresponding mat select signal PXN0 is supplied to the gate of the OSFET ND. Note that the drive MOSFETs P4 and NC have relatively large drive capabilities, and
The TND is designed to have a small driving capability compared to these driving MOSFETs.

The mat selection signals RXP0 to RXP7 are not particularly limited, but as shown in FIG. 5, when the dynamic RAM is set to the non-selection state, it is set to 0V, that is, a non-selection level such as the ground potential VSS. When the dynamic RAM is set to the selected state, it is alternatively set to a selection level such as the high voltage VHH at a predetermined timing. The mat selection signals RXN0 to RXN7 are set to a non-selection level such as the high voltage VCC when the dynamic RAM is in the non-selection state, and the mat selection signal RXP0 is set when the dynamic RAM is in the selection state. Alternatively, at approximately the same timing as above, a selection level such as the internal voltage VLL is alternatively set.

On the other hand, main word lines MWA0 to MWAk
Is when the dynamic RAM is deselected.
The non-selection level of the high voltage VHH is set, and the dynamic type R
When the AM is selected, the mat selection signal RXP
The selection level of the ground potential VSS is alternatively set at substantially the same timing as 0 and RXN0, but is returned to the non-selection level at a timing earlier than these mat selection signals by a predetermined time. Also, main word lines MWB0 to MWBk
Is when the dynamic RAM is deselected.
When the internal voltage VLL is set to a non-selection level and the dynamic RAM is selected, the main word line MW
When A0 is returned to the non-selection level, the high voltage V
After being set to the selection level of CC, the mat selection signal RX
It is returned to the non-selection level at substantially the same timing as P0 and RXN0. The internal control signal PC for controlling the precharge operation of the sense amplifier SAL0 is set to an effective level such as the internal voltage VDL, that is, a high level when the dynamic RAM is in the non-selected state, and the dynamic RAM is set to the selected state. Then, it is set to an invalid level such as the ground potential VSS, that is, a low level. Then, when the dynamic RAM is set to the non-selected state again, the power supply voltage VCC is returned to the high level almost in the middle of the period in which the main word line MWB0 is at the selected level.

From these, the dynamic RAM
Is in a non-selected state, the sub-word line drive circuit SW
In the unit sub-word line drive circuit UWD0 of D0, the drive M
OSFET P4 is turned off in response to the non-selection level of main word line MWA0, that is, high voltage VHH. The drive MOSFET NC is connected to the main word line MWB0.
Is turned off in response to the non-selection level, ie, the internal voltage VLL, and the drive MOSFET ND outputs the mat selection signal RX.
It is turned on in response to the non-selection level of N0, that is, the high voltage VCC. As a result, all the sub-word lines including sub-word line SWL0 of sub-memory array SML0 are set to internal voltage VLL, that is, a negative potential non-selection level (one logic level) of -1.0 V. All memory cells constituting array SML0 are set to a non-selected state.

Note that the dynamic RAM adopts the negative word line system, and the non-selection level of the sub-word lines SWL0 to SWLk constituting the sub-memory array SML0 is set to a negative potential such as -1.0 V, so that The address selection MOSFET Qa of the memory cell is in a so-called reverse bias state. As a result, the address selection MOSF
It is possible to suppress the leak current through the ETQa, improve the information holding characteristics of the memory cells constituting the sub memory array SML0, extend the refresh cycle of the dynamic RAM, and reduce its power consumption. .

Next, when the dynamic RAM is set to the selected state and the mat select signals RXP0 and RXN0 and the main word line MWA0 are set to the selected level, the unit sub word line drive circuit U of the sub word line drive circuit SWD0
In WD0, the drive MOSFET P4 is turned on upon receiving the selection level of the main word line MWA0, that is, the ground potential VSS. The drive MOSFET NC is connected to the main word line MWB0 at the non-selection level, that is, the internal voltage VLL.
In this state, the off state is continued, and the driving MOSF
ETND is turned off in response to the selection level of mat selection signal RXN0, that is, internal voltage VLL. As a result, sub word line SWL0 of sub memory array SML0
, The selected level (the other logical level), that is, the high voltage VHH is transmitted through the drive MOSFET P4.
In response, m + 1 memory cells coupled to sub word line SWL0 of sub memory array SML0 are set to the selected state. As a result, the non-inverted and inverted signal lines of the complementary bit lines B0 * to Bm * of the sub memory array SML0 output a minute read signal corresponding to the data held in the (m + 1) memory cells coupled to the selected sub word line SWL0. Is done.

When the access to the selected address of the dynamic RAM is completed, first, the main word line MWA
0 is returned to the non-selection level, ie, the high voltage VHH, and the main word line MWB0 is alternatively selected, ie, the high voltage VHH.
CC. When a predetermined time has elapsed, the internal control signal PC is returned to the high level. When the predetermined time has further elapsed, the main word line MWB0 is returned to the non-selection level, that is, the internal voltage VLL. The signal RXP0 is at the non-selection level, that is, the ground potential VSS
And the mat select signal RXN0 is returned to a non-selection level such as the high voltage VCC. Sub word line drive circuit S
In the unit sub-word line drive circuit UWD0 of WD0, the drive MOSFET P4, which has been on, is turned off by receiving the high voltage VHH of the main word line MWA0, and the drive MOSFET NC is instead connected to the main word line MWD0.
It is turned on in response to the high voltage VCC of WB0. The drive MOSFET NC is turned off when the main word line MWB0 is returned to a non-selection level such as the internal voltage VLL, and then the drive MOSFET ND is turned on in response to the high voltage VCC of the mat select signal RXN0.

As described above, the selection level of sub memory array SML0, that is, sub word line S at the high voltage VHH
The WL0 potential is first set to the unit sub-word line drive circuit UWD0.
When the drive MOSFET NC is turned on, the ground potential VSS is lowered as the target potential, and then, when the drive MOSFET ND is turned on, the internal voltage VLL, which is the final non-selection level, is set as the target potential. Will be reduced.

As is well known, sub memory array SML0
Are coupled to the gates of the address selection MOSFETs Qa of the (m + 1) memory cells, and a relatively large parasitic capacitance is coupled. The sub-word line SWL0 transitions from a selection level such as the high voltage VHH to a non-selection level such as the internal voltage VLL, so that the sub-word line SWL0 has a relatively large discharge current starting from its parasitic capacitance. Is shed. Further, the internal voltage VLL is a dynamic RAM
Is shared as the non-selection level of all the sub-word lines, and the potential fluctuation degrades the disturb characteristics of the dynamic RAM.

However, in this embodiment, the dynamic R
In the AM, as described above, the sub-word line in the selected state is first reduced in potential with the ground potential VSS as the target potential, and then, after a predetermined time has elapsed, the internal voltage VLL of the negative potential is set as the target potential. Will be reduced. In the unit sub-word line drive circuit UWD0, the drive MOSFET NC provided between the sub-word line SWL0 and the like and the ground potential VSS is designed to have a relatively large driving capability.
The drive MOSFET ND provided between L and L is designed to have a small drive capability in comparison with this. further,
As is well known, the ground potential VSS, which is the initial target potential of the sub-word line SWL0 or the like, is supplied from an external power supply device having a relatively large supply capability via a predetermined external terminal, and is spread around the semiconductor substrate. Further, the supply wiring is formed with a relatively large wiring width.

From the above, the potential of the selected sub-word line SWL0 or the like such as the high voltage VHH is first rapidly reduced to the ground potential VSS by the sufficient supply capability of the ground potential supply line, and is lowered to the ground potential VSS. No problematic potential fluctuations occur. In addition, the potential of the sub-word line SWL0 or the like that has become the ground potential VSS is slowly lowered to the internal voltage VLL via the drive MOSFET ND having a relatively small driving ability, and a potential fluctuation that causes a problem also occurs in the internal voltage VLL. Absent. Furthermore, as is clear from the above description, the internal voltage generation circuit VG that generates the internal voltage VLL does not require a very large supply capability, and the circuit elements added to the dynamic RAM to take the above measures are small. A supply line for supplying the ground potential VSS may be used as it is. As a result, it is possible to stabilize the operation of the dynamic RAM employing the hierarchical word line system and the negative word line system without impairing its high speed and low cost.

The sense amplifier SAL0 receives the high level of the internal control signal PC and receives a precharge MOSF
The precharge operation of the complementary bit lines B0 * to Bm * by the ETNs 7 to N9 is started. At this time, since the potential of the sub word line SWL0 has changed to the ground potential VSS, the memory constituting the sub memory array SML0 The cell address selection MOSFET Qa is not weakly turned on. These address selection MOSFETs Qa
Is further reverse biased by setting the selected sub-word line SWL0 to the internal voltage VLL, that is, a negative potential of -1.0 V, whereby the leak current becomes substantially zero. In the unit sub-word line drive circuit UWD0, as described above, the drive MOSFET ND is turned on while the precharge operation of the complementary bit lines B0 * to Bm * is performed, and the selected sub-word line SWL0 lowered to the ground potential VSS. Of the internal voltage VL more slowly
Since the voltage is reduced to L, the fluctuation of the potential of the internal voltage VLL is also suppressed.

The operation and effect obtained from the above embodiment are as follows. (1) In a dynamic RAM or the like employing a hierarchical word line system and a negative word line system, when a sub-word line having a predetermined high voltage as its selection level is shifted to a predetermined non-selection level of a negative potential, The potential is first changed from a ground potential which is externally supplied and a sufficient supply wiring is prepared as a target potential, and then a negative potential having a small supply capability is used by utilizing a period in which the precharge operation of the complementary bit line is performed. By changing the non-selection level as the target potential,
First, the selection level of the sub-word line is changed relatively quickly to the ground potential through a ground potential supply path having a large supply capacity, and then slowly changed to a non-potential supply path through a relatively small supply potential. The effect of being able to change to the selection level is obtained.

(2) According to the above item (1), without increasing the supply capability of the internal voltage generating circuit for generating the internal voltage of the negative potential, the sub-word line having the internal voltage of the negative potential as its non-selection level can be used. The effect of increasing the speed of the level change and suppressing the potential fluctuation of the internal voltage of the negative potential accompanying this can be obtained. (3) According to the above items (1) and (2), it is possible to stabilize the operation of a dynamic RAM or the like employing a hierarchical word line system and a negative word line system without impairing its high speed and low cost. The effect that it can be obtained is obtained.

Although the invention made by the inventor has been specifically described based on the embodiments, the invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist of the invention. Needless to say, there is. For example, in FIG.
Any bit configuration such as 8 or × 16 bits can be adopted. In addition, the dynamic RAM does not require that the address multiplex method be adopted,
Various embodiments can be adopted for the block configuration, the combination of the start control signal and the address signal, the polarity of the power supply voltage, and the like. The specific potentials of the power supply voltage VCC, the high voltage VHH, the internal voltages VDL, VDH, VLL and the substrate voltage VBB do not restrict the gist of the present invention.

In FIG. 2, the memory array MARY and the direct peripheral portion can be divided into an arbitrary number of memory mats.
A shared sense method can also be adopted. In FIG. 3, memory array MARY can include an arbitrary number of redundant elements, and unit sub-word line driving circuits UWD0 to UWD0.
Sub word line drive circuits SWD0-SWD including UWDk
k, sub memory arrays SML0 to SML7 and SM
R0 to SMR7, sense amplifiers SAL0 to SAL7 and SAR0 to SAR7, sense amplifier drive circuit SAD
The specific configuration of 0 to SAD7 can take various embodiments. The unit sub-word line driving circuit represented by UWD0 in FIG.
An NMOS type including only an FET may be used.

In FIG. 5, the specific level and time relationship of each signal do not limit the present invention. Also, the sub-word lines SWL0-SWL0 once lowered to the ground potential VSS
The operation for lowering the potential of SWLk and SWR0 to SWRk to the internal voltage VLL is performed by the sense amplifier SAL
0 complementary bit line B0 by the bit line precharge circuit
It may be started at the same time as the precharge operation of * to Bm *.

In the above description, mainly the case where the invention made by the present inventor is applied to the dynamic RAM and the change of the sub-word line to the non-selection level, which is the field of application, has been described. The present invention is not limited to this. For example, the level of another signal that uses the internal voltage generated by the internal voltage generating circuit VG as the level after the operation of raising the main word line and the sub-word line to the high voltage VHH, or the level of another signal It can be applied to change. Further, the present invention can be applied to various memory integrated circuits having a dynamic RAM as a basic configuration, and also to a logic integrated circuit device such as a microcomputer including the same. The present invention is widely applied to a semiconductor integrated circuit device including a signal line having at least one of its logic levels as an internal voltage and receiving an external voltage as another potential, and a device or system including such a semiconductor integrated circuit device. Applicable.

[0062]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a dynamic RAM or the like employing a hierarchical word line system and a negative word line system, when a sub-word line having a predetermined high voltage as its selection level is transited to a non-selection level of a predetermined negative potential, its potential is changed to: First, external supply and sufficient supply wiring are prepared. For example, after changing the ground potential as the target potential,
By using the period during which the precharge operation of the complementary bit line is performed and changing the non-selection level of the negative potential having a small supply capability as the target potential, the selection level of the sub-word line can be changed to the external supply first to increase the large supply capability. After the potential is relatively quickly changed to the ground potential through the ground potential supply path, the potential can be slowly changed to the non-selection level through the negative potential supply path having a relatively small supply capacity.
As a result, without increasing the supply capability of the internal voltage generating circuit for generating the internal voltage of the negative potential, the level change of the sub-word line that makes the internal voltage of the negative potential the non-selection level is speeded up, and the level of the sub-word line is increased. Potential fluctuation of the negative internal voltage due to the change can be suppressed. This makes it possible to stabilize the operation of a dynamic RAM or the like employing the hierarchical word line system and the negative word line system without impairing its high speed and low cost.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a dynamic RAM to which the present invention is applied.

FIG. 2 is a block diagram showing one embodiment of a memory array and a direct peripheral part included in the dynamic RAM of FIG. 1;

FIG. 3 is a partial circuit diagram showing one embodiment of a memory array and a direct peripheral portion included in the dynamic RAM of FIG. 1;

FIG. 4 is a circuit diagram showing one embodiment of a unit sub-word line driving circuit of the sub-word line driving circuit included in the memory mat of FIG. 2;

FIG. 5 is a signal waveform diagram showing one embodiment of a memory array and a direct peripheral portion included in the dynamic RAM of FIG. 1;

FIG. 6 is a circuit diagram showing an example of a unit sub-word line drive circuit of a sub-word line drive circuit of a dynamic RAM developed by the present inventors prior to the present invention.

[Explanation of symbols]

MARY ... memory array, XD ... X address decoder, MS ... mat selection circuit, XB ... X address buffer, SA ... sense amplifier, YD ... Y address decoder, YB ... Y address buffer, IO ... Data input / output circuit, VG: internal voltage generation circuit, TG: timing generation circuit. RASB ... row address strobe signal or its input terminal, CASB ... column address strobe signal or its input terminal, WEB ... write enable signal or its input terminal, A0-Ai ... address signal or its input terminal, Din ... Input data or its input terminal, Dout... Output data or its output terminal, V
CC: power supply voltage or its input terminal, VSS: ground potential or its input terminal. MAT0 to MAT7: memory mats, SML0 to SML7, SMR0 to SMR7 ... sub memory arrays, SWD0 to SWD7 ... sub word line drive circuits, SAL0 to SAL7, SAR0 to SAR7 ...
... Sense amplifiers, SAD0 to SAD7 ... Sense amplifier drive circuits, X0 to Xi ... Internal X address signals, MWA
0 to MWAk, MWB0 to MWBk... Main word line, RXP0 to RXP7, RXN0 to RXN7, PA0
To PA7: mat selection signal, PC: precharge control signal, CD *: complementary common data line. SWL0-SW
Lk, SWR0 to SWRk... Sub word line, B0 * to
Bm *: complementary bit line, Qa: address selection MOS
FET, Cs: information storage capacitor, UWD0 to UW
Dk... Unit sub-word line drive circuit, YSL0 to YSL
m: Bit line selection signal, CSP, CSN: Common source line. P1 to P5 P-channel MOSFET, N
1 to NE: N-channel MOSFET, V1: inverter, Cw: sub-word line parasitic capacitance.

 ──────────────────────────────────────────────────の Continued on the front page (72) Inventor Masatoshi Hasegawa 2326 Imai, Ome-shi, Tokyo Inside the Hitachi, Ltd.Device Development Center (72) Inventor Seiji Narii 2326, Imai, Ome-shi, Tokyo Hitachi, Ltd.Device Development Center, Ltd. (72) Inventor Shinichi Miyatake 5-20-1, Josuihonmachi, Kodaira-shi, Tokyo Nippon-Cha SLS Engineering Co., Ltd. (72) Inventor Yosuke Tanaka 2326 Imai, Ome-shi, Tokyo Inside Hitachi Device Development Center (72) Inventor Kazuhiko Kazuya 2326 Imai, Ome-shi, Tokyo Inside Hitachi Device Development Center (72) Inventor Hiroki Fujisawa 2326 Imai, Ome-shi, Tokyo Inside Hitachi Device Development Center (72) Inventor Shuichi Kubouchi Tokyo Kodaira Josuihon-cho 5-chome No. 20 No. 1 Date standing ultra-El es Eye Engineering Co., Ltd. in

Claims (5)

[Claims] 1. An internal voltage generating circuit for generating an internal voltage whose potential is a first potential, one of the logic levels being the first potential and the other being a second potential being a second potential And an external terminal to which an external voltage whose potential is a third potential between the first and second potentials is input, wherein the internal signal line is connected to the second potential. Wherein the potential changes from the first potential to the first potential, the potential is first changed using the third potential as a target potential, and then the first potential is changed using the first potential as a target potential. apparatus. 2. The first switch according to claim 1, wherein the semiconductor integrated circuit device is provided between the internal signal line and the supply point of the external voltage and is selectively turned on at a predetermined timing. And a drive circuit including a second switch provided between the internal signal line and the supply point of the internal voltage, the second switch being turned on after the first switch is turned off. A semiconductor integrated circuit device. 3. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device includes a memory array in which dynamic memory cells are arranged in a lattice, and the internal signal line is selected by A word line of the memory array whose level is set to the second potential and whose non-selection level is set to the first potential; the drive circuit is a unit provided corresponding to each word line of the memory array A sub-word line driving circuit, wherein the third potential is a ground potential of the circuit, and the memory array has a fourth potential at a high level after amplification of a read signal on the non-inverted and inverted signal lines. , Including a complementary bit line whose low level is the third potential, and the first potential is a predetermined negative potential lower than the ground potential of the circuit. A semiconductor integrated circuit device characterized by the above-mentioned. 4. The non-inverted and inverted signal line of the complementary bit line according to claim 1, wherein the word line is changed from the second potential to a third potential.
The word line potential is precharged to an intermediate potential between the fourth and third potentials, while the non-inverted and inverted signal lines of the complementary bit line are precharged to the intermediate potential. To
A semiconductor integrated circuit device wherein the first potential is changed as a target potential. 5. The dynamic RAM according to claim 1, wherein the semiconductor integrated circuit device employs a hierarchical word line system and includes a plurality of memory mats.
The semiconductor integrated circuit device according to claim 1, wherein the drive circuit is dispersedly arranged on a semiconductor substrate surface on which the semiconductor integrated circuit device is formed.