JP3214584B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, for example, a low power consumption static RAM (random access memory) employing an auto power down system.
This is a technology that is particularly effective when used for

[0002]

2. Description of the Related Art There is a static RAM in which a memory array in which static memory cells are arranged in a lattice is a basic component. Further, in such a static RAM or the like, even when the chip selection state is continued for a relatively long time, power consumption is reduced by stopping the operation of selecting a word line and a bit line after a predetermined time. There is a so-called auto power down method.

A static RAM employing an auto power-down method is disclosed in, for example, "IEEE Journal" published in October, 1990.
Of Solid State Circuits (Journal
of Solid-State Circuits)
Vol. 25, no. 5 "in" 23-ns 4-Mb
CMOS SRAM With 0.2 μA Stan
dby Current ".

[0004]

SUMMARY OF THE INVENTION The present inventors faced the following problems in an attempt to further reduce the power consumption of the static RAM employing the auto power down method. That is, in recent years, so-called multi-bit static RAMs have been developed, and it is necessary to provide a plurality of sense amplifiers corresponding to each bit of read data output simultaneously. However, in a conventional static RAM employing an auto power-down method, the sense amplifier is constituted by a so-called current mirror sense amplifier. Although this current mirror sense amplifier can operate at high speed, the amplification factor is relatively small. It has the disadvantage that a direct current always flows while it is active. Therefore, in order to obtain a sufficient gain as a sense amplifier, a multi-stage structure must be adopted, and if the operation of the sense amplifier is stopped after the amplification operation to reduce the operating current of the sense amplifier,
An output latch for holding the amplified read data must be separately provided. As a result, the required number of elements of the read-related circuit increases, and the current consumption increases, so that the cost and power consumption of the static RAM are restricted.

SUMMARY OF THE INVENTION It is an object of the present invention to reduce the operating current of a readout circuit, simplify the circuit configuration, and promote cost reduction and power consumption reduction of a static RAM or the like employing an auto power down system. It is in.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0007]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, in a static RAM or the like that employs an auto power-down method, a sense amplifier includes a latch substantially formed by cross-coupled a pair of CMOS inverters, a drive MOSFET that selectively supplies an operating current to the latch, A pair of transfer MOSFs respectively provided between the non-inverted and inverted input / output nodes of the latch and the non-inverted and inverted signal lines of the complementary common data line
The transfer MOSFET is constituted by an inverter type CMOS latch including an ET and a drive MOSFET.
Immediately after the FET is turned on and the sense amplifier is turned on, it is turned off and the sense amplifier is disconnected from the common data line.

[0008]

According to the above means, a single inverter type CMO
The S-latch enables high-speed operation, and has a relatively large amplification factor due to the full swing of its output amplitude.
Moreover, it is possible to realize a sense amplifier that allows a DC current to flow only at the time of state transition. As a result, the circuit configuration of the sense amplifier itself can be simplified, and these sense amplifiers can be kept operating even after the end of the read signal amplification operation, and can be used as an output latch. As a result, it is possible to reduce the operating current of the readout circuit, simplify the circuit configuration, and promote cost reduction and power consumption reduction of a static RAM or the like employing an auto power down method.

[0009]

FIG. 1 is a block diagram showing one embodiment of a static RAM to which the present invention is applied. 2 and 3 are partial circuit diagrams of an embodiment of a memory array and a Y switch included in the static RAM of FIG. 1, respectively. FIG. 4 is a circuit diagram of a write amplifier and a sense amplifier. A partial block diagram of one embodiment is shown. Further, FIGS. 5 and 6 are circuit diagrams of an embodiment of the unit write amplifier and the unit sense amplifier constituting the write amplifier and the sense amplifier of FIG. 4, respectively. FIG. FIG. 5 shows a signal waveform diagram of one embodiment in a read mode of a RAM. Based on these figures, the static RAM of this embodiment
The configuration, operation, and characteristics thereof will be described. Each of the circuit elements shown in FIGS. 1 to 6 and the circuit elements constituting each block are well-known CMOS (complementary MOS).
Depending on integrated circuit manufacturing technology, one such as single crystal silicon
It is formed on individual semiconductor substrates. In the following circuit diagrams, MOSFETs (metal oxide semiconductor type field effect transistors, in each of which a channel (back gate) portion is marked with an arrow. In this specification, MOSFETs are generally referred to as insulated gate type field effect transistors. ) Is a P-channel type (second conductivity type), which is distinguished from an N-channel type (first conductivity type) without an arrow.

In FIG. 1, the static RAM of this embodiment is not particularly limited, but includes four memory arrays ARY0 to ARY divided in the direction in which complementary bit lines extend.
3 as its basic component. These memory arrays are supplied with corresponding selection drive signals WD0 to WD3 from a mat selection circuit MS described later.

The memory arrays ARY0 to ARY3 are shown in FIG.
As representative of the memory array ARY0, m + 1 sub word lines S arranged in parallel in the horizontal direction.
W0 to SWm and n + 1 arranged in parallel in the vertical direction
A set of complementary bit lines B0 * to Bn * (here, for example, the non-inverted bit line B0T and the inverted bit line B0B are indicated by asterisk (*) like a complementary bit line B0 *. A so-called non-inverted signal or the like which is selectively set to a high level when the signal is given is indicated by adding a T to the end of its name, and a so-called inverted signal or the like which is selectively set to a low level when the signal is valid. B at the end of the name
And is represented by The same applies to the following), and are arranged in a grid at the intersection of these sub-word lines and complementary bit lines (m + 1)
× (n + 1) static memory cells MC.

As shown in FIG. 2, each of the memory cells MC constituting the memory arrays ARY0 to ARY3 has a pair of N-channel drive MOSFETs N1 and N2, the drains of these drive MOSFETs and the power supply voltage of the circuit. And a pair of high resistance loads R1 and R2 provided between them. The gate of the drive MOSFET N1 is driven M
The driving MOSFET is connected to the drain of the OSFET N2.
The gate of TN2 is coupled to the drain of drive MOSFET N1. Thereby, the drive MOSFETs N1 and N2
Are cross-coupled to form a latch serving as a storage element of the memory cell MC. The drain of the driving MOSFET N1, that is, the gate of the driving MOSFET N2 is used as a non-inverting input / output node of the memory cell MC, and is an N-channel type selection MOS.
Complementary bit lines B0 * to Bn via FETN3
Each of them is commonly coupled to the non-inverted signal line of *. Also, the drain of the drive MOSFET N2, that is, the drive MOSFET
The gate of N1 is an inverted input / output node of the memory cell MC, and is commonly coupled to the corresponding inverted signal lines of the corresponding complementary bit lines B0 * to Bn * via an N-channel type selection MOSFET N4. Select MOSFET N3 and N4
Are commonly coupled to corresponding sub-word lines SW0 to SWm, respectively.

Sub-word lines SW0-SWm forming memory arrays ARY0-ARY3 are coupled to corresponding sub-word line drive circuits SWD0-SWDm. Each of these sub-word line driving circuits is, as represented by sub-word line driving circuit SWD0, an N-channel MOSFET N6 provided between corresponding sub-word lines SW0 to SWm and the ground potential of the circuit, and a common coupling thereof. Sub-word lines SW0-SWm corresponding to the drains
P channel M in the form of a CMOS inverter coupled to
OSFET P6 and N-channel MOSFET N5. Commonly coupled gates of MOSFETs P6 and N5 forming sub word line drive circuits SWD0 to SWDm are commonly coupled to corresponding main word lines MW0B to MWmB, respectively. Further, the corresponding selection drive signals WD0 to WD3 are commonly supplied to the source of the MOSFET P6, and the inverted signal of the inverter V1 is commonly supplied to the gate of the MOSFET N6.

As shown in FIG. 7, the selection drive signals WD0 to WD3 are normally set to a low level such as the ground potential of the circuit, the static RAM is selected, and the Z address signals AZ0 to AZ1 are used. When the corresponding memory arrays ARY0 to ARY3 are designated,
It is selectively set to a high level such as a power supply voltage of a circuit in synchronization with an internal control signal TCS described later. The main word lines MW0B to MWmB are normally set to the high level like the power supply voltage of the circuit, and when the static RAM is selected and the corresponding row address is designated by the X address signals AX0 to AXi, It is selectively set to a low level such as the ground potential of the circuit. The main word lines MW0B to MWmB are connected to the memory arrays ARY0 to ARY0 to A
Shared by RY3, the left end of which is coupled to X address decoder XD.

Thereby, the sub word lines SW0 to SWm
7, as shown in FIG. 7, is normally set to a low level such as the ground potential of the circuit, and the corresponding selection drive signal WD
When 0 to WD3 are set to the high level and the corresponding main word lines MW0B to MWmB are set to the low level, a high-level selection state such as the power supply voltage of the circuit is alternatively set. In response to the high level of the sub-word lines SW0 to SWm, the selection MOSFETs N3 and N4 of the (n + 1) memory cells MC arranged in the corresponding rows of the memory arrays ARY0 to ARY3 are selectively and simultaneously turned on. Then, a read signal according to the data held in each memory cell MC is output to the non-inverted and inverted signal lines of the corresponding complementary bit lines B0 * to Bn *, respectively.

On the other hand, complementary bit lines B0 * to Bn * forming memory arrays ARY0 to ARY3 are coupled to corresponding bit line precharge circuits BPC0 to BPCn at one side, that is, in the upper part of FIG. Below, they are coupled to the corresponding switch MOSFETs of the corresponding Y switches YS0-YS3.

Bit line precharge circuits BPC0-BP
As shown by bit line precharge circuit BPC0 in FIG. 2, Cn is provided between the power supply voltage of the circuit and the corresponding non-inverted and inverted signal lines of complementary bit lines B0 * to Bn *, respectively. P channel type load MO
Three P-channel precharges provided between the SFETs P1 and P2 and the non-inverted and inverted signal lines of the complementary bit lines B0 * to Bn * corresponding to the power supply voltage of the circuit and between the non-inverted and inverted signal lines MOSFET P3 to P5
And respectively. Of these, the load MOSFETs P1 and P2 are in a so-called latch form because their gates and drains are cross-coupled.
The corresponding precharge control signals PC0 to PC3 are commonly supplied to the gates of TP3 to P5. The load MOSFETs P1 and P2 are designed to have a relatively small conductance. The precharge control signals PC0 to PC3 are, for example, static type R
It is at a low level when AM is in a non-selected state and at a high level when it is in a selected state.

Thus, the precharge MOSFET P
For example, when the static RAM is set to the non-selection state, the corresponding precharge control signals PC0 to PC5
Upon receiving the low level of PC3, it is selectively turned on,
The non-inverted and inverted signal lines of the corresponding complementary bit lines B0 * to Bn * are precharged to a high level such as the power supply voltage of the circuit. Also, when the static type RAM is selected, the load MOSFETs P1 and P2 output from the (n + 1) memory cells MC coupled to the selected word lines W0 to Wm to the corresponding complementary bit lines B0 * to Bn *. The change of the read signal to be performed is promoted and the signal amount is increased.

Returning to the description of FIG. The X address decoder XD is supplied with i + 1-bit internal address signals X0 to Xi from the X address buffer XB, and an internal control signal TCS from the timing generation circuit TG. The X address buffer XB has address input terminals AX0 to AX
X address signals AX0 to AXi are supplied via Xi. As shown in FIG. 7, the internal control signal TCS is set to a low level such as the ground potential of the normal circuit, and selectively changes to a high level such as the power supply voltage of the circuit in response to the low level change of the chip selection signal CSB. However, after a predetermined time tcs has elapsed, the level is returned to the low level. This time tcs corresponds to the minimum time required for the write or read operation of the stored data, and is the timing for entering the auto power down state when the static RAM is kept in the selected state for a longer period than necessary. Served to set.

The X address buffer XB has an address input terminal A when the static RAM is selected.
X address signal AX0 supplied via X0 to AXi
AXi are taken in and held, and based on these X address signals, internal address signals X0 to Xi are formed and supplied to the X address decoder XD. The X address decoder XD is selectively activated in response to the high level of the internal control signal TCS, decodes the internal address signals X0 to Xi supplied from the X address buffer XB, and Main word lines MW0B to M
WmB is alternatively set to a low-level selection level such as the ground potential of the circuit. As described above, the internal control signal TCS
Is set to the high level for a predetermined time tcs, and the operation of selecting the main word line by the X address decoder XD and the operation of selecting the sub word lines in the memory arrays ARY0 to ARY3 are also performed for the time tcs. As a result, even when the static RAM is in the selected state for a relatively long period of time, it is in the auto power down state, and power consumption is reduced.

Next, the Y switches YS0 to YS3 are shown in FIG.
As representatively represented by Y switch YS0, complementary bit lines B0 * to Bn of memory arrays ARY0 to ARY3.
* Includes n-channel type n + 1 pairs of switch MOSFETs N7 and N8 and P-channel type n + 1 pairs of switch MOSFETs P7 and P8, respectively. Of these, switch MOSFETs N7 and N
8 are respectively coupled to the non-inverted or inverted signal lines of the corresponding complementary bit lines B0 * to Bn * of the memory arrays ARY0 to ARY3, and the other is connected to the complementary complementary data lines for writing CW0 * to CW7 * (the One non-inverted or inverted signal line of one complementary common data line) is commonly coupled every eight pairs. The gates of these switch MOSFETs are commonly connected in order of eight pairs, and Y address decoders YD0 to YD3
Supplies corresponding bit line selection signals YSW0 to YSWp. Similarly, switch MOSFETs P7 and P8
Are coupled to the non-inverted or inverted signal lines of the corresponding complementary bit lines B0 * to Bn * of the memory arrays ARY0 to ARY3, respectively, and the other is coupled to the read complementary common data lines CR0 * to CR7 * (second Complementary data line)
Are commonly coupled to every eight pairs of non-inverted or inverted signal lines.
These switch MOSFET gates are commonly coupled in order of eight pairs, and corresponding bit line selection signals YSR0 to YSRp are supplied from Y address decoders YD0 to YD3.

The bit line selection signals YSW0 to YSW
It goes without saying that p and the number of bits p + 1 of YSR0 to YSRp are in the relationship of p + 1 = (n + 1) / 8. Y switch YS
0 to YS3 complementary common data lines CW0 * to CW for writing
W7 * is coupled to corresponding write amplifiers WA0-WA3, respectively. Further, the read complementary common data line C
R0 * to CR7 * are the corresponding write amplifiers WA0 to WA
A3, and coupled to corresponding sense amplifiers SA0-SA3, respectively.

As a result, the switch MOSFETs N7 and N8 constituting the Y switches YS0 to YS3 are selectively turned on in pairs of 8 by setting the corresponding bit line selection signals YSW0 to YSWp to the high level, thereby setting the corresponding memory. Eight sets of complementary bit lines B0 * to Bn * specified in arrays ARY0 to ARY3 and complementary common data lines CW0 * to CW7 * for writing, that is, write amplifiers WA0 to WA0.
WA3 is selectively connected. Similarly, the switch MOSFET P7 constituting the Y switches YS0 to YS3
And P8 are corresponding bit line selection signals YSR0 to YS.
When Rp is set to the high level, eight pairs are selectively turned on, and the corresponding memory arrays ARY0 to ARY3 are turned on.
Of complementary bit lines B0 * to Bn * and complementary common data lines CR0 * to CR7 * for reading, that is, write amplifiers WA0 to WA3 and sense amplifier SA0.
To SA3 are selectively connected.

As described above, the complementary common data lines are provided corresponding to the memory arrays ARY0 to ARY3, and are dedicated as the complementary complementary data lines CW0 * to CW7 * for writing and the complementary common data lines CR0 * to CR * 7 for reading. In particular, the level change of the complementary common data line during the read operation can be speeded up, and the static RAM
Can be speeded up. Note that a complementary data line for writing and a complementary data line for reading are provided corresponding to the memory arrays ARY0 to ARY3, and the sense amplifiers SA0 to SA3 are connected to the memory array ARY.
The provision of the sense amplifiers corresponding to the sense amplifiers SA0 to ARY3 leads to an increase in the amount of hardware of the sense amplifier, that is, the readout circuit. However, in this embodiment, as described later, each unit sense amplifier of the sense amplifiers SA0 to SA3 has an inverter. This is not a problem because it is configured by a CMOS latch. In other words, in this embodiment, each unit sense amplifier of the sense amplifiers SA0 to SA3 is an inverter type C
With the configuration using the MOS latch, the complementary common data line can be divided without considering the hardware amount of the sense amplifier, and the speed of the read operation can be increased.

The Y address decoders YD0 to YD3 have:
The Y address buffer YB supplies the j + 1-bit internal address signals Y0 to Yj, the timing generation circuit TG supplies the internal control signal TCS, and the mat selection circuit MS supplies the corresponding mat selection signals M0 to M3. . The Y address buffer YB has Y address signals AY0 to AY0 via address input terminals AY0 to AYj.
AYj is supplied. In addition, the mat selection circuit MS includes:
Two-bit internal address signals Z0 to Z1 are supplied from a Z address buffer ZB, and internal control signals CS and TCS are supplied from a timing generation circuit TG. To the Z address buffer ZB, Z address signals AZ0 to AZ1 are supplied via address input terminals AZ0 to AZ1. As shown in FIG. 7, the internal control signal CS is normally set to a low level, and when the static RAM is set to the selected state in response to the low level change of the chip select signal CSB,
While the chip select signal CSB is at the low level, it is at the high level.

The Z address buffer ZB has an address input terminal A when the static RAM is selected.
Z address signal AZ0 supplied via Z0 to AZ1
AZ1 are taken in and held, and based on these Z address signals, internal address signals Z0-Z1 are formed and supplied to the mat selection circuit MS. The mat selection circuit MS is selectively activated by receiving the high level of the internal control signal CS, and decodes the internal address signals Z0 to Z1 supplied from the Z address buffer ZB. Then, the mat selection signals M0 to M3 corresponding to the internal control signal CS are alternately set to the high level, and the selection drive signal W corresponding to the internal control signal TCS is substantially synchronized.
D0 to WD3 are alternatively set to the high level.

Similarly, when the static RAM is set to the selected state, the Y address buffer YB takes in and holds the Y address signals AY0 to AYj supplied via the address input terminals AY0 to AYj. The internal address signals Y0 to Y based on the Y address signal
j is formed and supplied to the Y address decoders YD0 to YD3. The Y address decoders YD0 to YD3 are selectively activated when the internal control signal TCS is set to the high level and the corresponding mat selection signals M0 to M3 are set to the high level, and are supplied from the Y address buffer YB. The internal address signals Y0 to Yj are decoded, and the bit line select signals YSW0 to YSWp and YSR0 to YSR0 are decoded.
YSRp is selectively set to a high level under a predetermined condition. As described above, the internal control signal TCS is set to the high level for the predetermined time tcs, and the Y address decoders YD0 to YD
3 and bit line B by Y switches YS0 to YS3
The selection operation of 0 * to Bn * is also performed for the time tcs.
As a result, even when the static RAM is in the selected state for a relatively long period of time, the state becomes the auto power down state, and the power consumption can be reduced.

The write amplifiers WA0 to WA3 correspond to the write complementary common data lines CW0 * to CW7 * and the read complementary common data lines CR0 * to CR7 *, as shown by the write amplifier WA0 in FIG. And eight unit write amplifiers UWA0 to UWA7, respectively. These unit write amplifiers are respectively coupled to corresponding write complementary data lines CW0 * to CW7 * and read complementary common data lines CR0 * to CR7 * at one side, that is, at the top of the figure, and at the other side, that is, in the figure. Below, it is coupled to the corresponding data input / output buses DB0 * to DB7 *. The data input / output buses DB0 * to DB7 * are coupled to the output terminals of the corresponding unit circuits of the data input buffer DIB, coupled to the corresponding unit sense amplifiers of the sense amplifiers SA0 to SA3, and further connected to the data output buffer DOB. It is coupled to the input terminal of the corresponding unit circuit. An internal control signal WP is commonly supplied from a timing generation circuit TG to the unit write amplifiers UWA0 to UWA7, and the mat selection circuit MWA
The corresponding mat selection signals M0 to M3 are supplied in common from S. The internal control signal WP is normally set to a low level, and temporarily set to a high level at a predetermined timing when the static RAM is selected in the write mode. As described above, the mat selection signals M0 to M3 are normally at the low level, and the Z address signals AZ0 to AZ0 when the static RAM is in the selected state.
It is alternatively set to a high level in accordance with AZ1.

When the static RAM is selected in the write mode, the data input buffer DIB takes in the write data supplied via the data input / output terminals IO0 to IO7, and outputs the data input / output buses DB0 * to DB0.
The data is transmitted to the unit write amplifiers UWA0 to UWA7 of the write amplifiers WA0 to WA3 via B7 *.

The unit write amplifiers UWA0 to UWA7 constituting the write amplifiers WA0 to WA3 are composed of two write circuits WC1 (first write circuit) and WC2, as represented by the unit write amplifier UWA0 in FIG.
(A second writing circuit), and an AND gate AG3 and an inverter V5 provided in common to these writing circuits. The internal control signal WP is supplied to one input terminal of the AND gate AG3, and the corresponding mat selection signals M0 to M
3 are supplied. Thus, the output signal of AND gate AG3 is selectively set to the high level when internal control signal WP is set to the high level and corresponding mat selection signals M0 to M3 are set to the high level.

The write circuit WC1 includes a pair of P-channel type precharge MOSFETs PK and PL provided between the power supply voltage of the circuit and the non-inverted and inverted signal lines of the complementary complementary data lines CW0 * to CW7 *.
And data input / output buses DB corresponding to the non-inverted and inverted signal lines of write complementary common data lines CW0 * to CW7 *
A pair of N-channel type switch MOSFs respectively provided between non-inverted and inverted signal lines of 0 * to DB7 *
ETNI and NJ respectively. Precharge MO
SFET PK and PL and switch MOSFET N
The output signals of the AND gate AG3 are commonly supplied to the gates of I and NJ.

As a result, the precharge MOSFETs PK and PL constituting the write circuit WC1 are set when the output signal of the corresponding AND gate AG3 is set to a low level, in other words, when the internal control signal WP is set to a low level or when the corresponding mat selection signal is set. When the signal M0 is set to the low level, it is selectively turned on, and the non-inverted and inverted signal lines of the corresponding complementary complementary data lines for writing CW0 * to CW7 * are precharged to a high level such as the power supply voltage of the circuit. When the output signal of the corresponding AND gate AG3 is at a high level, in other words, the internal control signal WP and the corresponding mat selection signals M0 to M3 are both at a high level. Is turned on selectively, and the data input buffer DIB described later
The write signals supplied from the corresponding data input / output buses DB0 * to DB7 * are transmitted to corresponding write complementary common data lines CW0 * to CW7 *, respectively.

On the other hand, the write circuit WC2 is connected to the power supply voltage of the circuit and the complementary complementary data lines CR0 * to CR7 * for reading.
And three non-inverted and inverted signal lines, and three P-channel type precharge MOSFETs PM-PO provided between the non-inverted and inverted signal lines, and non-inverted complementary read common data lines CR0 * -CR7 *. And a pair of complementary gates G5 and G6 respectively provided between the inverted signal lines and the corresponding non-inverted and inverted signal lines of the data input / output buses DB0 * to DB7 *. The gates of the precharge MOSFETs PM to PO have corresponding precharge control signals PCD from the timing generation circuit TG.
0 to PCD3 are commonly supplied. Also, an N-channel MOSFE forming the complementary gates G5 and G6
The output signal of the AND gate AG3 is supplied to the gate of T, and the inverted signal from the inverter V5 is supplied to the gate of the P-channel MOSFET.

Thus, when the corresponding precharge control signals PCD0 to PCD3 are at a low level, in other words, for example, the static type R
When AM is in the non-selected state, it is selectively turned on, and the corresponding read complementary common data lines CR0 * to CR0 * C
The non-inverted and inverted signal lines of R7 * are precharged to a high level such as the power supply voltage of the circuit. Further, the complementary gate G
5 and G6 are selectively turned on when the output signal of the corresponding AND gate AG3 is at a high level, in other words, when both the internal control signal WP and the corresponding mat selection signal M0 to M3 are at a high level. From the data input buffer DIB to the corresponding data input / output bus D
The write signals supplied via B0 * to DB7 * are supplied to corresponding complementary complementary data lines for reading CR0 * to CR7 *.
To each other.

As described above, in the static RAM of this embodiment, the complementary common data line is connected to the memory array ARY.
0 to ARY3, and dedicated to the write complementary common data lines CW0 * to CW7 * and the read complementary common data lines CR0 * to CR7 *, thereby reducing the load on the sense amplifiers SA0 to SA3. In order to speed up the read operation,
The write complementary common data lines CW0 * to CW7 *
N-channel switch M of switches YS0 to YS3
Memory array ARY0 via OSFETs N7 and N8
To ARY3 of the eight sets of complementary bit lines B0 * to B0
n * and the complementary complementary data line CR0 * for reading.
To CR7 * are connected to designated eight sets of complementary bit lines B0 * to Bn * of the memory arrays ARY0 to ARY3 via P-channel type switch MOSFETs P7 and P8 of Y switches YS0 to YS3.

However, in this embodiment, the static type R
In the write mode of AM, as described above, the data input / output buses DB0 * to DB7 *
Are written from the write circuits WC1 of the unit write amplifiers UWA0 to UWA7 to write complementary common data lines CW0 * to CW7 *, that is, the N-channel type switch MOSFET of the write circuit WC1.
NI and NJ and the N-channel type switch MOSFETs N7 and N8 of the Y switches YS0 to YS3 are transmitted to the selected eight memory cells MC of the memory arrays ARY0 to ARY3, and at the same time, the write circuit W
C2 to read complementary common data lines CR0 * to CR7
*, That is, the complementary gate G of the write circuit WC2
5 and G6 and the P-channel type switch MOSFETs P7 and P8 of the Y switches YS0 to YS3 are transmitted to the selected eight memory cells MC of the memory arrays ARY0 to ARY3. Therefore, the write signal has a high level and a low level which are set to the switch MOSF.
The data is transmitted and written to the selected eight memory cells MC without being reduced by the threshold voltage of ET. As a result, the level margin of the write signal in the write mode of the static RAM is expanded, and the write operation is stabilized.

Next, the sense amplifiers SA0 to SA3 are, as shown by the sense amplifier SA0 in FIG. 4, eight unit sense circuits provided corresponding to the read complementary common data lines CR0 * to CR7 *. Amplifier USA0-USA
7 inclusive. These unit sense amplifiers are coupled to the corresponding complementary complementary data lines for reading CR0 * to CR7 * at one side, that is, at the top of the figure, and correspond to the corresponding data input / output buses DB0 * to DB0 at the other side, that is, at the bottom of the figure.
Connected to DB7 *. Data input / output buses DB0 * -D
As described above, B7 * is coupled to the input terminal of the corresponding unit circuit of the data output buffer DOB, is coupled to the corresponding unit write amplifier of the write amplifiers WA0 to WA3, and furthermore, corresponds to the data input buffer DIB. It is coupled to the output terminal of the unit circuit. Internal sense signals SD and SO are commonly supplied to unit sense amplifiers USA0 to USA7 from timing generation circuit TG, and corresponding mat selection signal M from mat selection circuit MS.
0 to M3 are supplied in common. The data output buffer DOC is supplied with the internal control signal DOC from the timing generation circuit TG.

The internal control signal SD is normally at a low level as shown in FIG.
When M is selected in the read mode, it is selectively set to a high level substantially in synchronization with the internal control signal TCS. The internal control signal SO is normally set to a low level, and is selectively set to a high level substantially in synchronization with the internal control signal CS when the static RAM is selected in the read mode. Further, the internal control signal DOC is normally set to a low level, and is selectively set to a high level in response to a low level change of the output enable signal OEB when the static RAM is selected in the read mode.

The unit sense amplifiers USA0 to USA7 constituting the sense amplifiers SA0 to SA3 include an inverter type CMOS latch VL and a sense amplifier output gate S as representatively represented by the unit sense amplifier USA0 in FIG.
Includes AOG respectively. Among them, inverter type CMO
Although the S latch VL is not particularly limited, the P-channel M
OSFETP9, PA and N-channel MOSFETN
9, NA and P-channel MOSFET PB, PC
And a latch formed by cross-connecting a pair of substantially CMOS inverters including N-channel MOSFETs NB and NC, and a predetermined internal control signal, that is, an AND gate AG1
And an N-channel type drive MOSFET ND selectively turned on in accordance with the output signal of the above and selectively supplying a predetermined operation current to the latch. In addition, MOS
The FETs P9, PA, N9, NA, PB, and PC, and NB and NC are formed by a so-called process common centrate method, whereby errors in mask alignment during gate formation can be corrected.

MOSFETs P9 and P constituting a latch
A and the commonly coupled drains of N9 and NA, i.e. the MOSFETs PB and PC and the commonly coupled gates of NB and NC, are connected to the non-inverting input / output node n of the latch.
a, P-channel transfer MOSFET
Complementary read common data line CR via PI
0 * to CR7 * are coupled to non-inverted signal lines. Also, M
The commonly coupled drains of OSFETs PB and PC and NB and NC, that is, the MOSFETs P9 and PA and the commonly coupled gates of N9 and NA, are the inverting input / output nodes nb of the latch, and correspond via the P-channel transfer MOSFET PJ. It is coupled to the inverted signal lines of the read complementary common data lines CR0 * to CR7 *. The output signals of the AND gate AG1 are supplied to the gates of the transfer MOSFETs PI and PJ via the resistor R3. The resistor R3 is a transfer MOSFET.
A predetermined delay circuit is configured together with the gate capacitances of the TPI and the PJ.

The internal control signal SD is supplied to one input terminal of the AND gate AG1, and the corresponding mat selection signals M0 to M3 are supplied to the other input terminal. As a result, the output signal of AND gate AG1 is set such that when both internal control signal SD and corresponding mat select signals M0-M3 are at a high level, in other words, the static RAM is selected in the read mode and Z address is output. When the corresponding memory arrays ARY0 to ARY3 are designated by the signals AZ0 to AZ1, they are selectively and temporarily set to the high level.

When the output signal of AND gate AG1 is at a low level, corresponding unit sense amplifiers USA0 to USA0
The transfer MOSFETs PI and PJ constituting the inverter type CMOS latch VL of the USA7 are both turned on, and the non-inverted input / output node na and the inverted input / output node nb of the inverter type CMOS latch VL are connected to the corresponding complementary complementary data line CR0 * for reading. .. CR7 *. Therefore, as shown in FIG. 7, the non-inverting input / output node na and the inverting input / output node nb of the inverter type CMOS latch VL correspond to eight memory cells MC coupled to the selected word line. Read complementary data lines CR0 * to CR7
The read signal output via the * is transmitted, and according to these read signals, the MOSFE forming the latch
TP9, PA and N9, NA and PB, PC and N
The parasitic capacitances of the gates of B and NC which are commonly coupled are charged. At this time, the drive MOSFET ND of each unit sense amplifier is turned off because the output signal of the AND gate AG3 is at a low level, and the corresponding inverter type CMOS latch VL is turned off.

On the other hand, when the output signal of AND gate AG1 is set to the high level, the corresponding unit sense amplifier USA
In 0 to USA7, first, the drive MOSFET ND is turned on, and the inverter type CMOS latch VL is turned on. Also, the transfer MOSFET P
I and PJ are turned off, and the unit sense amplifier USA
0 to USA7 are the corresponding complementary complementary data lines C for reading.
It is separated from R0 * to CR7 *. Thereby, the non-inverting input / output node na of the inverter type CMOS latch VL
And the inverted input / output node nb, that is, the MOSFET P9,
PA and N9, NA and PB, PC and NB, NC
The difference in the amount of charge stored in the parasitic capacitance of the common-coupled gates is rapidly expanded and full-swinged to a high level such as a circuit power supply voltage or a low level such as a circuit ground potential.

The output signal of the AND gate AG1 is transmitted to the gate of the transfer MOSFET PI and PJ via the delay circuit including the resistor R3, so that the transfer MOSFETs PI and PJ have passed a predetermined time since the drive MOSFET ND was turned on. Later, it is turned off. As a result, the non-inverting and inverting input / output nodes of the inverter type CMOS latch VL are disconnected from the corresponding complementary common data lines for reading CR0 * to CR7 * when the amplification operation has progressed to some extent. CMOS
The operation margin of the latch VL can be increased.

Next, the unit sense amplifiers USA0 to USA
7 comprises two pairs of a P-channel MOSFET PG and an N-channel MO provided in series between the power supply voltage and the ground potential of the circuit.
Includes SFETNG and P-channel MOSFETPH and N-channel MOSFETNH, respectively. MO
The commonly coupled drains of SFETs PG and NG are coupled to the inverted signal lines of corresponding data input / output buses DB0 * -DB7 *, and the commonly coupled drains of MOSFETs PH and NH are coupled to their non-inverted signal lines. . MO
To the gates of the SFETs PG and NG, an inverted signal of the non-inverted output signal na of the inverter type CMOS latch VL by the inverter V3, that is, an inverted output signal of the inverter type CMOS latch VL is supplied via complementary gates G1 and G3. The gates of the MOSFETs PH and NH are connected to inverter-type CMs through complementary gates G2 and G4.
An inverted signal of the inverted output signal nb of the OS latch VL by the inverter V4, that is, a non-inverted output signal of the inverter type CMOS latch VL is supplied. The output signals of the AND gate AG2 are commonly supplied to the gates of the N-channel MOSFETs forming the complementary gates G1 to G4, and the inverted signal of the inverter V2 is commonly supplied to the gates of the P-channel MOSFETs.

The sense amplifier output gate SAOG further includes a pair of N-channel MOs provided between the output terminals of the inverters V3 and V4 and the ground potential of the circuit.
The power supply voltage of the circuit including SFETs NI and NJ and MOS
A pair of P-channel MOSFETs PE and PF respectively provided between the gates of the FETs PG and PH;
It includes a pair of N-channel MOSFETs NE and NF respectively provided between OSFETs NG and NH and the ground potential of the circuit. Of these, MOSFET NI
And NJ are latched by their gates and drains being cross-coupled to each other. Also, MOSFET
The output signal of the AND gate AG2 is supplied to the gates of PE and PF, and the inverted signal of the inverter V2 is supplied to the gates of the MOSFETs NE and NF.
Further, the internal control signal SO is supplied to one input terminal of the AND gate AG2, and the other input terminal is connected to the other input terminal.
Corresponding mat select signals M0-M3 are supplied. Thereby, the output signal of AND gate AG2 is selectively set to the high level when both internal control signal SO and corresponding mat selection signals M0 to M3 are set to the high level.

When the output signal of AND gate AG2 is at a low level, in other words, when internal control signal SO or corresponding mat select signal M0-M3 is at a low level, sense amplifier output gates of unit sense amplifiers USA0-USA7. In SAOG, complementary gates G1 to G
4 are simultaneously turned off, and the MOSFETs PE and NE
In addition, PF and NF are simultaneously turned on. Therefore, MOSFET PG and NG and PH and NH
Are both turned off, and the unit sense amplifiers USA0 to USA0
USA7 is a corresponding data input / output bus DB0 * to DB7.
* Separated from At this time, the data output buffer D
Since the internal control signal DOC supplied to the OB is at a low level, the data input / output terminals IO0 to IO7 are all in a high impedance state Hz as shown in FIG.

On the other hand, when the static RAM is selected in the read mode and the output signal of the AND gate AG2 is set to the high level, the unit sense amplifiers USA0 to USA
In the sense amplifier output gate SAOG of A7, MOSF
ETPE and NE and PF and NF are turned off, and complementary gates G1 to G4 are turned on instead.
Then, when the internal control signal SD is set to the high level and the corresponding inverter type CMOS latch VL is activated, the non-inverted output signal na and the inverted output signal nb are output via the inverters V3 and V4. Accordingly, MOSFETs PG and NH or PH and NG are complementarily turned on. As a result, as shown in FIG. 7, the level of the non-inverted output signal na or the inverted output signal nb of the inverter type CMOS latch VL is applied to the corresponding data input / output buses DB0 * to DB7 *, as shown in FIG. At the time when the level becomes lower than the threshold level LT, read data corresponding to the read 8-bit storage data is output, and the data output buffer DOB is output.
Is transmitted to the corresponding unit circuit. These read data are sent to the outside of the static RAM from the corresponding data input / output terminals IO0 to IO7 in response to the high level of the internal control signal DOC.

As described above, the unit sense amplifiers USA0 to USA7 constituting the sense amplifiers SA0 to SA3 of the static RAM of this embodiment are substantially composed of a pair of Cs.
Inverter type C in which MOS inverters are cross-coupled
MOS latch VL as its basic component,
An operating current is selectively applied to this latch via a driving MOSFET ND, and its non-inverting and inverting input / output nodes are connected to a pair of transfer MOSFETs PI which are turned off immediately after the driving MOSFET ND is turned on.
And PJ, and are connected to corresponding read complementary common data lines CR0 * to CR7 *. As is well known, the P-channel MOSFET and the N-channel MOSFET constituting a pair of CMOS inverters of the inverter type CMOS latch VL are temporarily turned on simultaneously until the output signal level reaches the power supply voltage of the circuit or the ground potential. After the output signal level reaches the power supply voltage or the ground potential of the circuit, one of them is turned off and no through current flows. In addition, inverter type CMOS
The non-inverting input / output node na and the inverting input / output node nb of the latch VL are connected to the corresponding complementary common data lines for reading CR0 * through transfer MOSFETs PI and PJ.
By being connected to CR7 *, the corresponding complementary complementary data lines for reading CR0 * to CR7 immediately after the operation state is set.
* To reduce the load.

Because of these facts, the output signal is full-swinged, and the unit sense amplifier US
The amplification factor of A0-USA7 is increased, the speed of the read signal amplification operation is increased, and the DC current is reduced. In addition, since the single structure simplifies the circuit configuration of the sense amplifier itself, and since the DC current is small, the sense amplifier can be kept in the operating state even after the end of the read signal amplification operation and used as an output latch.
As a result, while reducing the operating current of the readout circuit, the circuit configuration is simplified, and the static RAM
It is possible to promote cost reduction and power consumption reduction.

As shown in the above-mentioned embodiment, the present invention is applied to a static RA using an auto power down system.
The following effects can be obtained by applying the present invention to a semiconductor memory device such as M. (1) Static type R adopting the auto power down method
In AM and the like, a sense amplifier is constituted by a latch formed by substantially cross-coupled a pair of CMOS inverters, and a driving MOSFE for selectively supplying an operating current to the latch.
And a pair of transfer MOSFETs provided between the non-inverted and inverted input / output nodes of the latch and the non-inverted and inverted signal lines of the complementary common data line, respectively. By turning off the drive amplifier immediately after the drive MOSFET is turned on and the sense amplifier is turned on and disconnecting the sense amplifier from the common data line,
A single inverter-type CMOS latch enables high-speed operation, realizes a sense amplifier having a relatively large amplification factor due to the full swing of its output amplitude, and flowing a DC current only at the time of state transition. The effect that it can be obtained is obtained.

(2) According to the above item (1), the circuit configuration of the sense amplifier itself can be simplified, and the sense amplifier can be kept operating even after the completion of the read signal amplification operation, and can be used as an output latch. The effect is obtained. (3) According to the above items (1) and (2), the operation current of the readout circuit can be reduced, and the circuit configuration can be simplified. (4) In the above items (1) to (3), the driving MOSF
By transmitting the internal control signal supplied to the gate of the ET to the gate of the transfer MOSFET via a predetermined delay circuit, the non-inverting and inverting input / output nodes are connected from the common data line after the sense amplifier is activated. There is an effect that a predetermined time is allowed to elapse before disconnection and the operation margin of the sense amplifier can be expanded.

(5) According to the above items (1) to (3), the memory array is divided in the direction in which the complementary bit lines extend without hindering the cost reduction of the static RAM, and the common data lines are correspondingly divided. Since the wiring length can be shortened,
The effect is obtained that the load on the readout circuit can be reduced and its operation can be further speeded up. (6) According to the above items (1) to (3), the common data line can be dedicated for writing and reading without hindering the cost reduction of the static RAM. Reduce the load on the wire,
The effect is obtained that the operation of the readout circuit can be further speeded up. (7) In the above item (6), the write operation is performed via both the write common data line and the read common data line, thereby preventing the level of the write signal from being lowered by the threshold voltage of the switch MOSFET. Thus, the effect that the operation margin in the write mode can be increased can be obtained. (8) According to the above items (1) to (7), the operation of a static RAM or the like adopting an auto power down method is accelerated and stabilized, and its cost and power consumption are promoted. Is obtained.

Although the invention made by the inventor has been specifically described based on the embodiments, the invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist of the invention. Needless to say, there is. For example, in FIG. 1, the memory array can be divided into an arbitrary number in the bit direction and also into the word line direction. The Z address signals AZ0 to AZ1 can be regarded as a part of the Y address signal, and the number of bits changes according to the division number of the memory array. The static RAM can have an arbitrary bit configuration, and its block configuration, a combination of activation control signals, and the like can take various embodiments.

In FIG. 2, memory arrays ARY0 to ARY0-A
RY3 can include redundant word lines and redundant bit lines. Further, the word lines constituting the memory arrays ARY0 to ARY3 may be directly driven by the main word lines without passing through the sub word line driving circuit. In this case, it goes without saying that the selection level of the main word line is at the high level. The memory cell MC has a high resistance load R
1 and R2 can be replaced by MOSFETs, or so-called CMOS memory cells in which a pair of CMOS inverters are cross-coupled. The specific logical configurations of the sub-word line drive circuits SWD0 to SWDm and the bit line precharge circuits BPC0 to BPCn are not restricted by this embodiment.

In FIG. 3, the write operation of the static RAM does not always have to be performed by using the write and read complementary common data lines. When the write operation is performed only by the complementary complementary data lines for writing, the switch MOSFETs N7 and N8 for selectively connecting the complementary bit lines B0 * to Bn * and the complementary complementary data lines CW0 * to CW7 * are connected. What is necessary is just to replace with the complementary gate which consists of a P channel and an N channel MOSFET. In FIG. 4, data input / output bus D
B0 * to DB7 * may be dedicated as a data input bus and a data output bus, or may be write amplifiers WA0 to WA0.
The block configuration of A3 and the sense amplifiers SA0 to SA3 is not restricted by this embodiment.

In FIG. 5, precharge MOSFETs PM to PO included in write circuit WC2 may be included in corresponding unit sense amplifiers of sense amplifiers SA0 to SA3. When the write operation is performed only via the write complementary common data line as described above, it is necessary to replace the switch MOSFETs NI and NJ of the write circuit WC1 with complementary gates. In FIG. 6, a CM constituting an inverter type CMOS latch VL is shown.
The OS inverter is composed of two P
It need not be composed of channel and N-channel MOSFETs. Further, the delay circuit provided between the gate of the drive MOSFET ND and the gates of the transfer MOSFETs PI and PJ can include individually formed capacitors, or can be constituted by, for example, an even number of stages of inverters. Furthermore, AND gates AG1 to A
G3 may be included in, for example, a timing generation circuit, and specific circuit configurations of the unit write amplifiers UWA0 to UWA7 and the unit sense amplifiers USA0 to USA7 may employ various embodiments. The logic levels of the start control signal and the internal control signal in FIG. 7 and their timing conditions are not restricted by this embodiment.

In the above description, the case where the invention made mainly by the present inventor is applied to a static RAM, which is the field of application as the background, has been described.
The present invention is not limited to this, and can be applied to, for example, a single chip microcomputer including a static RAM, a gate array integrated circuit, and the like, and can also be applied to a semiconductor memory device that does not employ an auto power down method.

[0059]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a static RAM or the like that employs an auto power-down method, a sense amplifier includes a latch substantially formed by cross-coupled a pair of CMOS inverters, a drive MOSFET that selectively supplies an operating current to the latch, A pair of transfer MOSs respectively provided between the non-inverted and inverted input / output nodes of the latch and the non-inverted and inverted signal lines of the complementary common data line
FET and an inverter type CMOS latch including a transfer MOSFET.
The OSFET is turned on and the sense amplifier is turned off immediately after the sense amplifier is turned on, and the sense amplifier is disconnected from the common data line to enable high-speed operation with a single inverter-type CMOS latch, and the output amplitude is reduced. By performing full swing, it is possible to realize a sense amplifier having a relatively large amplification factor and flowing DC current only at the time of state transition. As a result, the circuit configuration of the sense amplifier itself can be simplified, and these sense amplifiers can be kept operating even after the end of the read signal amplification operation, and can be used as an output latch. As a result, it is possible to reduce the operating current of the readout circuit, simplify the circuit configuration, and promote cost reduction and power consumption reduction of a static RAM or the like employing an auto power down method.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a static RAM to which the present invention is applied.

FIG. 2 is a partial circuit diagram showing one embodiment of a memory array included in the static RAM of FIG. 1;

FIG. 3 is a partial circuit diagram showing one embodiment of a Y switch included in the static RAM of FIG. 1;

FIG. 4 is a partial block diagram showing one embodiment of a write amplifier and a sense amplifier included in the static RAM of FIG. 1;

FIG. 5 is a circuit diagram showing an embodiment of a unit write amplifier constituting the write amplifier of FIG. 4;

FIG. 6 is a circuit diagram showing an embodiment of a unit sense amplifier constituting the sense amplifier of FIG. 4;

FIG. 7 is a signal waveform diagram showing one embodiment of a read mode of the static RAM of FIG. 1;

[Explanation of symbols]

ARY0 to ARY3: memory array, XD: X
Address decoder, XB ... X address buffer, Y
S0 to YS3 ... Y switch, YD0 to YD3 ...
Y address decoder, YB... Y address buffer,
MS: mat selection circuit, ZB: Z address buffer, WA0 to WA3: write amplifier, SA0 to S
A3: sense amplifier, DIB: data input buffer, DOB: data output buffer, TG: timing generation circuit. MW0B to MWmB: Main word line, SW0 to S
Wm: sub-word line, B0 * to Bn *: complementary bit line, MC: memory cell, SWD0 to SWDm
..Sub-word line drive circuits, BPC0 to BPCn ...
Bit line precharge circuit. CW0 * to CW7 *: complementary data lines for writing, CR0 * to CR7 *: complementary data lines for reading. UWA0 to UWA7: Unit write amplifier, USA0
~ USA7 ... Unit sense amplifier, DB0 * ~ DB7
* ・ ・ ・ Data input / output bus. VL: Inverter type C
MOS latch, SAOG ... sense amplifier output gate. WC1 to WC2... Write circuit. P1-PO ... P-channel MOSFET, N1-N
J: N-channel MOSFET, G1 to G6 ...
Complementary gates, V1 to V5 ... inverters, AG1 to A
G3 ... AND gate, R1 to R3 ...
resistance.

Continuation of the front page (72) Inventor Yoshiaki Umekawa 145 Nakajima, Nanae-cho, Kameda-gun, Hokkaido Inside Hitachi Kokusai Semiconductor Co., Ltd. (56) References JP-A-64-62896 (JP, A) JP-A-61-148696 ( JP, A) JP-A-1-92990 (JP, A) JP-A-4-102294 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11C 11/41-11/419

Claims (9)

(57) [Claims] 1. A semiconductor memory device of an auto power down system, comprising: a latch having a pair of CMOS inverters cross-coupled; and a driving MOSF for selectively supplying an operating current to the latch.
And a sense amplifier including a pair of transfer MOSFETs provided between the non-inverted and inverted input / output nodes of the latch and the non-inverted and inverted signal lines of the complementary common data line. Storage device. 2. The drive MOSFET according to claim 1, wherein the drive MOSFET comprises a first conductivity type MOSFET which receives an internal control signal at a gate thereof, and wherein each of the transfer MOSFETs receives a second internal control signal at a gate thereof. Conductive MOSFE
A semiconductor memory device comprising T. 3. The transfer MO according to claim 2, wherein the internal control signal is supplied to a gate of the drive MOSFET and then passed through a delay circuit.
A semiconductor memory device supplied to the gate of an SFET. 4. The sense amplifier according to claim 1, wherein the sense amplifier is used as an output latch for holding storage data read from a selected memory cell. Semiconductor storage device. 5. The method according to claim 1, wherein the complementary bit line is divided into a plurality of bit lines,
A semiconductor memory device, wherein a plurality of the above-mentioned complementary common data lines and sense amplifiers are provided corresponding to respective memory arrays including divided complementary bit lines. 6. The first complementary data line according to claim 5, wherein each of said complementary common data lines is selectively connected to a designated complementary bit line of a corresponding memory array via a switch MOSFET of a first conductivity type. A complementary common data line, and a second complementary common data line selectively connected to a designated complementary bit line of a corresponding memory array via a switch MOSFET of a second conductivity type. Semiconductor storage device. 7. The memory device according to claim 6, wherein a write operation of storage data to a selected memory cell of the memory array is performed via the corresponding first and second complementary common data lines, and a read operation thereof is performed. Semiconductor memory device, which is performed via a corresponding second complementary common data line. 8. A semiconductor memory device in which the operation of selecting a word line or a bit line is stopped after a lapse of a first time in a chip selection state, a plurality of memory cells, and a complementary bit line to which the plurality of memory cells are connected. A phase to which a selected one of the complementary bit lines is connected
Has an auxiliary common data line, and a sense amplifier connected to the complementary common data line, the sense amplifier, a semiconductor memory device, characterized in that a latch pair of inverters, which are cross-connected . 9. The latch according to claim 8, wherein each of two input / output nodes of the latch and the complementary input / output node.
Transfer MO between each of the common data lines
A semiconductor memory device to which an SFET is connected.