JPH0745082A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To speed up a static type RAM for which an automatic power down system is adopted and to simplify its circuit so as to reduce a cost and electric power by forming a sense amplifier of specific constitution and passing DC only at the time of state transition. CONSTITUTION:The operating current is selectively supplied from a driving MOSFET ND to a latch VL crossed and coupled with a pair of CMOS inverters and the non-inversion and inversion input and output nodes na, nb of this latch V1 are connected via MOSFET PI, PJ to a corresponding complementary common data line CR for reading out. The sense amplifier is put into an off state right after the amplifier attains an operation state to disconnect the sense amplifier from the common data line CR. As a result, the circuity is simplified and the high-speed operation is made possible by single inverter type CMOS latch. The current is passed at the time of the state transition, by which the operating currents of the reading-out circuit are decreased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, for example, a low power consumption static RAM (random access memory) adopting an auto power down system.
It relates to a technology that is particularly effective for use in.

[0002]

2. Description of the Related Art There is a static RAM having a memory array in which static memory cells are arranged in a lattice as its basic constituent element. Further, in such a static RAM, even when the chip selection state is continued for a relatively long time, the power consumption can be reduced by stopping the selection operation of the word line, the bit line, etc. after a predetermined time. There is a so-called auto power down method.

As for the static type RAM adopting the auto power down method, for example, "IEE Journal" issued in October 1990 is used.
Of Solid State Circuits (Journal
of Solid-State Circuits)
Vol. 25, No. 5 ”to“ 23-ns 4-Mb
CMOS SRAM With 0.2 μA Stan
dby Current ”.

[0004]

The inventors of the present application faced the following problems in an attempt to further reduce the power consumption of the static RAM adopting the auto power down method. That is, in recent years, the so-called multi-bit of the static type RAM has been advanced, and it is necessary to provide a plurality of sense amplifiers corresponding to each bit of read data output simultaneously. However, in the conventional static type RAM adopting the auto power down method, the sense amplifier is configured by a so-called current mirror type sense amplifier, and while this current mirror type sense amplifier can operate at high speed, it has a relatively small amplification factor. It has the drawback of always flowing a direct current while it is in operation. Therefore, in order to obtain a sufficient gain as a sense amplifier, it is unavoidable to adopt a multi-stage structure, and if the operation of the sense amplifier is stopped after the amplification operation is completed in order to reduce the operating current of the sense amplifier,
There is no choice but to separately provide an output latch for holding the amplified read data. As a result, the number of required elements of the read system circuit increases and the current consumption thereof increases, which restricts the cost reduction and the power consumption reduction of the static RAM.

An object of the present invention is to reduce the operating current of a read system circuit and simplify the circuit configuration to promote cost reduction and power consumption reduction of a static RAM or the like which adopts an auto power down system. It is in.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0007]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, in a static RAM or the like that adopts an auto power down system, its sense amplifier includes a latch that is substantially a pair of CMOS inverters cross-coupled, and a drive MOSFET that selectively supplies an operating current to the latch. A pair of transfer MOSFs provided between the non-inverting and inverting input / output nodes of the latch and the non-inverting and inverting signal lines of the complementary common data line, respectively.
It is composed of an inverter type CMOS latch including ET and a transfer MOSFET is a driving MOS.
Immediately after the FET is turned on and the sense amplifier is turned on, the FET is turned off to disconnect the sense amplifier from the common data line.

[0008]

According to the above means, a single inverter type CMO is used.
S-latch enables high-speed operation, and its output amplitude is fully swung to have a relatively large amplification factor.
Moreover, it is possible to realize a sense amplifier that allows a direct current to flow only at the time of state transition. As a result, the circuit configuration of the sense amplifier itself can be simplified, and these sense amplifiers can be used as an output latch while remaining in the operating state even after the amplification operation of the read signal. As a result, the operating current of the read system circuit can be reduced, the circuit configuration can be simplified, and cost reduction and power consumption reduction of the static RAM or the like adopting the auto power down system can be promoted.

[0009]

1 is a block diagram of an embodiment of a static RAM to which the present invention is applied. 2 and 3 are partial circuit diagrams of an embodiment of the memory array and Y switch included in the static RAM of FIG. 1, respectively, and FIG. 4 shows a write amplifier and a sense amplifier. A partial block diagram of one embodiment is shown. 5 and 6 are circuit diagrams of an example of the unit write amplifier and the unit sense amplifier which form the write amplifier and the sense amplifier of FIG. 4, respectively. FIG. 7 shows the static type of FIG. A signal waveform diagram of one embodiment in a read mode of a RAM is shown. Based on these figures, the static RAM of this embodiment
The configuration and operation of and the characteristics thereof will be described. The circuit elements shown in FIGS. 1 to 6 and the circuit elements forming each block are well-known CMOS (complementary MOS).
Due to the manufacturing technology of integrated circuits,
It is formed on each semiconductor substrate. In addition, in the following circuit diagrams, a MOSFET (metal oxide semiconductor type field effect transistor, whose channel (back gate) part is indicated by an arrow. In this specification, MOSFET is a generic term for an insulated gate field effect transistor. Is a P-channel type (second conductivity type) and is shown in distinction from an N-channel type (first conductivity type) without an arrow.

In FIG. 1, the static RAM of this embodiment is not particularly limited, but four memory arrays ARY0 to ARY divided in the extending direction of the complementary bit lines.
3 is its basic component. Corresponding selection drive signals WD0 to WD3 are supplied to these memory arrays from a mat selection circuit MS described later.

The memory arrays ARY0 to ARY3 are shown in FIG.
Of the memory array ARY0, m + 1 sub-word lines S arranged in parallel in the horizontal direction.
N + 1 arranged in parallel with W0 to SWm in the vertical direction
A pair of complementary bit lines B0 * to Bn * (here, for example, the non-inverted bit line B0T and the inverted bit line B0B are collectively denoted by * like a complementary bit line B0 *. Further, it is validated. A so-called non-inverted signal or the like that is selectively set to a high level when it is turned on is represented by adding T to the end of the name, and a so-called inverted signal or the like that is selectively set to a low level when it is enabled is B at the end of the name
It is indicated by adding. The same shall apply hereinafter), and the sub-word lines and the complementary bit lines are arranged in a lattice pattern (m + 1).
Each includes x (n + 1) static memory cells MC.

As shown in FIG. 2, each of the memory cells MC constituting the memory arrays ARY0 to ARY3 has a pair of N-channel drive MOSFETs N1 and N2, the drains of these drive MOSFETs and the power supply voltage of the circuit. And a pair of high resistance loads R1 and R2 provided between and. The gate of the drive MOSFET N1 is a drive M
Drive MOSFET connected to the drain of OSFET N2
The gate of TN2 is coupled to the drain of drive MOSFET N1. As a result, the drive MOSFETs N1 and N2 are
Are cross-coupled to form a latch serving as a storage element of the memory cell MC. The drain of the drive MOSFET N1, that is, the gate of the drive MOSFET N2 serves as a non-inverting input / output node of the memory cell MC, and is an N-channel type selection MOS.
Corresponding complementary bit lines B0 * to Bn via FETN3
Commonly coupled to the * non-inverted signal lines. In addition, the drain of the drive MOSFET N2, that is, the drive MOSFET
The gate of N1 serves as an inversion input / output node of the memory cell MC, and is commonly coupled to the corresponding inversion signal line of the complementary bit lines B0 * to Bn * via the N-channel type selection MOSFET N4. Select MOSFETs N3 and N4
Gates are commonly coupled to the corresponding sub-word lines SW0 to SWm.

Sub word lines SW0 to SWm forming memory arrays ARY0 to ARY3 are coupled to corresponding sub word line drive circuits SWD0 to SWDm. Each of these sub-word line drive circuits, as represented by the sub-word line drive circuit SWD0, represents an N-channel MOSFET N6 provided between the corresponding sub-word lines SW0 to SWm and the ground potential of the circuit, and its common connection. Sub word lines SW0 to SWm corresponding to the drain
P-channel M in the form of a CMOS inverter coupled to
It includes an OSFET P6 and an N-channel MOSFET N5. The commonly coupled gates of the MOSFETs P6 and N5 forming the sub word line drive circuits SWD0 to SWDm are commonly coupled to the corresponding main word lines MW0B to MWmB, respectively. The sources of the MOSFET P6 are commonly supplied with the corresponding selection drive signals WD0 to WD3, and the gates of the MOSFET N6 are commonly supplied with the inverted signals of the inverter V1.

As shown in FIG. 7, the selection drive signals WD0 to WD3 are normally set to a low level like the ground potential of the circuit, the static RAM is set to the selected state, and the Z address signals AZ0 to AZ1 are used. When the corresponding memory arrays ARY0 to ARY3 are designated,
It is selectively set to a high level like the power supply voltage of the circuit in synchronization with an internal control signal TCS described later. Further, the main word lines MW0B to MWmB are normally set to a high level like the power supply voltage of the circuit, the static RAM is selected, and the corresponding row address is designated by the X address signals AX0 to AXi. It is selectively set to a low level like the ground potential of the circuit. The main word lines MW0B to MWmB are connected to the memory arrays ARY0 to ARY0.
It is shared by RY3 and its left end is coupled to the X address decoder XD.

As a result, the sub word lines SW0 to SWm
Is normally set to a low level like the ground potential of the circuit, as shown in FIG. 7, and the corresponding selection drive signal WD
When 0 to WD3 are set to the high level and the corresponding main word lines MW0B to MWmB are set to the low level, the selected state of the high level such as the power supply voltage of the circuit is alternatively selected. Upon receiving the high level of the sub word lines SW0 to SWm, the selection MOSFETs N3 and N4 of the n + 1 memory cells MC arranged in the corresponding rows of the memory arrays ARY0 to ARY3 are turned on selectively and simultaneously. , Read signals according to the data held in each memory cell MC are output to the non-inverted and inverted signal lines of the corresponding complementary bit lines B0 * to Bn *, respectively.

On the other hand, the complementary bit lines B0 * to Bn * forming the memory arrays ARY0 to ARY3 are coupled to the corresponding bit line precharge circuits BPC0 to BPCn on one side, that is, the upper side of the figure, and the other side, that is, the figure. Below, it is coupled to the corresponding switch MOSFET of the corresponding Y switch YS0-YS3.

Bit line precharge circuits BPC0 to BP
As represented by the bit line precharge circuit BPC0 in FIG. 2, Cn is provided between the power supply voltage of the circuit and the corresponding non-inverted and inverted signal lines of the complementary bit lines B0 * to Bn *, respectively. P channel type load MO
Three P-channel type precharges provided between the SFETs P1 and P2 and the non-inverting and inverting signal lines of the complementary bit lines B0 * to Bn * corresponding to the power supply voltage of the circuit and between the non-inverting and inverting signal lines MOSFET P3 to P5
Including and respectively. Of these, the load MOSFETs P1 and P2 are in a so-called latch form because their gates and drains are cross-coupled, and the precharge MOSFEs are used.
Corresponding precharge control signals PC0 to PC3 are commonly supplied to the gates of TP3 to P5. The load MOSFETs P1 and P2 are designed to have a relatively small conductance. Further, the precharge control signals PC0 to PC3 are, for example, static type R
When AM is in a non-selected state, it is at a low level, and when it is in a selected state, it is at a high level.

As a result, the precharge MOSFET P
3 to P5 are corresponding precharge control signals PC0 to PC0 when the static RAM is in the non-selected state, for example.
Upon receiving the low level of PC3, it is selectively turned on,
The non-inverted and inverted signal lines of the corresponding complementary bit lines B0 * to Bn * are precharged to a high level like the power supply voltage of the circuit. Further, the load MOSFETs P1 and P2 output from the n + 1 memory cells MC coupled to the selected word lines W0 to Wm to the corresponding complementary bit lines B0 * to Bn * when the static RAM is in the selected state. This serves to promote the change of the read signal to be read and to increase the signal amount.

Returning to the explanation of FIG. The X address decoder XD is supplied with the internal address signals X0 to Xi of i + 1 bits from the X address buffer XB and the internal control signal TCS from the timing generation circuit TG. The X address buffer XB has address input terminals AX0-A.
X address signals AX0 to AXi are supplied via Xi. As shown in FIG. 7, the internal control signal TCS is set to a low level such as the ground potential of the normal circuit, and selectively changes to a high level such as the power supply voltage of the circuit in response to the low level change of the chip selection signal CSB. However, after that, when a predetermined time tcs elapses, it is returned to the low level. This time tcs corresponds to the minimum time required for the write or read operation of the stored data, and indicates the timing to enter the auto power down state when the static RAM is kept in the selected state for a longer period than necessary. Served to set up.

The X address buffer XB has an address input terminal A when the static RAM is selected.
X address signal AX0 supplied via X0 to AXi
.About.AXi are fetched and held, and internal address signals X0 to Xi are formed based on these X address signals and supplied to the X address decoder XD. Further, the X address decoder XD receives the high level of the internal control signal TCS and is selectively brought into the operating state, decodes the internal address signals X0 to Xi supplied from the X address buffer XB, and outputs the corresponding one. Main word line MW0B to M
WmB is alternatively set to a low level selection level such as the ground potential of the circuit. As described above, the internal control signal TCS
Is set to a high level for a predetermined time tcs, and the main word line selecting operation by the X address decoder XD and the sub word line selecting operation in the memory arrays ARY0 to ARY3 are also performed for this time tcs. As a result, even when the static RAM is in the selected state for a relatively long period, it is in the auto power down state, and power consumption can be reduced.

Next, the Y switches YS0 to YS3 are operated as shown in FIG.
As represented by the Y switch YS0, the complementary bit lines B0 * to Bn of the memory arrays ARY0 to ARY3 are represented.
An N-channel type n + 1 pair of switch MOSFETs N7 and N8 provided corresponding to * and a P-channel type n + 1 pair of switch MOSFETs P7 and P8 are included, respectively. Of these, switch MOSFETs N7 and N
8 is coupled to the non-inverted or inverted signal lines of the corresponding complementary bit lines B0 * to Bn * of the memory arrays ARY0 to ARY3, respectively, and the other is written to the write complementary common data lines CW0 * to CW7 * (first One complementary common data line) is commonly coupled to non-inverted or inverted signal lines every eight pairs. The gates of these switch MOSFETs are connected in common in order by 8 pairs, and Y address decoders YD0 to YD3 are connected.
Corresponding bit line selection signals YSW0 to YSWp are supplied. Similarly, switch MOSFETs P7 and P8
One is coupled to the non-inverted or inverted signal line of the corresponding complementary bit line B0 * to Bn * of the memory arrays ARY0 to ARY3, respectively, and the other is read complementary common data lines CR0 * to CR7 * (second Complementary common data line)
Are commonly coupled to the non-inverted or inverted signal lines every 8 pairs.
Eight pairs of these switch MOSFET gates are commonly connected in order, and corresponding bit line selection signals YSR0 to YSRp are supplied from Y address decoders YD0 to YD3.

Bit line selection signals YSW0 to YSW
It goes without saying that p and the number of bits p + 1 of YSR0 to YSRp are in the relationship of p + 1 = (n + 1) / 8. Y switch YS
0 to YS3 write complementary common data lines CW0 * to C
W7 * is coupled to corresponding write amplifiers WA0-WA3, respectively. In addition, the read complementary common data line C
R0 * to CR7 * are corresponding write amplifiers WA0 to WA
A3 is coupled to each of the sense amplifiers SA0 to SA3.

As a result, the switch MOSFETs N7 and N8 forming the Y switches YS0 to YS3 are selectively turned on by 8 pairs by setting the corresponding bit line selection signals YSW0 to YSWp to the high level, and the corresponding memories are turned on. Eight sets of designated complementary bit lines B0 * to Bn * and write complementary common data lines CW0 * to CW7 * of the arrays ARY0 to ARY3, that is, write amplifiers WA0 to WA0.
The WA3 is selectively connected. Similarly, a switch MOSFET P7 forming the Y switches YS0 to YS3
And P8 are corresponding bit line selection signals YSR0 to YS.
By turning Rp to a high level, eight pairs are selectively turned on, and the corresponding memory arrays ARY0 to ARY3 are turned on.
8 complementary bit lines B0 * to Bn * and read complementary common data lines CR0 * to CR7 *, that is, write amplifiers WA0 to WA3 and sense amplifier SA0.
~ SA3 are selectively connected.

Thus, the complementary common data lines are provided corresponding to the memory arrays ARY0 to ARY3, and are dedicated as the write complementary common data lines CW0 * to CW7 * and the read complementary common data lines CR0 * to CR * 7. By increasing the speed, the level change of the complementary common data line is speeded up especially during the read operation, and the static RAM
The read operation can be speeded up. A write complementary common data line and a read complementary common data line are provided corresponding to the memory arrays ARY0 to ARY3, and the sense amplifiers SA0 to SA3 are provided in the memory array ARY.
The provision of 0 to ARY3 leads to an increase in the hardware amount of the sense amplifier, that is, the read system circuit, but in this embodiment, as will be described later, each unit sense amplifier of the sense amplifiers SA0 to SA3 is an inverter. Since it is constituted by a CMOS CMOS type latch, there is no problem. In other words, in this embodiment, each unit sense amplifier of the sense amplifiers SA0 to SA3 is an inverter type C
By being configured with a MOS latch, the complementary common data line can be divided without considering the hardware amount of the sense amplifier, and the read operation can be speeded up.

The Y address decoders YD0 to YD3 include
The Y address buffer YB supplies j + 1-bit internal address signals Y0 to Yj, the timing generation circuit TG supplies an internal control signal TCS, and the mat selection circuit MS supplies corresponding mat selection signals M0 to M3. . The Y address buffer YB has Y address signals AY0 to AY0 via address input terminals AY0 to AYj.
AYj is supplied. Further, the mat selection circuit MS includes
2-bit internal address signals Z0 to Z1 are supplied from Z address buffer ZB, and internal control signals CS and TCS are supplied from timing generation circuit TG. Z address signals AZ0 to AZ1 are supplied to Z address buffer ZB via address input terminals AZ0 to AZ1. As shown in FIG. 7, the internal control signal CS is normally at the low level, and when the static RAM is brought into the selected state in response to the low level change of the chip selection signal CSB,
It is set to high level while the chip selection signal CSB is set to low level.

The Z address buffer ZB has an address input terminal A when the static RAM is in the selected state.
Z address signal AZ0 supplied via Z0 to AZ1
.About.AZ1 are fetched and held, and internal address signals Z0 to Z1 are formed based on these Z address signals and supplied to the mat selection circuit MS. The mat selection circuit MS receives the high level of the internal control signal CS and is selectively activated to decode the internal address signals Z0 to Z1 supplied from the Z address buffer ZB. Then, the corresponding mat selection signals M0 to M3 are alternatively set to the high level almost in synchronism with the internal control signal CS, and the corresponding selection drive signal W almost in synchronism with the internal control signal TCS.
D0 to WD3 are alternatively set to the high level.

Similarly, the Y address buffer YB fetches and holds the Y address signals AY0 to AYj supplied via the address input terminals AY0 to AYj when the static RAM is in the selected state, and at the same time, these are held. Internal address signals Y0 to Y based on the Y address signal
j is formed and supplied to the Y address decoders YD0 to YD3. The Y address decoders YD0 to YD3 are selectively activated by the internal control signal TCS being set to the high level and the corresponding mat selection signals M0 to M3 being set to the high level, and supplied from the Y address buffer YB. The internal address signals Y0 to Yj are decoded and the bit line selection signals YSW0 to YSWp and YSR0 to
YSRp is selectively set to a high level under a predetermined condition. As described above, the internal control signal TCS is set to the high level for a predetermined time tcs, and the Y address decoders YD0 to YD
3 and the bit line B by the Y switches YS0 to YS3
The selection operation of 0 * to Bn * is also performed for the time tcs.
As a result, even when the static RAM is in the selected state for a relatively long period, it is in the auto power down state, and power consumption can be reduced.

The write amplifiers WA0 to WA3 correspond to the write complementary common data lines CW0 * to CW7 * and the read complementary common data lines CR0 * to CR7 * as represented by the write amplifier WA0 in FIG. 8 unit write amplifiers UWA0 to UWA7 are provided respectively. These unit write amplifiers are respectively coupled to the corresponding complementary complementary common data lines CW0 * to CW7 * for reading and complementary complementary data lines CR0 * to CR7 * for reading at one side, that is, at the upper side of the figure, and the other side, that is, at the upper side of the figure. Below, it is coupled to corresponding data input / output buses DB0 * to DB7 *. The data input / output buses DB0 * to DB7 * are coupled to the output terminals of the corresponding unit circuits of the data input buffer DIB and to the corresponding unit sense amplifiers of the sense amplifiers SA0 to SA3, and further to the data output buffer DOB. It is coupled to the input terminal of the corresponding unit circuit. An internal control signal WP is commonly supplied from the timing generation circuit TG to the unit write amplifiers UWA0 to UWA7, and the mat selection circuit M
Corresponding mat selection signals M0 to M3 are commonly supplied from S. The internal control signal WP is normally set to low level, and temporarily set to high level at a predetermined timing when the static RAM is selected in the write mode. As described above, the mat select signals M0 to M3 are normally set to the low level, and when the static RAM is in the selected state, the Z address signals AZ0 to AZ0.
It is alternatively set to a high level according to AZ1.

The data input buffer DIB fetches write data supplied via the data input / output terminals IO0 to IO7 when the static RAM is selected in the write mode, and the data input / output buses DB0 * to DB0 * D.
It is transmitted to the unit write amplifiers UWA0 to UWA7 of the write amplifiers WA0 to WA3 via B7 *.

The unit write amplifiers UWA0 to UWA7 constituting the write amplifiers WA0 to WA3 are composed of two write circuits WC1 (first write circuit) and WC2 as represented by the unit write amplifier UWA0 in FIG.
Each includes a (second write circuit), an AND gate AG3 and an inverter V5 which are provided commonly to these write circuits. The internal control signal WP is supplied to one input terminal of the AND gate AG3, and the corresponding mat selection signals M0 to M are supplied to the other input terminals.
3 is supplied. Thus, the output signal of the AND gate AG3 is selectively set to the high level when the internal control signal WP is set to the high level and the corresponding mat selection signals M0 to M3 are set to the high level.

The write circuit WC1 is a pair of P-channel type precharge MOSFETs PK and PL provided between the power supply voltage of the circuit and the non-inverted and inverted signal lines of the write complementary common data lines CW0 * to CW7 *, respectively.
And the data input / output bus DB corresponding to the non-inverted and inverted signal lines of the write complementary common data lines CW0 * to CW7 *
A pair of N-channel type switch MOSFs provided between the non-inversion and inversion signal lines of 0 * to DB7 *, respectively.
It includes ETNI and NJ, respectively. Precharge MO
SFET PK and PL and switch MOSFET N
The output signal of the AND gate AG3 is commonly supplied to the gates of I and NJ.

As a result, the precharge MOSFETs PK and PL constituting the write circuit WC1 are set to the low level when the output signal of the corresponding AND gate AG3 is set to the low level, in other words, the internal control signal WP is set to the low level or the corresponding mat selection. When the signal M0 is set to low level, it is selectively turned on, and the corresponding non-inverted and inverted signal lines of the write complementary common data lines CW0 * to CW7 * are precharged to a high level such as the power supply voltage of the circuit. Further, the switch MOSFETs NI and NJ forming the write circuit WC1 are high level when the output signal of the corresponding AND gate AG3 is high level, in other words, the internal control signal WP and the corresponding mat selection signals M0 to M3 are both high level. Is selectively turned on, and the data input buffer DIB described later
From the corresponding data input / output buses DB0 * to DB7 * are transmitted to the corresponding write complementary common data lines CW0 * to CW7 *, respectively.

On the other hand, the write circuit WC2 has a circuit power supply voltage and read complementary common data lines CR0 * to CR7 *.
Non-inverting and inverting signal lines, and three P-channel type precharge MOSFETs PM to PO respectively provided between the non-inverting and inverting signal lines and non-inverting of the read complementary common data lines CR0 * to CR7 *. And a pair of complementary gates G5 and G6 respectively provided between the inverted signal line and the non-inverted and inverted signal lines of the corresponding data input / output buses DB0 * to DB7 *. The gates of the precharge MOSFETs PM to PO have corresponding precharge control signals PCD from the timing generation circuit TG.
0 to PCD3 are commonly supplied. In addition, an N channel MOSFE forming complementary gates G5 and G6
The output signal of the AND gate AG3 is supplied to the gate of T, and the inverted signal of the inverter V5 is supplied to the gate of the P-channel MOSFET.

As a result, the precharge MOSFETs PM to PO forming the write circuit WC2 are set to a low level when the corresponding precharge control signals PCD0 to PCD3 are at a low level, in other words, for example, static type R.
When AM is in a non-selected state, it is selectively turned on, and the corresponding read complementary common data lines CR0 * to C
The non-inverted and inverted signal lines of R7 * are precharged to a high level like the power supply voltage of the circuit. Also, the complementary gate G
5 and G6 are selectively turned on when the output signal of the corresponding AND gate AG3 is at a high level, in other words, when the internal control signal WP and the corresponding mat selection signals M0 to M3 are both at a high level. From the data input buffer DIB to the corresponding data input / output bus D
Read complementary common data lines CR0 * to CR7 * corresponding to write signals supplied via B0 * to DB7 *
Communicate to each.

As described above, in the static RAM of this embodiment, the complementary common data lines are connected to the memory array ARY.
0 to ARY3, and dedicated for the write complementary common data lines CW0 * to CW7 * and the read complementary common data lines CR0 * to CR7 *, the load on the sense amplifiers SA0 to SA3 is reduced. , I am trying to speed up the read operation, but at this time,
Write complementary common data lines CW0 * to CW7 * are set to Y
N channel type switch M of switches YS0 to YS3
Memory array ARY0 via OSFETs N7 and N8
To ARY3 designated eight sets of complementary bit lines B0 * to B
Complementary common data line for reading CR0 * connected to n *
.About.CR7 * are connected to designated eight sets of complementary bit lines B0 * to Bn * of the memory arrays ARY0 to ARY3 through the P-channel type switch MOSFETs P7 and P8 of the Y switches YS0 to YS3.

However, the static type R of this embodiment is
In the AM write mode, the data input / output buses DB0 * to DB7 * are transferred from the data input buffer DIB as described above.
The write signal output via the write-in common signal lines CW0 * to CW7 * for writing from the write circuit WC1 of the unit write amplifiers UWA0 to UWA7, that is, the N-channel switch MOSFET of the write circuit WC1.
The write circuit W is simultaneously transmitted to the selected eight memory cells MC of the memory arrays ARY0 to ARY3 through the NI and NJ and the N-channel type switch MOSFETs N7 and N8 of the Y switches YS0 to YS3.
Complementary common data lines CR0 * to CR7 for reading from C2
Through *, that is, the complementary gate G of the write circuit WC2
5 and G6 and the P-channel type switch MOSFETs P7 and P8 of the Y switches YS0 to YS3 are transmitted to the selected eight memory cells MC of the memory arrays ARY0 to ARY3. Therefore, the high level and the low level of the write signal are the switch MOSF.
It is transmitted to and written in the selected eight memory cells MC without being lowered by the threshold voltage of ET. As a result, the level margin of the write signal in the write mode of the static RAM is expanded, and the write operation is stabilized.

Next, the sense amplifiers SA0 to SA3 are provided with eight unit senses corresponding to the read complementary common data lines CR0 * to CR7 *, as represented by the sense amplifier SA0 in FIG. Amplifier USA0 to USA
Including 7. These unit sense amplifiers are connected to corresponding read complementary common data lines CR0 * to CR7 * on one side, that is, on the upper side of the drawing, and on the other side, that is, on the lower side of the drawing, corresponding data input / output buses DB0 * to DB0 *.
It is linked to DB7 *. Data input / output bus DB0 * to D
As described above, B7 * is coupled to the input terminal of the corresponding unit circuit of the data output buffer DOB, coupled to the corresponding unit write amplifier of the write amplifiers WA0 to WA3, and further to the corresponding data input buffer DIB. It is coupled to the output terminal of the unit circuit. The unit sense amplifiers USA0 to USA7 are supplied with the internal control signals SD and SO from the timing generation circuit TG in common and the corresponding mat selection signal M from the mat selection circuit MS.
0 to M3 are commonly supplied. Further, the data output buffer DOB is supplied with the internal control signal DOC from the timing generation circuit TG.

The internal control signal SD is normally at a low level as shown in FIG.
When M is selected in the read mode, it is selectively set to the high level almost in synchronization with the internal control signal TCS. Further, the internal control signal SO is normally set to low level, and is selectively set to high level almost in synchronization with the internal control signal CS when the static RAM is selected in the read mode. Further, the internal control signal DOC is normally set to the low level and selectively set to the high level in response to the change of the output enable signal OEB to the low level when the static RAM is selected in the read mode.

The unit sense amplifiers USA0 to USA7 forming the sense amplifiers SA0 to SA3 are, as represented by the unit sense amplifier USA0 of FIG. 6, represented by an inverter type CMOS latch VL and a sense amplifier output gate S.
Includes each AOG. Of these, the inverter type CMO
The S latch VL is not particularly limited, but the P channel M
OSFET P9, PA and N-channel MOSFET N
9, NA and P-channel MOSFET PB, PC
And a latch formed by cross-coupling a pair of substantial CMOS inverters composed of N-channel MOSFETs NB and NC, and a predetermined internal control signal, that is, an AND gate AG1.
And an N-channel type drive MOSFET ND which is selectively turned on in accordance with the output signal of N.sub.2 and selectively supplies a predetermined operating current to the latch. In addition, MOS
The FETs P9 and PA, N9 and NA, PB and PC, and NB and NC are formed by a so-called process common centrate method, and by this, an error in mask alignment at the time of forming a gate can be corrected.

MOSFETs P9 and P forming a latch
The common-coupled drains of A and N9 and NA, ie the common-coupled gates of MOSFETs PB and PC and NB and NC, are connected to the non-inverting input / output node n of the latch.
a, a P-channel transfer MOSFET
Corresponding complementary common data line CR for reading via PI
It is connected to the non-inverted signal line of 0 * to CR7 *. Also, M
The commonly coupled drains of the OSFETs PB and PC and NB and NC, that is, the commonly coupled gates of the MOSFETs P9 and PA and N9 and NA are used as the inverting input / output node nb of the latch and correspond to each other via the P-channel transfer MOSFET PJ. Read complementary common data lines CR0 * to CR7 * are connected to inverted signal lines. The output signals of the AND gate AG1 are supplied to the gates of the transfer MOSFETs PI and PJ via the resistor R3. The resistor R3 is a transfer MOSFET.
A predetermined delay circuit is configured with the gate capacitances of TPI and PJ.

The internal control signal SD is supplied to one input terminal of the AND gate AG1, and the corresponding mat selection signals M0 to M3 are supplied to the other input terminal. As a result, the output signal of the AND gate AG1 is set to the high level when the mat control signals M0 to M3 corresponding to the internal control signal SD are both set to the high level, in other words, the static RAM is selected in the read mode and the Z address is set. When the corresponding memory arrays ARY0 to ARY3 are designated by the signals AZ0 to AZ1, they are selectively and temporarily brought to the high level.

When the output signal of the AND gate AG1 is set to low level, the corresponding unit sense amplifiers USA0 to USA0.
The transfer MOSFETs PI and PJ forming the inverter type CMOS latch VL of the USA 7 are both turned on, and the non-inverting input / output node na and the inverting input / output node nb of the inverter type CMOS latch VL correspond to the corresponding complementary complementary common data line CR0 * for reading. Connected to non-inverting and inverting signal lines of ~ CR7 *. Therefore, the non-inverting input / output node na and the inverting input / output node nb of the inverter type CMOS latch VL correspond to the eight memory cells MC coupled to the selected word line, as shown in FIG. Read complementary common data lines CR0 * to CR7
Read signals that are output via * are transmitted, and in accordance with these read signals, the MOSFE that forms the latch
TP9, PA and N9, NA and PB, PC and N
The parasitic capacitances of the commonly coupled gates of B and NC are charged. At this time, the drive MOSFET ND of each unit sense amplifier is turned off because the output signal of the AND gate AG3 is low level, and the corresponding inverter type CMOS latch VL is deactivated.

On the other hand, when the output signal of the AND gate AG1 is set to the high level, the corresponding unit sense amplifier USA
In 0 to USA7, the drive MOSFET ND is first turned on and the inverter type CMOS latch VL is turned on. In addition, the transfer MOSFET P is slightly delayed.
I and PJ are turned off, and unit sense amplifier USA
0 to USA7 are corresponding complementary common data lines C for reading
Separated from R0 * to CR7 *. As a result, the non-inverting input / output node na of the inverter type CMOS latch VL is
And the inverted input / output node nb, that is, the MOSFET P9,
PA and N9, NA and PB, PC and NB, NC
The difference in the amount of charge stored in the parasitic capacitance of the commonly coupled gates is rapidly widened, and is fully swung to a high level such as the power supply voltage of the circuit or a low level such as the ground potential of the circuit.

Since the output signal of the AND gate AG1 is transmitted to its gate through the delay circuit including the resistor R3, the transfer MOSFETs PI and PJ have passed a predetermined time after the drive MOSFET ND is turned on. It is turned off later. As a result, the non-inverting and inverting input / output nodes of the inverter type CMOS latch VL are disconnected from the corresponding read complementary common data lines CR0 * to CR7 * when the amplifying operation progresses to a certain extent, whereby the inverter type CMOS
The operation margin of the latch VL can be increased.

Next, the unit sense amplifiers USA0 to USA
The sense amplifier output gate SAOG constituting 7 includes two pairs of P-channel MOSFET PG and N-channel MO provided in series between the power supply voltage and the ground potential of the circuit.
It includes SFETNG and P-channel MOSFET PH and N-channel MOSFET NH, respectively. MO
The commonly coupled drains of SFETPG and NG are coupled to the inverted signal lines of the corresponding data input / output buses DB0 * to DB7 *, and the commonly coupled drains of MOSFETs PH and NH are coupled to their non-inverted signal lines. . MO
An inverted signal of the non-inverted output signal na of the inverter type CMOS latch VL by the inverter V3, that is, an inverted output signal of the inverter type CMOS latch VL is supplied to the gates of the SFETPG and NG via the complementary gates G1 and G3. Further, the gates of the MOSFETs PH and NH are connected to the inverter type CM via complementary gates G2 and G4.
An inverted signal of the inverted output signal nb of the OS latch VL by the inverter V4, that is, a non-inverted output signal of the inverter type CMOS latch VL is supplied. The output signal of the AND gate AG2 is commonly supplied to the gates of the N-channel MOSFETs forming the complementary gates G1 to G4, and the inverted signal of the inverter V2 is commonly supplied to the gates of the P-channel MOSFETs.

The sense amplifier output gate SAOG further includes a pair of N-channel MOs provided between the output terminals of the inverters V3 and V4 and the ground potential of the circuit.
Including SFETNI and NJ, circuit power supply voltage and MOS
A pair of P-channel MOSFETs PE and PF provided between the gates of FETPG and PH, respectively, and M
It includes a pair of N-channel MOSFETs NE and NF respectively provided between OSFETs NG and NH and the ground potential of the circuit. Of these, MOSFETNI
, And NJ are latched by having their gates and drains cross-coupled to each other. Also MOSFET
The output signal of the AND gate AG2 is supplied to the gates of PE and PF, and the inverted signal of the inverter V2 is supplied to the gates of the MOSFETs NE and NF.
Further, the internal control signal SO is supplied to one input terminal of the AND gate AG2, and the other input terminal is
Corresponding mat selection signals M0 to M3 are supplied. As a result, the output signal of the AND gate AG2 is selectively set to the high level when the internal control signal SO and the corresponding mat selection signals M0 to M3 are both set to the high level.

When the output signal of the AND gate AG2 is at the low level, in other words, when the internal control signal SO or the corresponding mat selection signals M0 to M3 is at the low level, the sense amplifier output gates of the unit sense amplifiers USA0 to USA7. In SAOG, complementary gates G1 to G
4 are turned off all at once, and MOSFETPE and NE are
Also, PF and NF are simultaneously turned on. Therefore, MOSFET PG and NG and PH and NH
Are both turned off, and the unit sense amplifiers USA0 to USA0
USA7 is the corresponding data input / output bus DB0 * to DB7
Separated from * At this time, the data output buffer D
Since the internal control signal DOC supplied to OB is at low level, the data input / output terminals IO0 to IO7 are both in the high impedance state Hz, as shown in FIG.

On the other hand, when the static type RAM is selected in the read mode and the output signal of the AND gate AG2 is set to the high level, the unit sense amplifiers USA0 to USA are used.
In the sense amplifier output gate SAOG of A7, MOSF
ETPE and NE and PF and NF are turned off, and complementary gates G1 to G4 are turned on instead.
Then, when the internal control signal SD is set to the high level and the corresponding inverter type CMOS latch VL is activated, the non-inverted output signal na and the inverted output signal nb are output via the inverters V3 and V4, and this Accordingly, MOSFETs PG and NH or PH and NG are complementarily turned on. As a result, as shown in FIG. 7, the level of the non-inverted output signal na or the inverted output signal nb of the inverter type CMOS latch VL is changed to the logic level of the inverter V3 or V4 on the corresponding data input / output bus DB0 * to DB7 *. When it becomes lower than the threshold level LT, read data corresponding to the read 8-bit storage data is output, and the data output buffer DOB
Is transmitted to the corresponding unit circuit. Upon receipt of the high level of the internal control signal DOC, these read data are sent to the outside of the static RAM from the corresponding data input / output terminals IO0 to IO7.

As described above, the unit sense amplifiers USA0 to USA7 forming the sense amplifiers SA0 to SA3 of the static RAM of this embodiment are substantially composed of a pair of Cs.
Inverter type C in which MOS inverters are cross-coupled
With the MOS latch VL as its basic constituent element,
An operating current is selectively applied to this latch via the driving MOSFET ND, and its non-inverting and inverting input / output nodes are turned off immediately after the driving MOSFET ND is turned on.
, And PJ to the corresponding read complementary common data lines CR0 * to CR7 *. As is well known, the P-channel MOSFET and the N-channel MOSFET forming a pair of CMOS inverters of the inverter type CMOS latch VL are temporarily turned on simultaneously until the output signal level reaches the power supply voltage or the ground potential of the circuit. However, after the output signal level reaches the power supply voltage or the ground potential of the circuit, one of them is turned off and the through current does not flow. Inverter type CMOS
The non-inverting input / output node na and the inverting input / output node nb of the latch VL correspond to corresponding read complementary common data lines CR0 * through the transfer MOSFETs PI and PJ.
By connecting to CR7 *, the corresponding read complementary common data lines CR0 * to CR7 immediately after being brought into the operating state
It is separated from * to reduce the load.

Due to these facts, the output signal thereof is fully swung, and the unit sense amplifier US
The amplification factor of A0 to USA7 is increased, the amplification operation of the read signal is speeded up, and the direct current is reduced. Further, since the sense amplifier has a single structure, the circuit configuration of the sense amplifier itself is simplified, and since the direct current is small, it can be used as it is after the amplification operation of the read signal and used as an output latch.
As a result, while reducing the operating current of the read system circuit, the circuit configuration is simplified and the static RAM
It is possible to promote cost reduction and power consumption reduction of.

As shown in the above embodiment, the present invention is a static type RA adopting an auto power down system.
When applied to a semiconductor memory device such as M, the following operational effects can be obtained. That is, (1) static type R adopting the auto power down method
In an AM or the like, the sense amplifier is composed of a latch substantially composed of a pair of CMOS inverters cross-coupled with each other, and a drive MOSFE for selectively supplying an operating current to the latch.
T and a pair of transfer MOSFETs provided between the non-inverting and inverting input / output nodes of the latch and the non-inverting and inverting signal lines of the complementary common data line, respectively. , The drive MOSFET is turned on and the sense amplifier is turned off immediately after being activated, and the sense amplifier is disconnected from the common data line.
A single inverter-type CMOS latch enables high-speed operation, and its output amplitude is fully swung to have a relatively large amplification factor, and it is possible to realize a sense amplifier in which a direct current flows only at the time of state transition. The effect of being able to be obtained is obtained.

(2) According to the above item (1), the circuit configuration of the sense amplifier itself can be simplified, and the sense amplifier can be used as an output latch even after the read signal amplification operation is completed. The effect is obtained. (3) According to the above items (1) and (2), it is possible to reduce the operating current of the readout system circuit and simplify the circuit configuration. (4) In the above items (1) to (3), the driving MOSF
By transmitting the internal control signal supplied to the gate of ET to the gate of the transfer MOSFET through a predetermined delay circuit, the non-inverting and inverting input / output nodes of the sense amplifier are operated from the common data line. It is possible to obtain an effect that the operation margin of the sense amplifier can be expanded by allowing a predetermined time before being separated.

(5) According to the above items (1) to (3), the memory array is divided in the extending direction of the complementary bit lines without hindering the cost reduction of the static RAM, and the common data lines are correspondingly divided. Since the wiring length can be shortened,
There is an effect that the load of the read system circuit can be reduced and the operation can be further speeded up. (6) According to the above items (1) to (3), since the common data line can be dedicated for writing and reading without hindering the cost reduction of the static RAM, especially the common data for reading Reduce the load on the wire,
An effect that the operation of the read system circuit can be further speeded up is obtained. (7) In the above item (6), the write operation is performed via both the write common data line and the read common data line to prevent the level of the write signal from decreasing due to the threshold voltage of the switch MOSFET. The effect that the operation margin in the write mode can be increased is obtained. (8) According to the above items (1) to (7), the cost and power consumption of the static RAM adopting the auto power-down method should be promoted while speeding up and stabilizing the operation. The effect of being able to do is obtained.

Although the invention made by the present inventor has been concretely described based on the embodiments, the invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, the memory array can be divided into any number in the bit direction, and can also be divided into the word line direction. The Z address signals AZ0 to AZ1 can be regarded as a part of the Y address signal, and the number of bits thereof also changes according to the number of divisions of the memory array. The static RAM can have any bit configuration, and its block configuration, combination of activation control signals, and the like can take various embodiments.

In FIG. 2, memory arrays ARY0-ARY
RY3 can include redundant word lines and redundant bit lines. Further, the word lines forming the memory arrays ARY0 to ARY3 may be directly driven by the main word line without passing through the sub word line drive circuit. In this case, it goes without saying that the selection level of the main word line becomes high level. The memory cell MC has a high resistance load R
1 and R2 can be replaced by MOSFETs, or can be a so-called CMOS memory cell in which a pair of CMOS inverters are cross-coupled. The specific logical configurations of the sub word line drive circuits SWD0 to SWDm and the bit line precharge circuits BPC0 to BPCn are not restricted by this embodiment.

In FIG. 3, the write operation of the static RAM does not necessarily require the use of the write and read complementary common data lines. When the write operation is performed by only the write complementary common data line, the switch MOSFETs N7 and N8 for selectively connecting the complementary bit lines B0 * to Bn * and the write complementary common data lines CW0 * to CW7 * are provided. It may be replaced with a complementary gate composed of P-channel and N-channel MOSFETs. In FIG. 4, the data input / output bus D
B0 * to DB7 * may be dedicated as data input buses and data output buses, or write amplifiers WA0 to WA
The block configuration of A3 and the sense amplifiers SA0 to SA3 is not restricted by this embodiment.

In FIG. 5, the precharge MOSFETs PM to PO included in the write circuit WC2 may be included in the corresponding unit sense amplifiers of the sense amplifiers SA0 to SA3. Further, when the write operation is performed via only the write complementary common data line as described above, it is necessary to replace the switch MOSFETs NI and NJ of the write circuit WC1 with the complementary gates. In FIG. 6, a CM that constitutes an inverter type CMOS latch VL
The OS inverter includes two P inverters which are not always in parallel form.
It need not consist of channel and N-channel MOSFETs. Further, the delay circuit provided between the gate of the drive MOSFET ND and the gates of the transfer MOSFETs PI and PJ can include capacitors that are individually formed, and can also be configured by, for example, an even number of stages of inverters. Furthermore, AND gates AG1 to A
G3 may be included in, for example, the timing generation circuit, and the specific circuit configuration of the unit write amplifiers UWA0 to UWA7 and the unit sense amplifiers USA0 to USA7 may be various embodiments. The logic levels of the start control signal and the internal control signal and the timing conditions thereof in FIG. 7 are not restricted by this embodiment.

In the above description, the case where the invention made by the present inventor is mainly applied to the static type RAM which is the field of application as the background has been described.
The present invention is not limited to this, and can be applied to, for example, a single-chip microcomputer including a static RAM, a gate array integrated circuit, or the like, or a semiconductor memory device that does not adopt the auto power down system.

[0059]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a static RAM or the like that adopts an auto power down system, its sense amplifier includes a latch that is substantially a pair of CMOS inverters cross-coupled, and a drive MOSFET that selectively supplies an operating current to the latch. A pair of transfer MOSs provided between the non-inverting and inverting input / output nodes of the latch and the non-inverting and inverting signal lines of the complementary common data line, respectively.
The transfer MOSFET is configured by an inverter type CMOS latch including an FET and a transfer MOSFET.
The OSFET is turned on and the sense amplifier is turned off immediately after it is turned on, and the sense amplifier is separated from the common data line to enable high-speed operation with a single inverter type CMOS latch, and its output amplitude is It is possible to realize a sense amplifier which has a relatively large amplification factor by being fully swung and which allows a direct current to flow only when a state transition occurs. As a result, the circuit configuration of the sense amplifier itself can be simplified, and these sense amplifiers can be used as an output latch while remaining in the operating state even after the amplification operation of the read signal. As a result, the operating current of the read system circuit can be reduced, the circuit configuration can be simplified, and cost reduction and power consumption reduction of the static RAM or the like adopting the auto power down system can be promoted.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a static RAM to which the present invention is applied.

FIG. 2 is a partial circuit diagram showing an embodiment of a memory array included in the static RAM of FIG.

3 is a partial circuit diagram showing an embodiment of a Y switch included in the static RAM of FIG.

FIG. 4 is a partial block diagram showing an embodiment of a write amplifier and a sense amplifier included in the static RAM of FIG.

5 is a circuit diagram showing an example of a unit write amplifier that constitutes the write amplifier of FIG. 4. FIG.

FIG. 6 is a circuit diagram showing an example of a unit sense amplifier that constitutes the sense amplifier of FIG.

7 is a signal waveform diagram showing an embodiment of a read mode of the static RAM shown in FIG.

[Explanation of symbols]

ARY0 to ARY3 ... Memory array, XD ... X
Address decoder, XB ... X address buffer, Y
S0 to YS3 ... Y switch, YD0 to YD3 ...
Y address decoder, YB ... Y address buffer,
MS ... Mat selection circuit, ZB ... Z address buffer, WA0-WA3 ... Write amplifier, SA0-S
A3 ... Sense amplifier, DIB ... Data input buffer, DOB ... Data output buffer, TG ... Timing generation circuit. MW0B to MWmB ... Main word line, SW0 to S
Wm ... Sub word line, B0 * to Bn * ... Complementary bit line, MC ... Memory cell, SWD0 to SWDm
..Sub-word line drive circuits, BPC0 to BPCn ...
Bit line precharge circuit. CW0 * to CW7 * ... Complementary common data line for writing, CR0 * to CR7 * ... Complementary common data line for reading. UWA0 to UWA7 ... Unit write amplifier, USA0
-USA7 ... Unit sense amplifier, DB0 * -DB7
* ... Data input / output bus. VL: Inverter type C
MOS latch, SAOG ... Sense amplifier output gate. WC1 to WC2 ... Writing circuit. P1-PO ... P-channel MOSFET, N1-N
J ... N-channel MOSFET, G1-G6 ...
Complementary gates, V1 to V5 ... Inverters, AG1 to A
G3 ... AND gate, R1-R3 ...
resistance.

Front page continued (72) Inventor Yoshiaki Umekawa 145 Nakajima, Nanae-cho, Kameda-gun, Hokkaido Hitachi-Hokukai Semiconductor Co., Ltd.

Claims (7)

[Claims] 1. A latch comprising a pair of CMOS inverters cross-coupled to each other, a drive MOSFET for selectively supplying an operating current to the latch, a non-inverting and inverting input / output node of the latch, and complementary common data. A semiconductor memory device, comprising: a sense amplifier including a pair of transfer MOSFETs respectively provided between a non-inversion line and an inversion signal line. 2. The drive MOSFET of the first conductivity type receives a predetermined internal control signal at its gate.
3. The semiconductor memory device according to claim 2, wherein each of the transfer MOSFETs comprises a second conductivity type MOSFET that receives the internal control signal at its gate. 3. The internal control signal is the drive MOSF.
3. The semiconductor memory device according to claim 2, wherein after being supplied to the gate of ET, it is supplied to the gate of said transfer MOSFET via a predetermined delay circuit. 4. The semiconductor memory device employs an auto power-down method, and the sense amplifier is also used as an output latch for holding storage data read from a selected memory cell. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a semiconductor memory device. 5. The memory array is divided into a plurality of pieces in the extension direction of complementary bit lines, and the plurality of complementary common data lines and sense amplifiers are provided corresponding to each of the divided memory arrays. The semiconductor memory device according to claim 1, claim 2, claim 3, or claim 4. 6. Each of the complementary common data lines and a first complementary common data line selectively connected to a designated complementary bit line of a corresponding memory array via a first conductivity type switch MOSFET. , Second conductivity type switch M
2. A second complementary common data line selectively connected to a designated complementary bit line of a corresponding memory array via an OSFET.
The semiconductor memory device according to claim 2, claim 3, claim 4, or claim 5. 7. A memory data write operation to a selected memory cell of the memory array is performed via the corresponding first and second complementary common data lines, and a read operation thereof is performed to a corresponding second common data line. 7. The semiconductor memory device according to claim 6, which is performed via the complementary common data line.