JPH05136293A - Optical semiconductor device - Google Patents
Optical semiconductor deviceInfo
- Publication number
- JPH05136293A JPH05136293A JP3295646A JP29564691A JPH05136293A JP H05136293 A JPH05136293 A JP H05136293A JP 3295646 A JP3295646 A JP 3295646A JP 29564691 A JP29564691 A JP 29564691A JP H05136293 A JPH05136293 A JP H05136293A
- Authority
- JP
- Japan
- Prior art keywords
- optical semiconductor
- semiconductor device
- lead
- specific lead
- die pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Led Device Packages (AREA)
- Light Receiving Elements (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、良好な光学的通路が
確保できた光学的半導体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical semiconductor device in which a good optical path can be secured.
【０００２】[0002]
【従来の技術】先ず、図３及び図４を用いて従来技術の
光学的半導体装置を説明する。図３において符号１は全
体として光学的半導体装置を示す。この光学的半導体装
置１は、図４に示したようなダイパッド部２と、複数の
インナーリード３とアウターリード４からなるリード部
５とから構成されたリードフレーム６の前記ダイパッド
部２に、発光ダイオードのような発光素子やＣＣＤのよ
うな受光素子の光学的半導体素子または周辺回路素子を
含む光学的半導体素子（以下、単に「光学的半導体素
子」と記す）７を銀ペースト等でダイボンディングし、
そしてその光学的半導体素子７のそれぞれの電極を金ワ
イヤ８でそれぞれの電極に対応した前記インナーリード
３に接続し、そしてその全体を透明樹脂でモールドし、
前記複数のアウターリード４を所定の長さに切断、曲げ
加工を施して、透明なパッケージ９で覆った構成になっ
ている。そしてこのような光学的半導体装置１の、例え
ば、電源電極となる第１リード（通常、第１ピンと呼ば
れている）のような特定リード１０を表示するために、
その特定リード１０に対応する前記透明パッケージ９の
表面に、即ち、受光面に凹部１１が設けられている。2. Description of the Related Art First, a conventional optical semiconductor device will be described with reference to FIGS. In FIG. 3, reference numeral 1 generally indicates an optical semiconductor device. This optical semiconductor device 1 emits light to the die pad portion 2 of a lead frame 6 including a die pad portion 2 as shown in FIG. 4 and a lead portion 5 composed of a plurality of inner leads 3 and outer leads 4. An optical semiconductor element such as a light emitting element such as a diode or a light receiving element such as a CCD or an optical semiconductor element including a peripheral circuit element (hereinafter, simply referred to as “optical semiconductor element”) 7 is die-bonded with silver paste or the like. ,
Then, each electrode of the optical semiconductor element 7 is connected to the inner lead 3 corresponding to each electrode with a gold wire 8, and the whole is molded with a transparent resin,
The plurality of outer leads 4 are cut into a predetermined length, bent, and covered with a transparent package 9. In order to display a specific lead 10 of the optical semiconductor device 1 such as the first lead (usually called the first pin) that serves as a power electrode,
A recess 11 is provided on the surface of the transparent package 9 corresponding to the specific lead 10, that is, on the light receiving surface.
【０００３】[0003]
【発明が解決しようとする課題】しかし、このように凹
部１１が受光面に存在していると、この凹部１１によっ
て入射光が屈折または遮断されて、映像信号にフレア等
の好ましくない現象が生じ、このような欠点は光学的半
導体装置１が小型化され、従って、受光面側の面積が狭
くなるにつれ増大するので、受光面側にこのような凹部
１１を形成することは望ましくない。また、このような
表示では、パッケージ９が透明であるため、その凹部１
１を識別しにくいという欠点があった。この発明はこの
ような欠点がない光学的半導体装置を発明したものであ
る。However, when the concave portion 11 is present on the light receiving surface as described above, incident light is refracted or blocked by the concave portion 11 and an undesirable phenomenon such as flare occurs in the video signal. However, such a defect increases as the optical semiconductor device 1 is miniaturized and therefore the area on the light-receiving surface side becomes smaller. Therefore, it is not desirable to form such a recess 11 on the light-receiving surface side. Further, in such a display, since the package 9 is transparent, the recess 1
There was a drawback that it was difficult to identify 1. The present invention is an invention of an optical semiconductor device which does not have such drawbacks.
【０００４】[0004]
【課題を解決するための手段】そのためこの発明は、前
記特定リードを表示する表示部を、その特定リードの近
傍のダイパッド部に形成し、そのダイパッド部に、前記
特定リードに接続される電極が位置するように光学的半
導体素子をダイボンディングして、透明樹脂でパッケー
ジするように構成し、前記の欠点を解決した。Therefore, according to the present invention, a display portion for displaying the specific lead is formed on a die pad portion near the specific lead, and an electrode connected to the specific lead is formed on the die pad portion. The optical semiconductor element was die-bonded so as to be positioned and packaged with a transparent resin to solve the above-mentioned drawback.
【０００５】[0005]
【作用】従って、受光面側に良好な受光路が確保でき、
また特定リードの識別が一瞥して判別することができ
る。[Function] Therefore, a good light receiving path can be secured on the light receiving surface side,
Further, the identification of the specific lead can be determined at a glance.
【０００６】[0006]
【実施例】以下、この発明の実施例を図を用いて説明す
る。図１はこの発明の光学的半導体装置を示す斜視図あ
り、図２はこの発明の光学的半導体装置に用いるリード
フレームの平面図である。なお、図３及び図４の光学的
半導体装置における構成、構造と同一の構成、構造の部
分には同一の符号を付した。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a perspective view showing an optical semiconductor device of the present invention, and FIG. 2 is a plan view of a lead frame used in the optical semiconductor device of the present invention. The same reference numerals are given to the same configurations and structures as those of the optical semiconductor devices of FIGS. 3 and 4.
【０００７】図２に示したこの発明の光学的半導体装置
１Ａに用いるリードフレーム６Ａには、特定リード１０
の近傍のダイパッド部２に表示部２０を設けた。他の構
成は図４に示したリードフレーム６と同様である。この
表示部２０は、図示の例であは突起を形成して表示した
が、切欠き、スリット等を形成し、一瞥して識別できる
構成の表示であれば、形状、構造は問わない。このよう
なリードフレーム６Ａのダイパッド部２に光学的半導体
素子７を、その特定リード１０に接続すべき電極を位置
させて銀ペースト等でダイボンディングし、各電極をそ
れぞれのインナーリード３に金ワイヤ８で接続し、そし
て透明樹脂でモールドし、硬化した後、アウターリード
４を所定の長さに切断、曲げ加工を施すと、この発明の
光学的半導体装置１Ａを得ることができる。The lead frame 6A used in the optical semiconductor device 1A of the present invention shown in FIG.
The display section 20 was provided on the die pad section 2 in the vicinity of. The other structure is the same as that of the lead frame 6 shown in FIG. In the illustrated example, the display section 20 is formed by forming a protrusion, but the display section 20 may be formed in any shape such as a notch, a slit, or the like, and the display and the structure can be identified at a glance. The optical semiconductor element 7 is die-bonded with silver paste or the like on the die pad portion 2 of the lead frame 6A, with the electrode to be connected to the specific lead 10 positioned, and each electrode is attached to the inner lead 3 by a gold wire. After being connected at 8, molded with a transparent resin, and cured, the outer lead 4 is cut into a predetermined length and bent to obtain the optical semiconductor device 1A of the present invention.
【０００８】この表示部２０は他の四隅のいずれかに設
けてもよい。その特定リード１０が光学的半導体装置１
Ａのどのような機能の電極に接続されているかが約束さ
れていれば、このような光学的半導体装置１Ａを電気回
路配線基板に実装するに当たり、誤って実装されること
はない。The display section 20 may be provided at any of the other four corners. The specific lead 10 is the optical semiconductor device 1.
If it is promised what kind of function of A the electrode is connected to, it will not be erroneously mounted when mounting such an optical semiconductor device 1A on an electric circuit wiring board.
【０００９】[0009]
【発明の効果】以上のようにダイパッド部２の特定箇所
に表示部２０を設けたので、透明パッケージ９の受光面
側に従来技術のような凹部１１を設ける必要はなく、従
って、入射光が屈折または遮断されることがない良好な
工学的通路を確保できる。しかも、従来技術に比し特定
リードを一瞥するだけで識別でき、光学的半導体装置を
正確に電気回路配線基板に実装することができる等、数
々の効果が得られる。As described above, since the display portion 20 is provided at a specific portion of the die pad portion 2, it is not necessary to provide the concave portion 11 on the light receiving surface side of the transparent package 9 as in the prior art, and therefore the incident light is A good engineering path can be ensured that is not bent or blocked. Moreover, compared with the prior art, it is possible to identify by just glancing at the specific lead, and the optical semiconductor device can be accurately mounted on the electric circuit wiring board, and various effects are obtained.
【図１】この発明の光学的半導体装置の斜視図である。FIG. 1 is a perspective view of an optical semiconductor device of the present invention.
【図２】この発明の光学的半導体装置に用いるリードフ
レームの平面図である。FIG. 2 is a plan view of a lead frame used in the optical semiconductor device of the present invention.
【図３】従来技術の光学的半導体装置の斜視図である。FIG. 3 is a perspective view of a prior art optical semiconductor device.
【図４】従来技術の光学的半導体装置に用いるリードフ
レームの平面図である。FIG. 4 is a plan view of a lead frame used in a conventional optical semiconductor device.
【符号の説明】 １Ａ 光学的半導体装置 ２ ダイパッド部 ３ インナーリード ４ アウターリード ５ リード部 ６Ａ リードフレーム ７ 光学的半導体素子 ８ 金ワイヤ ９ 透明パッケージ １０ 特定リード ２０ 表示部[Explanation of Codes] 1A Optical semiconductor device 2 Die pad part 3 Inner lead 4 Outer lead 5 Lead part 6A Lead frame 7 Optical semiconductor element 8 Gold wire 9 Transparent package 10 Specific lead 20 Display part
フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 // Ｈ０１Ｌ 23/50 Ｕ 9272−4Ｍ Continuation of front page (51) Int.Cl. 5 Identification number Office reference number FI technical display location // H01L 23/50 U 9272-4M
Claims (1)
ードの近傍のダイパッド部に形成し、該ダイパッド部
に、該表示部の近傍に前記特定リードに接続される電極
が位置するように、光学的半導体素子または周辺回路素
子を含む光学的半導体素子をダイボンディングした後、
透明樹脂で封止したことを特徴とする光学的半導体装
置。1. A display section for displaying a specific lead is formed on a die pad section near the specific lead, and an electrode connected to the specific lead is located in the die pad section near the display section. After die-bonding an optical semiconductor element including an optical semiconductor element or a peripheral circuit element,
An optical semiconductor device characterized by being sealed with a transparent resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3295646A JPH05136293A (en) | 1991-11-12 | 1991-11-12 | Optical semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3295646A JPH05136293A (en) | 1991-11-12 | 1991-11-12 | Optical semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05136293A true JPH05136293A (en) | 1993-06-01 |
Family
ID=17823345
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3295646A Pending JPH05136293A (en) | 1991-11-12 | 1991-11-12 | Optical semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05136293A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012098595A1 (en) * | 2011-01-19 | 2012-07-26 | パナソニック株式会社 | Wiring substrate and semiconductor device using same |
-
1991
- 1991-11-12 JP JP3295646A patent/JPH05136293A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012098595A1 (en) * | 2011-01-19 | 2012-07-26 | パナソニック株式会社 | Wiring substrate and semiconductor device using same |
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