WO2012098595A1 - Wiring substrate and semiconductor device using same - Google Patents

Wiring substrate and semiconductor device using same Download PDF

Info

Publication number
WO2012098595A1
WO2012098595A1 PCT/JP2011/004314 JP2011004314W WO2012098595A1 WO 2012098595 A1 WO2012098595 A1 WO 2012098595A1 JP 2011004314 W JP2011004314 W JP 2011004314W WO 2012098595 A1 WO2012098595 A1 WO 2012098595A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor chip
wiring board
die pad
characteristic shape
bonding pads
Prior art date
Application number
PCT/JP2011/004314
Other languages
French (fr)
Japanese (ja)
Inventor
新井　良之
英樹 迫田
Original Assignee
パナソニック株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by パナソニック株式会社 filed Critical パナソニック株式会社
Publication of WO2012098595A1 publication Critical patent/WO2012098595A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/02002—Arrangements for conducting electric current to or from the device in operations
    • H01L31/02005—Arrangements for conducting electric current to or from the device in operations for device characterised by at least one potential jump barrier or surface barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/5442—Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/83132—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/1016—Shape being a cuboid
    • H01L2924/10161—Shape being a cuboid with a rectangular active surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0266—Marks, test patterns or identification means
    • H05K1/0269—Marks, test patterns or identification means for visual or optical inspection
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H05K3/305—Affixing by adhesive

Abstract

This wiring substrate is characterized by being provided with a substrate main body (12o) on which bonding pads (12b) are arranged and a rectangular die pad (12a) formed on the substrate main body (12o) and by the die pad (12a) being provided with special shaped parts (P1, P2, P3) formed so as to protrude on two sides opposite to each other on at least two corners in a direction (Y) in which the bonding pads (12b) are not arranged.

Description

配線基板およびそれを用いた半導体装置Wiring substrate and semiconductor device using the same
　本発明は、配線基板上に接着剤を介して半導体チップを固着して形成する半導体装置用の配線基板に関する。 The present invention relates to a wiring board for a semiconductor device in which a semiconductor chip is fixedly formed on a wiring board via an adhesive.
　特許文献１に代表されるような光ピックアップ受光素子においては、半導体チップの電極が金線を介して配線基板の表面の電極に接続され、配線基板の表裏をスルーホールが貫通して、基板の表と裏との電極が導通することにより、配線基板の裏面に電極を自由に配置できる。半導体チップは配線基板のダイパッドにＡｇペーストで接着され、半導体チップの表側は封止樹脂により封止されている。 In an optical pickup light receiving element represented by Patent Document 1, an electrode of a semiconductor chip is connected to an electrode on the surface of a wiring board via a gold wire, and a through hole penetrates the front and back of the wiring board. When the front and back electrodes are electrically connected, the electrodes can be freely arranged on the back surface of the wiring board. The semiconductor chip is bonded to the die pad of the wiring board with Ag paste, and the front side of the semiconductor chip is sealed with a sealing resin.
　このような半導体装置の製造において、半導体チップは配線基板の所定の位置に正確に搭載されなければならない。所定の位置からずれて搭載されると、半導体チップ上のボンディングパッドと配線基板上のボンディングパッドとをワイヤーボンドする際に、ボンディングパッド位置の認識エラーが発生するからである。また、半導体チップが受光部を備えているので、搭載ズレが発生すると、レーザー光の入射が、受光部から外れて機能しなくなるため、特に半導体チップの搭載ズレに対する要求が厳しい。 In manufacturing such a semiconductor device, the semiconductor chip must be accurately mounted at a predetermined position on the wiring board. This is because if the mounting is shifted from a predetermined position, a recognition error of the bonding pad position occurs when wire bonding is performed between the bonding pad on the semiconductor chip and the bonding pad on the wiring board. In addition, since the semiconductor chip includes the light receiving portion, if mounting deviation occurs, the incidence of laser light is removed from the light receiving portion and does not function. Therefore, the demand for mounting deviation of the semiconductor chip is particularly severe.
　半導体チップが配線基板の所定の位置に正確に搭載されているかどうかを判定するためには、配線基板上に形成された配線パターンと半導体チップとの相対的な位置関係を測定する。その位置関係は、一般的にはＸ，Ｙ方向の位置とθ方向の３つのパラメータより記述される。配線基板上のパターンにおいてこれらＸ，Ｙ，θの基準となる位置を見出すには、配線基板上に基準になる特徴パターンが必要である。通常、その特徴パターンとして適しているとされているものは、配線基板に搭載される半導体チップの外形に沿って設計されたダイパッドのパターンである。 In order to determine whether or not the semiconductor chip is accurately mounted at a predetermined position on the wiring board, the relative positional relationship between the wiring pattern formed on the wiring board and the semiconductor chip is measured. The positional relationship is generally described by three parameters in the X and Y directions and the θ direction. In order to find a position serving as a reference for these X, Y, and θ in a pattern on the wiring board, a characteristic pattern serving as a reference is required on the wiring board. Usually, what is suitable as the characteristic pattern is a die pad pattern designed along the outline of a semiconductor chip mounted on a wiring board.
　図８（ａ）～図８（ｃ）は、配線基板２上のダイパッド２ａに接着剤３を介して半導体チップ１を固着して形成した従来の半導体装置を示す。半導体チップ１のボンディングパッド１ａと配線基板２のボンディングパッド２ｂの間は、ワイヤ４で接続されている。配線基板２のボンディングパッド２ｂに接続されているランド２ｃはスルーホール２ｄを介して外部端子２ｅに接続されている。５は封止樹脂である。 8A to 8C show a conventional semiconductor device formed by fixing the semiconductor chip 1 to the die pad 2a on the wiring substrate 2 with the adhesive 3 interposed therebetween. The bonding pads 1 a of the semiconductor chip 1 and the bonding pads 2 b of the wiring board 2 are connected by wires 4. The land 2c connected to the bonding pad 2b of the wiring board 2 is connected to the external terminal 2e through the through hole 2d. 5 is a sealing resin.
　図９（ａ）はダイパッド２ａに接着剤３を塗布して半導体チップ１を載せる前の状態、図９（ｂ）は半導体チップ１を載せた状態を示している。 FIG. 9A shows a state before the semiconductor chip 1 is placed after the adhesive 3 is applied to the die pad 2a, and FIG. 9B shows a state where the semiconductor chip 1 is placed.
特開２００１－２３０４２７号公報Japanese Patent Laid-Open No. 2001-230427
　しかしながら、このようにして得られた半導体装置には以下の課題がある。 However, the semiconductor device obtained in this way has the following problems.
　配線基板上の配線パターンには、ワイヤ４との接続性を確保するために金属のめっきが施されている。めっきと配線基板を封止する封止樹脂との接着力は著しく低い。配線パターンと封止樹脂５との界面にて接着力が低いと、その半導体装置をマザー基板に搭載する際のリフローの熱によってめっきと封止樹脂５との間で界面剥離が発生し、半導体装置の信頼性を劣化させる。従って、配線基板２上の配線パターンは、その面積を極力小さくするか、あるいはその表面をソルダーレジストで被覆して、封止樹脂５との接着力低下を極力抑えるように設計する。当然、ダイパッド２ａもその対象である。 The wiring pattern on the wiring board is plated with metal to ensure connectivity with the wires 4. The adhesive force between the plating and the sealing resin for sealing the wiring board is extremely low. If the adhesive strength is low at the interface between the wiring pattern and the sealing resin 5, the interface peeling occurs between the plating and the sealing resin 5 due to the heat of reflow when the semiconductor device is mounted on the mother substrate. Deteriorating device reliability. Therefore, the wiring pattern on the wiring board 2 is designed to minimize the area thereof or to cover the surface with a solder resist so as to suppress the decrease in the adhesive strength with the sealing resin 5 as much as possible. Of course, the die pad 2a is also the object.
　半導体装置の信頼性を向上させるためにダイパッド２ａの面積を小さくすると、半導体チップ１とダイパッド２ａとを接合する接着剤３のはみ出しが、図９（ｂ）に符号Ａで示すようにダイパッド２ａの外周部に達し、半導体チップ１の搭載位置の精度の確認に必要な、ダイパッド２ａのパターンの外周部の検出が正確にできない。 When the area of the die pad 2a is reduced in order to improve the reliability of the semiconductor device, the protrusion of the adhesive 3 that joins the semiconductor chip 1 and the die pad 2a is caused by the die pad 2a as shown by symbol A in FIG. The outer periphery of the pattern of the die pad 2a necessary for confirming the accuracy of the mounting position of the semiconductor chip 1 cannot be detected accurately.
　また、ソルダーレジストでダイパッド２ａを被覆しても、ソルダーレジストは着色されているため、配線パターンの外周部の検出ができない。 Also, even if the die pad 2a is covered with a solder resist, the outer periphery of the wiring pattern cannot be detected because the solder resist is colored.
　本発明は上記の課題を解決するためになされたもので、配線基板に対する半導体チップの搭載精度を確保しつつ、信頼性の劣化を引き起こさない半導体装置用の配線基板を提供することを目的とする。 The present invention has been made to solve the above problems, and an object of the present invention is to provide a wiring board for a semiconductor device that does not cause deterioration in reliability while ensuring mounting accuracy of a semiconductor chip on the wiring board. .
　本発明の配線基板は、ボンディングパッドが配列された基板本体と、前記基板本体上に形成された矩形状のダイパッドとを備え、前記ダイパッドは、少なくとも２箇所のコーナーにおいて前記ボンディングパッドが配列されていない方向に向かって対向する二辺を突出させて形成した特徴形状部を備えることを特徴とする。 The wiring board of the present invention includes a substrate body on which bonding pads are arranged, and a rectangular die pad formed on the substrate body, and the bonding pads are arranged at at least two corners. It is characterized by comprising a characteristic shape part formed by projecting two sides facing each other in a non-direction.
　また、本発明の配線基板は、ボンディングパッドが配列された基板本体と、前記基板本体上に形成された矩形状のダイパッドと、前記ダイパッドとは分離して前記基板本体上に形成された導体層の特徴形状部を備えることを特徴とする。 The wiring board according to the present invention includes a substrate body on which bonding pads are arranged, a rectangular die pad formed on the substrate body, and a conductor layer formed on the substrate body separately from the die pad. The characteristic shape part is provided.
　本発明によれば、ダイパッドの少なくとも２箇所のコーナーにおいてボンディングパッドが配列されていない方向に向かって対向する二辺を突出させて形成した特徴形状部を設ける、または、ダイパッドから分離して特徴形状部を設けることで、半導体チップの搭載精度の向上と高信頼性化とを両立した半導体装置を実現できる。 According to the present invention, at least two corners of the die pad are provided with a characteristic shape portion formed by projecting two sides facing each other in the direction in which the bonding pads are not arranged, or separated from the die pad. By providing the portion, it is possible to realize a semiconductor device that achieves both improved mounting accuracy of the semiconductor chip and higher reliability.
（ａ）本発明の実施の形態１にかかる半導体装置１０の平面模式図、（ｂ）　　半導体装置１０の断面図、（ｃ）半導体装置１０の底面図(A) The plane schematic diagram of the semiconductor device 10 concerning Embodiment 1 of this invention, (b) Sectional drawing of the semiconductor device 10, (c) Bottom view of the semiconductor device 10 （ａ）ダイパッド部１２ａに接着剤１３を塗布し、半導体チップ１１を搭載　　する前の平面拡大図、（ｂ）半導体チップ１１を搭載して、搭載位置ズレが発生した　　場合の平面模式図、（ｃ）搭載した半導体チップ１１とはみ出した接着剤１３の平面　　模式図とその要部拡大図(A) An enlarged plan view before the semiconductor chip 11 is mounted by applying the adhesive 13 to the die pad portion 12a, (b) a schematic plan view when the mounting position shift occurs when the semiconductor chip 11 is mounted, ( c) A plan view of the adhesive 13 protruding from the mounted semiconductor chip 11 and a schematic enlarged view of the main part thereof. （ａ）～（ｄ）それぞれ本実施の形態１の応用例を示す平面模式図(A) to (d) are schematic plan views showing application examples of the first embodiment. （ａ）本発明の実施の形態２にかかる半導体装置２０の平面模式図、（ｂ）　　ダイパッド部１２ａに接着剤１３を塗布し、半導体チップ１１を搭載する前の平面拡　　大図、（ｃ）半導体チップ１１を搭載して、搭載位置ズレが発生した場合の平面模式　　図(A) Schematic plan view of the semiconductor device 20 according to the second embodiment of the present invention, (b) An enlarged plan view before the semiconductor chip 11 is mounted by applying the adhesive 13 to the die pad portion 12a, (c) Schematic plan view when semiconductor chip 11 is mounted and mounting position shift occurs 搭載した半導体チップ１１とはみ出した接着剤１３の平面模式図とその要部　　拡大図Schematic plan view of the adhesive 13 protruding from the mounted semiconductor chip 11 and its main part enlarged view （ａ）～（ｄ）それぞれ本実施の形態２の応用例を示す平面模式図(A) to (d) are schematic plan views showing application examples of the second embodiment. （ａ）（ｂ）それぞれ本実施の形態３の半導体装置４０，５０の平面模式図(A) (b) The plane schematic diagram of the semiconductor devices 40 and 50 of this Embodiment 3, respectively. （ａ）従来の半導体装置の平面模式図、（ｂ）半導体装置の断面図、（ｃ）　　半導体装置の底面図(A) A schematic plan view of a conventional semiconductor device, (b) a sectional view of the semiconductor device, and (c) a bottom view of the semiconductor device. （ａ）ダイパッド部２ａに接着剤３を塗布し、半導体チップ１を搭載する　　前の平面拡大図、（ｂ）搭載した半導体チップ１に搭載位置ズレが発生した場合の平　　面模式図(A) The adhesive 3 is applied to the die pad portion 2a and the semiconductor chip 1 is mounted. Front enlarged plan view, (b) A schematic plan view when a mounting position shift occurs in the mounted semiconductor chip 1.
　以下、本発明の各実施の形態を図１～図７に基づいて説明する。 Hereinafter, embodiments of the present invention will be described with reference to FIGS.
　　（実施の形態１）
　図１（ａ）は、本発明の実施の形態１にかかる半導体装置１０をその上方から見た状態を示す。図１（ｂ）は断面図、図１（ｃ）は底面図である。 (Embodiment 1)
FIG. 1A shows a state in which the semiconductor device 10 according to the first embodiment of the present invention is viewed from above. 1B is a cross-sectional view, and FIG. 1C is a bottom view.
　外周形状が矩形状の配線基板１２は、基板本体１２ｏの上面にダイパッド１２ａと、ボンディングパッド１２ｂならびにボンディングパッド１２ｂに配線パターンで接続されたランド１２ｃなどからなる配線パターンを設け、基板本体１２ｏの下面に外部端子１２ｅが設けられている。ランド１２ｃと外部端子１２ｅは、図１（ｂ）と図１（ｃ）に示すように、基板本体１２ｏの内部に形成されたスルーホール１２ｄで接続されている。 The wiring substrate 12 having a rectangular outer peripheral shape is provided with a wiring pattern including a die pad 12a, a bonding pad 12b, and a land 12c connected to the bonding pad 12b by a wiring pattern on the upper surface of the substrate body 12o. Are provided with external terminals 12e. As shown in FIGS. 1B and 1C, the land 12c and the external terminal 12e are connected by a through hole 12d formed in the substrate body 12o.
　半導体チップ１１は、配線基板１２のダイパッド１２ａに接着剤１３を介して搭載されている。半導体チップ１１のボンディングパッド１１ａと、配線基板１２のボンディングパッド１２ｂとの間がワイヤ１４によって接続されている。この半導体装置１０は、基板本体１２ｏの上面と、半導体チップ１１、ワイヤ１４とともに封止樹脂１５によって封止して構成されている。 The semiconductor chip 11 is mounted on the die pad 12a of the wiring board 12 via an adhesive 13. A wire 14 connects the bonding pad 11 a of the semiconductor chip 11 and the bonding pad 12 b of the wiring substrate 12. The semiconductor device 10 is configured by being sealed with a sealing resin 15 together with the upper surface of the substrate body 12 o, the semiconductor chip 11, and the wires 14.
　この半導体装置１０は、外部電極１２ｅが、ここで図示していないマザー基板の電極と接合されることにより、半導体チップ１１の電気信号を外部に取り出すことができる。 This semiconductor device 10 can take out an electrical signal of the semiconductor chip 11 by joining the external electrode 12e to an electrode of a mother substrate (not shown).
　ダイパッド１２ａの形状は、平面形状が四辺形の半導体チップ１１と同じか僅かに大きな四辺形である。また、ダイパッド１２ａに搭載される半導体チップ１１の複数のボンディングパッド１１ａに沿って、複数のボンディングパッド１２ｂがダイパッド１２ａの対向する二辺に平行に基板本体１２ｏの上面に設けられている。 The shape of the die pad 12a is a quadrangle that is the same as or slightly larger than the semiconductor chip 11 whose planar shape is a quadrangle. Further, along the plurality of bonding pads 11a of the semiconductor chip 11 mounted on the die pad 12a, a plurality of bonding pads 12b are provided on the upper surface of the substrate body 12o in parallel with two opposite sides of the die pad 12a.
　ここで、本実施の形態１においてはダイパッド１２ａのコーナー部の形状に特徴がある。 Here, the first embodiment is characterized by the shape of the corner portion of the die pad 12a.
　ダイパッド１２ａの外周部は、おおまかには半導体チップ１１の四辺形の形状に沿っており、搭載する半導体チップ１１のボンディングパッド１１ａが配置されていない二辺に平行な辺、すなわち、ボンディングパッド１２ｂに対向していない短辺のコーナー部に、ここでは、ダイパッド１２ａの四隅のうち３つの隅に、ボンディングパッド１２ｂに対向している辺をそのまま延伸した方向（Ｙ方向）に突出させた規定の形状である矩形の特徴形状部Ｐ１，Ｐ２，Ｐ３が形成されている。 The outer peripheral portion of the die pad 12a is generally along the quadrilateral shape of the semiconductor chip 11, and is parallel to the two sides where the bonding pad 11a of the semiconductor chip 11 to be mounted is not disposed, that is, the bonding pad 12b. A specified shape in which the side facing the bonding pad 12b is projected as it is in the extending direction (Y direction) at the corners of the short sides that are not facing, here, at the three corners of the four corners of the die pad 12a The rectangular characteristic shape portions P1, P2, and P3 are formed.
　基板本体１２ｏのダイパッド１２ａ、特徴形状の特徴形状部Ｐ１，Ｐ２，Ｐ３、ボンディングパッド１２ｂを除いた表面が、絶縁体のソルダーレジスト（図示せず）によって覆われている。 The surface of the substrate body 12o excluding the die pad 12a, the characteristic shape portions P1, P2, P3, and the bonding pad 12b is covered with an insulating solder resist (not shown).
　この構成によると、以下のように半導体装置１０はその信頼性を劣化させること無く、半導体チップ１１をダイパッド１２ａに搭載する精度が向上する。 According to this configuration, the accuracy of mounting the semiconductor chip 11 on the die pad 12a is improved without degrading the reliability of the semiconductor device 10 as described below.
　図２（ａ）は、ダイパッド部１２ａに接着剤１３を塗布し、半導体チップ１１を搭載する前の状態を示している。ここで、接着剤１３は半導体チップ１１をダイパッド１２ａに強固に接合するためにダイパッド１２ａの面積の全面に濡れ広がっている。 FIG. 2A shows a state before the adhesive 13 is applied to the die pad portion 12a and the semiconductor chip 11 is mounted. Here, the adhesive 13 wets and spreads over the entire area of the die pad 12a in order to firmly bond the semiconductor chip 11 to the die pad 12a.
　半導体チップ１１を高精度に搭載する際には、ダイパッド１２ａの位置を正確に認識しなければならない。従来のダイパッドの形状（図９（ａ）に示す）においては、ダイパッドの外周部を認識しようとしても接着剤３の影響で正確な認識ができず、半導体チップ１１の搭載位置がばらつく。しかし、本実施の形態１に示すようにダイパッド１２ａの３隅に特徴形状の特徴形状部Ｐ１，Ｐ２，Ｐ３があれば、その３箇所からダイパッド１２ａのＸ軸，Ｙ軸を検出することで、接着剤１３の影響を受けずに半導体チップ１１の搭載位置を正確に算出できる。従って、半導体チップ１１の搭載位置の精度を高めることができる。 When the semiconductor chip 11 is mounted with high accuracy, the position of the die pad 12a must be accurately recognized. In the conventional die pad shape (shown in FIG. 9A), even if the outer periphery of the die pad is to be recognized, it cannot be accurately recognized due to the influence of the adhesive 3, and the mounting position of the semiconductor chip 11 varies. However, as shown in the first embodiment, if there are characteristic shape portions P1, P2, P3 at the three corners of the die pad 12a, by detecting the X-axis and Y-axis of the die pad 12a from the three locations, The mounting position of the semiconductor chip 11 can be accurately calculated without being affected by the adhesive 13. Therefore, the accuracy of the mounting position of the semiconductor chip 11 can be increased.
　ここで特徴形状部Ｐ１，Ｐ２，Ｐ３をダイパッド１２ａの短辺の隅部に配置する構成には以下の利点がある。 Here, the configuration in which the characteristic shape portions P1, P2, P3 are arranged at the corners of the short sides of the die pad 12a has the following advantages.
　接着剤１３は半導体チップ１１とダイパッド１２ａとを接着するために塗布されるため、ダイパッド１２ａの中心部において量が多く、ダイパッド１２ａの外周部に向かうほどその量が少なくなる。はみ出し量が最も少なくなるのが隅部であり、その隅部に特徴形状部を配置することで、接着剤の影響を最小限にすることができる。 Since the adhesive 13 is applied to bond the semiconductor chip 11 and the die pad 12a, the amount of the adhesive 13 is large at the center of the die pad 12a, and the amount of the adhesive 13 decreases toward the outer periphery of the die pad 12a. It is the corner that has the smallest amount of protrusion, and the influence of the adhesive can be minimized by disposing the characteristic shape portion in the corner.
　反対に、ダイパッド１２ａの隅部以外、例えばダイパッド１２ａのボンディングパッド１１ａが配置された辺に沿った長辺に特徴形状部Ｐ１，Ｐ２，Ｐ３を配置した場合、接着剤１３のはみ出しの影響によりその位置の正確な検出ができない虞がある。 On the other hand, when the characteristic shape portions P1, P2, P3 are arranged on the long side along the side where the bonding pad 11a of the die pad 12a is arranged, for example, other than the corner portion of the die pad 12a, There is a possibility that the position cannot be accurately detected.
　さらに、ダイパッド１２ａの３隅の特徴形状部Ｐ１，Ｐ２，Ｐ３が、ボンディングパッド１２ｂの配置されていないＹ軸方向に突起している構成には、以下の利点がある。 Furthermore, the configuration in which the characteristic shape portions P1, P2, P3 at the three corners of the die pad 12a protrude in the Y-axis direction where the bonding pad 12b is not arranged has the following advantages.
　特徴形状部Ｐ１，Ｐ２，Ｐ３がＹ軸方向に突起していることにより、たとえその特徴形状部において封止樹脂との界面剥離を生じても、その剥離がボンディングパッド１２ｂの方向に延伸する虞は小さく、ワイヤ１４の断線という致命的な不良を防止することができる。また、その方向には、ボンディングパッド１２ｂが配置されておらず配線パターンの密度が低いため、ボンディングパッド１２ｂが配置されている方向に突起させるよりも配線基板１２の面積を低減することができ、半導体装置の小型化に寄与する。 Since the characteristic shape portions P1, P2, and P3 protrude in the Y-axis direction, even if interface separation with the sealing resin occurs in the characteristic shape portion, the separation may extend in the direction of the bonding pad 12b. Is small and can prevent a fatal failure such as disconnection of the wire 14. In addition, since the bonding pad 12b is not disposed in that direction and the density of the wiring pattern is low, the area of the wiring substrate 12 can be reduced as compared with the protrusion in the direction in which the bonding pad 12b is disposed. Contributes to miniaturization of semiconductor devices.
　図２（ｂ）に示しているのは、図２（ａ）のように塗布した接着剤１３を介してダイパッド１２ａの上に半導体チップ１１を搭載して、搭載位置ズレが発生した場合の平面模式図である。ここで、ダイパッド１２ａの３箇所の特徴形状である特徴形状部Ｐ１，Ｐ２，Ｐ３によりダイパッド１２ａのＸ軸とＹ軸が検出され、これに対して半導体チップ１１の外形、もしくは回路等の特徴パターンを認識することによりその搭載位置を確認することができる。従って、たとえ搭載位置ズレが発生したとしても、その後の検査における測定作業により不良品を排除できる。 FIG. 2B shows a plane when the semiconductor chip 11 is mounted on the die pad 12a via the adhesive 13 applied as shown in FIG. 2A and mounting position deviation occurs. It is a schematic diagram. Here, the X-axis and Y-axis of the die pad 12a are detected by the characteristic shape portions P1, P2, P3 which are the three characteristic shapes of the die pad 12a. Can be confirmed by recognizing. Therefore, even if the mounting position shift occurs, defective products can be eliminated by the measurement work in the subsequent inspection.
　従来技術のように、接着剤１３の影響を排するためにダイパッド１２ａの面積を四辺形の形状のまま増大させると、ダイパッド１２ａとその封止樹脂１５との界面において剥離が発生する虞があった。これに対して本実施の形態では、特徴形状部Ｐ１，Ｐ２，Ｐ３の規定の形状を、認識が可能となる必要最小限の面積にとどめる事により、半導体装置１０をマザー基板に実装する際の熱によるダイパッド１２ａとその封止樹脂１５との界面での剥離の発生を抑えることができる。つまり、半導体チップ１１の搭載位置の精度向上と高信頼性とを両立させることができる。 If the area of the die pad 12a is increased in the shape of a quadrilateral in order to eliminate the influence of the adhesive 13 as in the prior art, peeling may occur at the interface between the die pad 12a and the sealing resin 15 thereof. It was. On the other hand, in the present embodiment, by restricting the prescribed shapes of the characteristic shape portions P1, P2, and P3 to a necessary minimum area that can be recognized, the semiconductor device 10 is mounted on the mother board. The occurrence of peeling at the interface between the die pad 12a and the sealing resin 15 due to heat can be suppressed. That is, it is possible to achieve both improvement in accuracy of mounting position of the semiconductor chip 11 and high reliability.
　具体的な大きさの一例を以下に述べる。 An example of specific size is described below.
　半導体チップ１１の平面寸法は０．５ｍｍ×０．５ｍｍから２ｍｍ×２ｍｍまでの間とし、それを搭載するダイパッド１２ａのサイズは、それに対応する半導体チップ１１の各辺の寸法に対して０μｍから２００μｍまでの範囲で半導体チップ１１の寸法より大きいものとする。半導体チップ１１の厚みとして５０μｍから２００μｍまでの間とし、接着剤１３の半導体チップ１１の側面への這い上がりは、それが半導体チップ１１の表面にまで達するとショートが起きるため、半導体チップ１１の厚みの２／３以下、すなわち３３μｍから１３３μｍまでとする。接着剤１３の半導体チップ１１の外周からのはみ出し寸法は、上記の這い上がりの寸法の１／２から２／２の間なので１６μｍから１３３μｍとなる。従ってダイパッド１２ａの特徴形状部Ｐ１，Ｐ２，Ｐ３の寸法としては、ダイパッド１２ａの中心に半導体チップ１１が搭載されたとして、その半導体チップ１１の外周部から１３３μｍ以上突起していれば、接着剤１３のはみ出しに影響されることが無いため好ましい。搭載した半導体チップ１１とはみ出した接着剤１３の平面模式図とその要部拡大図を図２（ｃ）に示す。 The planar dimension of the semiconductor chip 11 is between 0.5 mm × 0.5 mm and 2 mm × 2 mm, and the size of the die pad 12a on which the semiconductor chip 11 is mounted is 0 μm to 200 μm with respect to the dimension of each side of the semiconductor chip 11 corresponding thereto. It is assumed that it is larger than the size of the semiconductor chip 11 in the above range. The thickness of the semiconductor chip 11 is between 50 μm and 200 μm, and the scooping of the adhesive 13 to the side surface of the semiconductor chip 11 causes a short circuit when it reaches the surface of the semiconductor chip 11. 2/3 or less, that is, 33 μm to 133 μm. The protruding dimension of the adhesive 13 from the outer periphery of the semiconductor chip 11 is between 16 μm and 133 μm because it is between 1/2 and 2/2 of the above-mentioned rising dimension. Accordingly, the dimensions of the characteristic shape portions P1, P2, and P3 of the die pad 12a are as follows. Assuming that the semiconductor chip 11 is mounted at the center of the die pad 12a, and protrudes from the outer periphery of the semiconductor chip 11 by 133 μm or more, the adhesive 13 This is preferable because it is not affected by the protrusion of the film. FIG. 2C shows a schematic plan view of the adhesive 13 protruding from the mounted semiconductor chip 11 and an enlarged view of the main part thereof.
　次に、半導体装置１０の各構成物に使用する材料について説明する。 Next, materials used for each component of the semiconductor device 10 will be described.
　半導体チップ１１としてはＳｉを想定しているが、その機能に応じてＳｉＣ，ＳｉＧｅ，ＧａＡｓ，ＧａＮ等の化合物であってもよい。配線基板１２は一般的に基板本体１２ｏと導体部とよりなり、基板本体１２ｏとしてはガラス・エポキシ，ＢＴレジン，ポリイミドテープ等に代表される有機材料とアルミナセラミックス基板に代表される無機材料に二分される。導体としては有機の基板本体１２ｏに対してはＣｕ、無機の基板本体１２ｏに対してはＷが代表的である。 The semiconductor chip 11 is assumed to be Si, but may be a compound such as SiC, SiGe, GaAs, or GaN depending on its function. The wiring board 12 is generally composed of a board body 12o and a conductor. The board body 12o is divided into an organic material typified by glass / epoxy, BT resin, polyimide tape and the like and an inorganic material typified by an alumina ceramic substrate. Is done. The conductor is typically Cu for the organic substrate body 12o and W for the inorganic substrate body 12o.
　本実施の形態１での基板本体１２ｏとしては有機材料を想定しているが、無機材料の適用を除外しているわけではない。Ｃｕ箔の表面にはＣｕの酸化・汚染防止のためのＮｉめっき、更にワイヤ１４との接続性を確保するためのＡｕめっきやＡｇめっきの処理を施すのが一般的である。接着剤１３としてはエポキシ等の樹脂にＡｇフィラーを分散させた導電性のＡｇペーストが一般的であるが、絶縁性のペースト材も一般に使用されており、これを接着剤１３として使用することもできる。 Although an organic material is assumed as the substrate body 12o in the first embodiment, the application of an inorganic material is not excluded. In general, the surface of the Cu foil is subjected to Ni plating for preventing oxidation and contamination of Cu, and further, Au plating or Ag plating for ensuring connectivity with the wire 14. As the adhesive 13, a conductive Ag paste in which an Ag filler is dispersed in a resin such as an epoxy is generally used, but an insulating paste material is also generally used, and this may be used as the adhesive 13. it can.
　ワイヤ１４としてはＡｕ合金が一般的であるが、Ａｌ，Ｃｕ合金も適用できる。封止樹脂１５としては通常はエポキシ樹脂が使用されるが、ビフェニル樹脂，シリコーン樹脂等の他の樹脂を使用することもできる。 As the wire 14, an Au alloy is generally used, but Al and Cu alloys can also be applied. An epoxy resin is usually used as the sealing resin 15, but other resins such as a biphenyl resin and a silicone resin can also be used.
　封止樹脂１５は、通常は光による半導体チップ１１の誤動作を防止するため黒色に着色されているのが一般的であるが、受光素子等の光によって機能する半導体チップが搭載されている場合には光を透過する樹脂が使用される。 The sealing resin 15 is generally colored black in order to prevent malfunction of the semiconductor chip 11 due to light, but when a semiconductor chip that functions by light such as a light receiving element is mounted. A resin that transmits light is used.
　受光素子の用途としては、光の照度センサー、リモートコントロール機器用の受光センサー、光ディスクドライブのピックアップ用の受光ＩＣ等が挙げられる。特に受光ＩＣにおいては、光ディスクの信号を読み取るレーザー光を正確に受光しなければならないため、その半導体装置１０において半導体チップ１１の搭載位置に高い精度を要求されており、本発明の有用性は高い。 Applications of the light receiving element include a light illuminance sensor, a light receiving sensor for a remote control device, a light receiving IC for a pickup of an optical disk drive, and the like. In particular, in a light receiving IC, a laser beam for reading a signal on an optical disk must be accurately received. Therefore, a high accuracy is required for the mounting position of the semiconductor chip 11 in the semiconductor device 10, and the usefulness of the present invention is high. .
　本実施の形態１の応用例を、図３（ａ）～図３（ｄ）に示す。 An application example of the first embodiment is shown in FIGS. 3 (a) to 3 (d).
　図１に示した特徴形状部Ｐ１，Ｐ２，Ｐ３は、ダイパッド１２ａの３隅に配置されているが、図３（ａ）に示すようにダイパッド１２ａの対角の２箇所の特徴形状部Ｐ１，Ｐ３であっても構わない。対角の２箇所の特徴形状部Ｐ１，Ｐ３を認識することでダイパッド１２ａのＸ軸，Ｙ軸を算出できるからである。 The characteristic shape portions P1, P2, and P3 shown in FIG. 1 are arranged at the three corners of the die pad 12a. However, as shown in FIG. P3 may also be used. This is because the X-axis and Y-axis of the die pad 12a can be calculated by recognizing the two feature shapes P1 and P3 on the diagonal.
　また、図３（ｂ）に示すようにダイパッド１２ａの４隅に設けても構わない。４箇所の特徴形状部Ｐ１，Ｐ２，Ｐ３，Ｐ４をそれぞれ認識し、Ｘ軸，Ｙ軸を算出すれば、それだけ半導体チップ１１の搭載精度は向上する。但し、認識に要する時間は追加した特徴形状部Ｐ４を認識する時間の分だけ増えるため、生産効率は低下する。 Also, as shown in FIG. 3 (b), it may be provided at the four corners of the die pad 12a. If the four feature shapes P1, P2, P3, and P4 are recognized and the X axis and the Y axis are calculated, the mounting accuracy of the semiconductor chip 11 is improved accordingly. However, since the time required for recognition increases by the time for recognizing the added feature shape portion P4, the production efficiency decreases.
　図３（ｃ）では、図３（ａ）と比べて配線パターンに引き出し線１２ｆが追加されている点が異なっている。この引き出し線１２ｆは、ダイパッド１２ａ，ボンディングパッド１２ｂならびにランド１２ｃなどにめっきする場合に使用される。配線基板１２の導体には前記した理由でめっきが施されるのが一般的であり、そのめっきの手法としては大きく電解めっきと無電解めっきとに分けられる。電解めっきの場合は導通が必要なので、配線基板１２上の全ての導体部分には、半導体装置１０の組立に必要な箇所の他に、通電のための引き出し線を設ける必要がある。 FIG. 3C is different from FIG. 3A in that a lead line 12f is added to the wiring pattern. The lead wire 12f is used when plating the die pad 12a, the bonding pad 12b, the land 12c, and the like. The conductors of the wiring board 12 are generally plated for the reasons described above, and the plating methods are largely divided into electrolytic plating and electroless plating. In the case of electrolytic plating, since conduction is necessary, it is necessary to provide a lead-out line for energization in addition to the portions necessary for assembling the semiconductor device 10 in all the conductor portions on the wiring board 12.
　この図３（ｃ）では、ダイパッド１２ａに対して設けた引き出し線１２ｆを、ダイパッド１２ａの１つのコーナーに設けているが、この位置に限るものでない。また、半導体チップ１１の機能によっては、グランドなどの基準電位のように電位を同じくするボンディングパッド１２ａを吊リードで接続しても良い。電解めっきは一般的にめっきの組織が緻密で品質が高く、かつコストも低いため有用である。ただし、引き出し線１２ｆに要する面積の分、導体のパターン配置の自由度は減り、微細な導体パターンの必要な配線基板には不向きである。その場合には引き出し線１２ｆの不要な無電解めっきが適用される。 In FIG. 3C, the lead-out line 12f provided for the die pad 12a is provided at one corner of the die pad 12a. However, the present invention is not limited to this position. Further, depending on the function of the semiconductor chip 11, bonding pads 12a having the same potential, such as a reference potential such as a ground, may be connected by a suspended lead. Electroplating is generally useful because the plating structure is dense, high in quality, and low in cost. However, the degree of freedom of the pattern arrangement of the conductor is reduced by the area required for the lead-out line 12f, and is not suitable for a wiring board that requires a fine conductor pattern. In that case, unnecessary electroless plating of the lead wire 12f is applied.
　なお、これまでの説明では、ダイパッド１２ａの特徴形状部Ｐ１～Ｐ３，Ｐ１とＰ３，Ｐ１～Ｐ４はダイパッド１２ａから外側に突出した矩形の突起状としていたが、規定の形状はこの形状に限らない。図３（ｄ）に示しているのはその別の一例で、特徴形状部Ｐ１，Ｐ３を鉤状の形状としている。配線基板１２の導体は、通常エッチングによりパターニングされるが、その製法上、設計したパターン通りの形状を確保できない場合がある。そうした場合、矩形の突起状のパターンに替えてより複雑な形状の特徴パターンとすることで、特徴形状のユニーク性を確保することができる。 In the above description, the characteristic shape portions P1 to P3 and P1 and P3 and P1 to P4 of the die pad 12a are rectangular protrusions protruding outward from the die pad 12a. However, the prescribed shape is not limited to this shape. . FIG. 3D shows another example in which the characteristic shape portions P1 and P3 have a bowl shape. Although the conductor of the wiring board 12 is usually patterned by etching, there is a case where the shape according to the designed pattern cannot be secured due to its manufacturing method. In such a case, it is possible to ensure the uniqueness of the feature shape by using a feature pattern having a more complicated shape instead of the rectangular projection pattern.
　なお、上記の図１（ａ）および図３（ａ）～図３（ｄ）に述べた実施の形態１の各実施例は、それぞれ示された形状に限定されるものではなく、適宜、組み合わせることができる。 Each example of the first embodiment described in FIG. 1 (a) and FIGS. 3 (a) to 3 (d) is not limited to the illustrated shape, and is appropriately combined. be able to.
　このように、実施の形態１の半導体装置に使用した配線基板１２は、半導体チップ１１の搭載精度の向上と、半導体装置１０としての高信頼性化とを同時に実現することができ、配線基板のダイパッドパターン上に接着剤を介して半導体チップを搭載する構成を備えた半導体装置全般に有用であり、特に半導体チップの搭載ズレに対する要求の厳しいＰＤＩＣ（ photodetector integrated circuit ）等の半導体装置に有用である。 As described above, the wiring board 12 used in the semiconductor device of the first embodiment can simultaneously improve the mounting accuracy of the semiconductor chip 11 and increase the reliability as the semiconductor device 10. This is useful for all semiconductor devices having a configuration in which a semiconductor chip is mounted on a die pad pattern via an adhesive, and particularly useful for a semiconductor device such as a PDIC (photodetector integrated circuit), which has a high demand for mounting misalignment of the semiconductor chip. .
　　（実施の形態２）
　図４（ａ）は、本発明の実施の形態２にかかる半導体装置２０をその上方から見た状態を示す。なお、実施の形態１と同様の作用をなすものには同一の符号を付けて説明する。 (Embodiment 2)
FIG. 4A shows the semiconductor device 20 according to the second embodiment of the present invention as viewed from above. In addition, the same code | symbol is attached | subjected and demonstrated to the thing which performs the effect | action similar to Embodiment 1. FIG.
　実施の形態１では、半導体チップ１１を配線基板１２に高精度に搭載するための特徴形状部Ｐ１～Ｐ３，Ｐ１とＰ３，Ｐ１～Ｐ４などをダイパッド１２ａに設けたが、この実施の形態２では、ダイパッド１２ａとは分離して細長い矩形の特徴形状部Ｐ５を設けた点が異なっている。その他は実施の形態１と同じである。 In the first embodiment, the characteristic shape portions P1 to P3, P1 and P3, P1 to P4 and the like for mounting the semiconductor chip 11 on the wiring substrate 12 with high accuracy are provided on the die pad 12a. This embodiment is different from the die pad 12a in that an elongated rectangular characteristic shape portion P5 is provided. The rest is the same as in the first embodiment.
　実施の形態１に示すようにダイパッド１２ａに突起状の特徴形状部を設けると、この半導体装置１０をマザー基板に実装する際、この特徴形状部を基点にダイパッド１２ａと封止樹脂１５との界面剥離が発生することがあり得る。その界面剥離はダイパッド１２ａと接着剤１３または接着剤１３と半導体チップ１１との界面の剥離に至り、半導体チップ１１の機能に支障をきたす虞がある。 If the die pad 12a is provided with a protruding characteristic shape portion as shown in the first embodiment, when the semiconductor device 10 is mounted on the mother substrate, the interface between the die pad 12a and the sealing resin 15 is based on the characteristic shape portion. Peeling can occur. The interface peeling leads to peeling of the interface between the die pad 12a and the adhesive 13 or between the adhesive 13 and the semiconductor chip 11, and there is a possibility that the function of the semiconductor chip 11 may be hindered.
　これに対して、図４（ａ）に示すように特徴形状部Ｐ５とダイパッド１２ａとが分離していると、マザー基板への実装時に特徴形状部Ｐ５と封止樹脂１５との界面がたとえ剥離したとしても、その剥離が接着剤１３や半導体チップ１１まで至ることが無く、半導体チップ１１の機能に支障をきたす虞が小さい。なぜなら、配線基板１２において特徴形状部Ｐ５とダイパッド１２ａとの間の基材表面は、封止樹脂１５との界面の接着力がそれらのめっき部との接着力よりも大きいため、たとえ特徴形状部Ｐ５で界面剥離が発生してもそれがダイパッド１２ａにまで達して半導体チップ１１の故障にまで至る虞が低いからである。 On the other hand, when the feature shape portion P5 and the die pad 12a are separated as shown in FIG. 4A, the interface between the feature shape portion P5 and the sealing resin 15 is peeled off when mounted on the mother substrate. Even if it does, the peeling does not reach the adhesive 13 or the semiconductor chip 11, and there is little possibility that the function of the semiconductor chip 11 will be hindered. This is because the surface of the base material between the characteristic shape portion P5 and the die pad 12a in the wiring board 12 has a larger adhesive force at the interface with the sealing resin 15 than the adhesion force with the plated portion. This is because even if interfacial peeling occurs at P5, it is less likely to reach the die pad 12a and cause a failure of the semiconductor chip 11.
　従って、実施の形態２の半導体装置２０は実施の形態１に示した半導体装置１０よりも信頼性を高めることができる。 Therefore, the semiconductor device 20 of the second embodiment can be more reliable than the semiconductor device 10 shown in the first embodiment.
　次に、接着剤１３が図４（ｂ）に示すようにダイパッド１２ａの面積全面に濡れ広がっていても、特徴形状部Ｐ５を認識することにより半導体チップ１１を正確な位置に搭載することができることを説明する。 Next, even if the adhesive 13 spreads over the entire area of the die pad 12a as shown in FIG. 4B, the semiconductor chip 11 can be mounted at an accurate position by recognizing the characteristic shape portion P5. Will be explained.
　ここでダイパッド１２ａの短辺は、配線基板１２のＸ軸に平行である。直線状の特徴形状部Ｐ５は、その長辺が、基板本体１２ｏのボンディングパッド１２ｂが配列されていない側の辺に平行に配置されているため、この直線状の特徴形状部Ｐ５の、例えば、特徴形状部Ｐ５の中央付近Ｓ１の形状を認識することでダイパッド１２ａ部のＸ軸を検出することができ、そのＸ軸のデータから配線基板１２のＹ軸を仮想的に演算できる。 Here, the short side of the die pad 12 a is parallel to the X axis of the wiring board 12. Since the long side of the linear characteristic shape portion P5 is arranged in parallel to the side of the substrate body 12o where the bonding pads 12b are not arranged, the linear characteristic shape portion P5, for example, The X-axis of the die pad 12a can be detected by recognizing the shape near the center of the feature-shaped portion P5, and the Y-axis of the wiring board 12 can be virtually calculated from the X-axis data.
　図４（ｃ）は、接着剤１３を介してダイパッド１２ａの上に半導体チップ１１を搭載して、搭載位置ズレが発生した場合の平面模式図である。ここで、特徴形状部Ｐ５を仮想線で示す中央付近Ｓ１を認識することにより配線基板１２のＸ軸とＹ軸が検出され、これに対して半導体チップ１１の外形を認識することにより、配線基板１２に対する半導体チップ１１の搭載位置を演算することができる。従って、たとえ搭載位置ズレが発生したとしても、その後の測定作業により不良品を排除できる。 FIG. 4C is a schematic plan view when the semiconductor chip 11 is mounted on the die pad 12a via the adhesive 13 and a mounting position shift occurs. Here, the X-axis and the Y-axis of the wiring board 12 are detected by recognizing the central vicinity S1 indicated by the virtual line of the feature shape portion P5, and the wiring board is recognized by recognizing the outer shape of the semiconductor chip 11 on the basis of this. The mounting position of the semiconductor chip 11 with respect to 12 can be calculated. Therefore, even if the mounting position shift occurs, defective products can be eliminated by subsequent measurement work.
　半導体チップ１１の平面寸法が０．５ｍｍ×０．５ｍｍから２ｍｍ×２ｍｍまでの間とし、それを搭載するダイパッド１２ａのサイズは、それに対応する半導体チップ１１の各辺の寸法に対して０μｍから２００μｍまでの範囲で半導体チップ１１の寸法より大きい。接着剤１３の半導体チップ１１からのはみ出し寸法についても実施の形態１と同様に１６μｍから１３３μｍとなる。従って、特徴形状部Ｐ５の配置としては、その半導体チップ１１の外周部から１３３μｍ以上離れた位置に配置されていれば、接着剤１３のはみ出しに影響されることが無く、好ましい。搭載した半導体チップ１１とはみ出した接着剤１３の平面模式図とその要部拡大図を図５に示す。 The planar dimension of the semiconductor chip 11 is between 0.5 mm × 0.5 mm and 2 mm × 2 mm, and the size of the die pad 12a on which the semiconductor chip 11 is mounted is 0 μm to 200 μm with respect to the dimension of each side of the semiconductor chip 11 corresponding thereto. It is larger than the size of the semiconductor chip 11 in the range up to. The protruding dimension of the adhesive 13 from the semiconductor chip 11 is also 16 μm to 133 μm as in the first embodiment. Therefore, it is preferable that the characteristic shape portion P5 is disposed at a position separated by 133 μm or more from the outer peripheral portion of the semiconductor chip 11 without being affected by the protrusion of the adhesive 13. FIG. 5 shows a schematic plan view of the adhesive 13 protruding from the mounted semiconductor chip 11 and an enlarged view of the main part thereof.
　本実施の形態２の応用例を図６（ａ）～図６（ｄ）に示す。 Application examples of the second embodiment are shown in FIGS. 6 (a) to 6 (d).
　図６（ａ）に示した実施例の特徴形状部Ｐ６は、半導体チップ１１のボンディングパッド１１ａが配置されていない二辺に平行なダイパッド１２ａの辺、すなわちボンディングパッド１２ｂに対向していないダイパッド１２ａの短辺に直角に、細長い矩形の形状の一つである直線状の特徴形状部Ｐ６が基板本体１２ｏに設けられている。この特徴形状部Ｐ６の中央付近Ｓ２を認識することで配線基板１２のＹ軸を検出し、そのＹ軸を基準にＸ軸を検出して半導体チップ１１の搭載精度を向上させ、また搭載位置ずれが発生した不良品を排除できる。 The feature shape portion P6 of the embodiment shown in FIG. 6A is a die pad 12a that is parallel to two sides of the semiconductor chip 11 where the bonding pad 11a is not disposed, that is, the die pad 12a that is not opposed to the bonding pad 12b. The substrate main body 12o is provided with a linear characteristic shape portion P6, which is one of elongated rectangular shapes, at right angles to the short side. The Y-axis of the wiring board 12 is detected by recognizing the vicinity of the center S2 of the characteristic shape portion P6, and the X-axis is detected with reference to the Y-axis to improve the mounting accuracy of the semiconductor chip 11, and the mounting position shift It is possible to eliminate defective products that have occurred.
　図６（ｂ）に示した実施例の特徴形状部Ｐ７は、特徴形状部Ｐ６の直線状に変わる他の形状を示している。この特徴形状部Ｐ７の中央付近Ｓ３を認識することで配線基板１２のＹ軸を検出し、そのＹ軸を基準にＸ軸を検出して半導体チップ１１の搭載精度を向上させ、また搭載位置不良品を排除できる。この例は、Ｔ字状の例を示している。この他に、Ｘ軸とＹ軸との平行な直線を組み合わせた形状、例えば十字状、Ｌ字状の形状などが使用できる。 The characteristic shape portion P7 of the embodiment shown in FIG. 6B shows another shape that changes to the linear shape of the characteristic shape portion P6. The Y-axis of the wiring board 12 is detected by recognizing the vicinity of the center S3 of the characteristic shape portion P7, and the X-axis is detected with reference to the Y-axis to improve the mounting accuracy of the semiconductor chip 11, and the mounting position is not detected. Good products can be eliminated. This example shows a T-shaped example. In addition, a shape in which parallel straight lines of the X axis and the Y axis are combined, for example, a cross shape, an L shape, or the like can be used.
　図６（ｃ）に示した実施例の特徴形状部Ｐ８は、図３（ｃ）と同様に、ダイパッド１２ａ，ボンディングパッド１２ｂならびにランド１２ｃなどにめっきする場合に使用される場合で、図４（ａ）に示した特徴形状部Ｐ５の両端に引き出し線１２ｆを追加して形成されている。ダイパッド１２ａ，ボンディングパッド１２ｂならびにランド１２ｃについても引き出し線１２ｆが設けられている。 The characteristic shape portion P8 of the embodiment shown in FIG. 6C is used when plating the die pad 12a, the bonding pad 12b, the land 12c, etc., as in FIG. The lead wire 12f is added to both ends of the characteristic shape portion P5 shown in a). Lead wires 12f are also provided for the die pad 12a, the bonding pad 12b, and the land 12c.
　この図６（ｃ）に示したように、特徴形状部Ｐ５に引き出し線１２ｆを所定角度の例えば直角に、つまり、ダイパッド１２ａのＹ軸に平行に配置すれば、この引き出し線１２ｆを認識することで、ダイパッド１２ａのＹ軸を検出でき、半導体チップ１１の搭載精度の向上に有利である。 As shown in FIG. 6C, if the lead line 12f is arranged at a predetermined angle, for example, at a right angle, that is, parallel to the Y axis of the die pad 12a, the lead line 12f is recognized. Thus, the Y-axis of the die pad 12a can be detected, which is advantageous for improving the mounting accuracy of the semiconductor chip 11.
　なお、特徴形状部Ｐ５およびそれと導通する引き出し線１２ｆの形状としては、ここで示したコの字を９０度回転させた形状のほか、Ｔ字状，Ｌ字状，逆Ｌ字状，カタカナの「ト」字状などのようにダイパッド１２ａのＸ軸，Ｙ軸方向に沿った直線パターンを組み合わせた各種の形状を適用できる。 Note that the shape of the characteristic shape portion P5 and the lead wire 12f connected to the characteristic shape portion P5 is not only the shape of the U-shape shown here rotated 90 degrees, but also the shape of T-shape, L-shape, inverted L-shape, katakana Various shapes combining linear patterns along the X-axis and Y-axis directions of the die pad 12a, such as a “G” shape, can be applied.
　図６（ｄ）に示した実施例の特徴形状部Ｐ８，Ｐ９は、図６（ｃ）での実施例で見られたダイパッド１２ａが無く、特徴形状部Ｐ８に加えて特徴形状部Ｐ８と同様の特徴形状部Ｐ９を、半導体チップ１１を挟んで対称の位置に配置した応用例である。 The feature shape portions P8 and P9 of the embodiment shown in FIG. 6 (d) do not have the die pad 12a seen in the embodiment of FIG. 6 (c), and are similar to the feature shape portion P8 in addition to the feature shape portion P8. This is an application example in which the characteristic shape portion P9 is arranged at a symmetrical position with the semiconductor chip 11 in between.
　この実施例を適用できるのは、半導体チップ１１で実現しようとしている機能がダイパッド１２ａを必要としない場合に限られる。ここでダイパッド１２ａを排除し、基板本体１２ｏに半導体チップ１１を直接に接着剤１３にて接合することで、基材に対する接着剤１３の接着力はダイパッド１２ａに対するそれよりも一般的に高いため、半導体装置１０を高信頼性化することができる。更に、半導体チップ１１を挟んで特徴形状部Ｐ８，Ｐ９の２箇所に、配線基板１２の外形に対して規定の角度方向に延びる特徴形状部を配置しているため、搭載精度の向上に寄与する。 This embodiment can be applied only when the function to be realized by the semiconductor chip 11 does not require the die pad 12a. Here, by eliminating the die pad 12a and bonding the semiconductor chip 11 directly to the substrate body 12o with the adhesive 13, the adhesive force of the adhesive 13 to the base material is generally higher than that to the die pad 12a. The reliability of the semiconductor device 10 can be improved. Furthermore, since the characteristic shape portions extending in the prescribed angular direction with respect to the outer shape of the wiring board 12 are arranged at two positions of the characteristic shape portions P8 and P9 across the semiconductor chip 11, it contributes to improvement of mounting accuracy. .
　なお、図６（ｃ）で特徴形状部Ｐ８および引き出し線１２ｆの形状について述べた説明は、全てこの図６（ｄ）にも適用できる。また、図６（ｄ）は導体パターン表面のめっきが電解めっきの場合を示しているが、これが無電解めっきであってもその効果は同等に得ることができる。 It should be noted that all of the descriptions about the shapes of the characteristic shape portion P8 and the lead line 12f in FIG. 6C can also be applied to FIG. 6D. Further, FIG. 6D shows a case in which the plating on the surface of the conductor pattern is electrolytic plating, but even if this is electroless plating, the same effect can be obtained.
　以上の説明において、特徴形状部の配置は、四辺形の形状の半導体装置１０の中で、半導体チップ１１のボンディングパッド１１ａが配置されていない辺に対向した領域に限定した。その理由は、半導体チップ１１のボンディングパッド１１ａが配置されている辺に対向した領域、すなわち、ボンディングパッド１２ｂやランド１２ｃが配置された側に特徴形状部を配置すると、この特徴形状部と封止樹脂１５との間で界面剥離が発生した場合、それが進展してボンディングパッド１２ｂに至り、電気的な接続が損なわれる虞があるからである。 In the above description, the arrangement of the characteristic shape portions is limited to a region facing the side where the bonding pad 11a of the semiconductor chip 11 is not arranged in the quadrilateral semiconductor device 10. The reason is that if the characteristic shape portion is arranged in a region facing the side where the bonding pad 11a of the semiconductor chip 11 is arranged, that is, the side where the bonding pad 12b or the land 12c is arranged, the characteristic shape portion and the sealing portion are sealed. This is because when the interface peeling occurs with the resin 15, it progresses to the bonding pad 12 b and the electrical connection may be impaired.
　なお、半導体装置１０に使用できる材料については実施の形態１に述べた内容と重複するのでここでの説明は割愛する。 Note that materials that can be used for the semiconductor device 10 are the same as those described in the first embodiment, and thus description thereof will be omitted.
　　（実施の形態３）
　図７（ａ）（ｂ）は、それぞれ本発明の実施の形態３にかかる半導体装置を示す。実施の形態２との違いは、配線基板１２の表面を、ダイパッド１２ａ，ボンディングパッド１２ｂ，特徴形状部を除いて、ソルダーレジスト３０ａ，３０ｂ，３０ｃにて被覆している点である。 (Embodiment 3)
FIGS. 7A and 7B show a semiconductor device according to the third embodiment of the present invention. The difference from the second embodiment is that the surface of the wiring substrate 12 is covered with solder resists 30a, 30b, and 30c except for the die pad 12a, the bonding pad 12b, and the characteristic shape portion.
　前述したように、めっき部は封止樹脂１５との接着力が低いため、必要の無い箇所は封止樹脂１５との界面の面積を極力小さくする方が好ましい。またソルダーレジスト３０ａ，３０ｂ，３０ｃはめっき部よりも封止樹脂１５との界面での接着力が高い。従って、外部に露出することが必要な部分、すなわち、接着剤１３を塗布して半導体チップ１１を搭載するダイパッド１２ａ，ワイヤ１４と接続するボンディングパッド１２ｂ，特徴形状部Ｐ５，Ｐ８，Ｐ９を除いた部分を、ソルダーレジスト３０ａ，３０ｂ，３０ｃで被覆することで、半導体装置１０の信頼性を高めることができる。 As described above, since the plating part has a low adhesive force with the sealing resin 15, it is preferable to reduce the area of the interface with the sealing resin 15 as much as possible in an unnecessary part. Further, the solder resists 30a, 30b, and 30c have higher adhesive strength at the interface with the sealing resin 15 than the plated portion. Therefore, the parts that need to be exposed to the outside, that is, the die pad 12a on which the semiconductor chip 11 is mounted by applying the adhesive 13, the bonding pad 12b connected to the wire 14, and the characteristic shape parts P5, P8, and P9 are excluded. The reliability of the semiconductor device 10 can be improved by covering the portions with the solder resists 30a, 30b, and 30c.
　図７（ａ）は、図４（ａ）に示した半導体装置に上記の改変を施した実施の形態３の基づく半導体装置４０を示している。 FIG. 7A shows a semiconductor device 40 according to the third embodiment in which the above-described modification is applied to the semiconductor device shown in FIG.
　配線基板１２の表面をソルダーレジスト３０ａ，３０ｂ，３０ｃにて被覆し、ソルダーレジスト３０ａの中央でダイパッド１２ａを露出させ、ソルダーレジスト３０ａとソルダーレジスト３０ｂの間でボンディングパッド１２ｂを露出させ、ソルダーレジスト３０ａとソルダーレジスト３０ｃの間でもボンディングパッド１２ｂを露出させている。ソルダーレジスト３０ａ，３０ｂ，３０ｃは互いに分離されている必要はなく、連なっていてもよい。ここでの特徴形状部Ｐ５を認識することで、半導体チップ１１をダイパッド１２ａに高精度で搭載でき、また搭載後の位置の測定ができる。 The surface of the wiring board 12 is covered with solder resists 30a, 30b, and 30c, the die pad 12a is exposed at the center of the solder resist 30a, and the bonding pads 12b are exposed between the solder resist 30a and the solder resist 30b. The bonding pad 12b is also exposed between the solder resist 30c. The solder resists 30a, 30b, and 30c do not need to be separated from each other, and may be connected. By recognizing the feature shape portion P5 here, the semiconductor chip 11 can be mounted on the die pad 12a with high accuracy, and the position after mounting can be measured.
　図７（ｂ）は、同様に図６（ｄ）に示した半導体装置１０に上記の改変を施した実施の形態３の基づく半導体装置５０を示している。図６（ｄ）に示した半導体装置１０の場合にはダイパッド１２ａを有していないため、その部分でのソルダーレジスト３０ａの開口は無く、ソルダーレジスト３０ａの表面上に半導体チップ１１が接着剤１３を介して直接に搭載されている。界面剥離の起点となるダイパッド１２ａが無く、かつ特徴形状部Ｐ８，Ｐ９は、特徴形状部Ｐ５とその両端の引き出し線１２ｆがソルダーレジスト３０ａの開口から露出しているため、高信頼性かつ半導体チップ１１の搭載位置の精度に優れた半導体装置５０を実現できる。 FIG. 7B shows a semiconductor device 50 according to the third embodiment in which the semiconductor device 10 shown in FIG. 6D is similarly modified as described above. Since the semiconductor device 10 shown in FIG. 6D does not have the die pad 12a, there is no opening of the solder resist 30a at that portion, and the semiconductor chip 11 is bonded to the adhesive 13 on the surface of the solder resist 30a. It is mounted directly through. Since there is no die pad 12a as a starting point of interface peeling, and the characteristic shape portions P8 and P9, the characteristic shape portion P5 and the lead lines 12f at both ends thereof are exposed from the openings of the solder resist 30a. Thus, it is possible to realize the semiconductor device 50 having excellent mounting position accuracy.
　なお、この図７（ｂ）で示す実施例においてダイパッド１２ａが設けられていない別の理由、例えば半導体チップ１１を搭載するソルダーレジスト３０ａの表面の平坦性を確保する等によってダイパッド１２ａを設けてその上をソルダーレジスト３０ａで被覆してもよい。 It should be noted that in the embodiment shown in FIG. 7B, the die pad 12a is provided for another reason, for example, by ensuring the flatness of the surface of the solder resist 30a on which the semiconductor chip 11 is mounted. The top may be covered with a solder resist 30a.
　また、ここでの特徴形状部Ｐ５に代わり、実施の形態１にて説明した特徴形状部Ｐ１～Ｐ３，Ｐ１とＰ３，Ｐ１～Ｐ４などを有するダイパッド形状を本実施の形態３に適用できる。 Further, instead of the feature shape portion P5 here, a die pad shape having the feature shape portions P1 to P3, P1 and P3, P1 to P4, etc. described in the first embodiment can be applied to the third embodiment.
　また、ここでの特徴形状部Ｐ５に代わり、実施の形態２にて説明した十字状、Ｔ字状、Ｌ字状、逆Ｌ字状などの、配線基板１２のＸ軸，Ｙ軸に平行な直線部分を組み合わせた特徴形状部などをこの実施の形態３に適用することもできる。 Further, instead of the characteristic shape portion P5 here, the cross-shaped, T-shaped, L-shaped, inverted L-shaped or the like described in the second embodiment is parallel to the X axis and Y axis of the wiring board 12. A feature shape portion or the like obtained by combining straight portions can also be applied to the third embodiment.
　なお、上記の実施の形態１～３および各々の実施例に記載の構成はあくまで本発明の一例として記載したものであり、発明の内容を記載された実施形態の構成のみに限定するものではない。また、上記の実施の形態１～３は本発明の主旨を逸脱しない範囲で適宜組み合わせて実施できる。 The configurations described in the first to third embodiments and the respective examples are merely described as an example of the present invention, and the contents of the invention are not limited to the configurations of the described embodiments. . Further, Embodiments 1 to 3 described above can be implemented in combination as appropriate without departing from the gist of the present invention.
　例えば、特徴形状部Ｐ５をダイパッド１２ａと分離させる構成において、ダイパッド１２ａは、半導体チップ１１よりも小さくても良い。 For example, in the configuration in which the characteristic shape portion P5 is separated from the die pad 12a, the die pad 12a may be smaller than the semiconductor chip 11.
　本発明は、配線基板上に接着剤を介して半導体チップを搭載する構成を備えた半導体装置全般に有用であり、特に半導体チップの搭載ズレに対する要求の厳しいＰＤＩＣ等の半導体装置としての高信頼性化に寄与する。 INDUSTRIAL APPLICABILITY The present invention is useful for all semiconductor devices having a configuration in which a semiconductor chip is mounted on a wiring board via an adhesive, and in particular, has high reliability as a semiconductor device such as a PDIC that has a severe demand for mounting displacement of the semiconductor chip. Contributes to

Claims (12)

  1. 　基板本体と、
    　前記基板本体上に配列されたボンディングパッドと、
    　前記基板本体上に配置された矩形状のダイパッドとを備え、
    　前記ダイパッドは、少なくとも２箇所のコーナーにおいて前記ボンディングパッドが配列されていない方向に向かって対向する二辺を突出させて形成した特徴形状部を備えることを特徴とする配線基板。     A substrate body;
    Bonding pads arranged on the substrate body;
    A rectangular die pad disposed on the substrate body,
    2. The wiring board according to claim 1, wherein the die pad includes a characteristic shape portion formed by projecting two sides facing each other in a direction in which the bonding pads are not arranged at at least two corners.
  2. 　前記ダイパッドの特徴形状部の表面は導体層であることを特徴とする請求項１記載の配線基板。 2. The wiring board according to claim 1, wherein the surface of the characteristic shape portion of the die pad is a conductor layer.
  3. 　前記ダイパッドの特徴形状部は、３箇所のコーナーにおいて設けられたことを特徴とする請求項１または請求項２に記載の配線基板。 The wiring board according to claim 1 or 2, wherein the characteristic shape portions of the die pad are provided at three corners.
  4. 　前記ダイパッドの特徴形状部は、４箇所のコーナーにおいて設けられたことを特徴とする請求項１または請求項２に記載の配線基板。 The wiring board according to claim 1 or 2, wherein the characteristic shape portions of the die pad are provided at four corners.
  5. 　前記ダイパッドの特徴形状部は、鉤状の形状であることを特徴とする請求項１～請求項４のいずれかに記載の配線基板。 5. The wiring board according to claim 1, wherein the characteristic shape portion of the die pad has a bowl shape.
  6. 　基板本体と、
    　前記基板本体上に配列されたボンディングパッドと、
    　前記基板本体上に配置された矩形状のダイパッドと、
    　前記ボンディングパッドが配列されていない方向に前記ダイパッドとは分離して前記基板本体上に形成された導体層の特徴形状部を備えることを特徴とする配線基板。     A substrate body;
    Bonding pads arranged on the substrate body;
    A rectangular die pad disposed on the substrate body;
    A wiring board comprising a characteristic shape part of a conductor layer formed on the substrate body separately from the die pad in a direction in which the bonding pads are not arranged.
  7. 　前記特徴形状部は、細長い矩形の形状であり、その長辺が、前記基板本体の前記ボンディングパッドが配列されていない側の辺に平行に配置されていることを特徴とする
    請求項６記載の配線基板。     The said characteristic shape part is an elongate rectangular shape, The long side is arrange | positioned in parallel with the edge | side by which the said bonding pad of the said board | substrate body is not arranged. Wiring board.
  8. 　前記特徴形状部は、その長辺が前記基板本体の前記ボンディングパッドが配列されている側の辺に平行に配置されている細長い矩形の形状を有することを特徴とする
    請求項６記載の配線基板。     7. The wiring board according to claim 6, wherein the characteristic shape portion has an elongated rectangular shape whose long side is arranged in parallel to the side of the substrate body on which the bonding pads are arranged. .
  9. 　前記基板本体の前記ダイパッド、前記特徴形状部、前記ボンディングパッドを除いた表面が、絶縁体によって覆われていることを特徴とする
    請求項６～請求項８のいずれかに記載の配線基板。     9. The wiring board according to claim 6, wherein a surface of the substrate body excluding the die pad, the characteristic shape portion, and the bonding pad is covered with an insulator.
  10. 　請求項１～請求項９のいずれかに記載の配線基板と、
    　前記配線基板のダイパッド上に接着剤を介して固着された矩形状の半導体チップと、
    　前記半導体チップの対向する二辺に沿って配列されたボンディングパッドと前記配線基板のボンディングパッドを電気的に接続するワイヤと、
    　前記配線基板の表面を、前記半導体チップ、前記ワイヤとともに封止する封止樹脂と
    を備え、前記ダイパッドの外周枠は前記半導体チップの外周枠の外側に近接して存在することを特徴とする
    半導体装置。     A wiring board according to any one of claims 1 to 9,
    A rectangular semiconductor chip fixed on the die pad of the wiring board via an adhesive;
    Bonding pads arranged along two opposite sides of the semiconductor chip and wires for electrically connecting the bonding pads of the wiring board;
    And a sealing resin that seals the surface of the wiring board together with the semiconductor chip and the wire, and the outer peripheral frame of the die pad is located close to the outer side of the outer peripheral frame of the semiconductor chip. apparatus.
  11. 　配線基板の中央に接着剤を介して矩形状の半導体チップが固着され、前記半導体チップの対向する二辺に沿って配列された第１のボンディングパッドとこの第１のボンディングパッドに沿って前記配線基板の側に配列された第２のボンディングパッドの間をワイヤで電気的に接続し、前記配線基板の表面を、前記半導体チップ、前記ワイヤとともに封止樹脂によって封止した半導体装置であって、
    　前記配線基板は、前記半導体チップの第１のボンディングパッドが配列された辺に隣接した辺に近接して、前記半導体チップを挟む２箇所に、配線基板の外形に対して規定の角度方向に延びる特徴形状部を備えていることを特徴とする
    半導体装置。     A rectangular semiconductor chip is fixed to the center of the wiring board via an adhesive, and a first bonding pad arranged along two opposite sides of the semiconductor chip and the wiring along the first bonding pad. A semiconductor device in which the second bonding pads arranged on the substrate side are electrically connected with a wire, and the surface of the wiring substrate is sealed with a sealing resin together with the semiconductor chip and the wire,
    The wiring board extends in a prescribed angular direction with respect to the outer shape of the wiring board at two locations sandwiching the semiconductor chip, close to the side adjacent to the side where the first bonding pads of the semiconductor chip are arranged. A semiconductor device comprising a characteristic shape portion.
  12. 　請求項１～請求項９のいずれかに記載の配線基板と、
    　前記配線基板のダイパッド上に接着剤を介して固着された矩形状の半導体チップと、
    　前記半導体チップの対向する二辺に沿って配列されたボンディングパッドと前記配線基板のボンディングパッドを電気的に接続するワイヤと、
    　前記配線基板の表面を、前記半導体チップ、前記ワイヤとともに封止する封止樹脂と
    を備え、前記ダイパッドの外周枠は前記半導体チップの外周枠の内側に近接して存在する
    ことを特徴とする半導体装置。     A wiring board according to any one of claims 1 to 9,
    A rectangular semiconductor chip fixed on the die pad of the wiring board via an adhesive;
    Bonding pads arranged along two opposite sides of the semiconductor chip and wires for electrically connecting the bonding pads of the wiring board;
    A semiconductor comprising: a sealing resin that seals the surface of the wiring board together with the semiconductor chip and the wire; and an outer peripheral frame of the die pad is located close to an inner side of the outer peripheral frame of the semiconductor chip. apparatus.
PCT/JP2011/004314 2011-01-19 2011-07-29 Wiring substrate and semiconductor device using same WO2012098595A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2011008338A JP2014063767A (en) 2011-01-19 2011-01-19 Wiring board and semiconductor device using the same
JP2011-008338 2011-01-19

Publications (1)

Publication Number Publication Date
WO2012098595A1 true WO2012098595A1 (en) 2012-07-26

Family

ID=46515250

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2011/004314 WO2012098595A1 (en) 2011-01-19 2011-07-29 Wiring substrate and semiconductor device using same

Country Status (2)

Country Link
JP (1) JP2014063767A (en)
WO (1) WO2012098595A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021260890A1 (en) * 2020-06-25 2021-12-30 三菱電機株式会社 Optical module

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05136293A (en) * 1991-11-12 1993-06-01 Sony Corp Optical semiconductor device
JPH07321146A (en) * 1994-05-25 1995-12-08 Fuji Xerox Co Ltd Arranging method of wire bonding recognition mark
JP2002314059A (en) * 2001-04-18 2002-10-25 Sony Corp Photo detector package and manufacturing method of photo receptor
JP2005072463A (en) * 2003-08-27 2005-03-17 Mitsumi Electric Co Ltd Semiconductor device
JP2007234900A (en) * 2006-03-01 2007-09-13 Sanyo Electric Co Ltd Semiconductor device and manufacturing method thereof
JP2010147200A (en) * 2008-12-18 2010-07-01 Panasonic Corp Solid-state imaging apparatus and method of manufacturing same

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05136293A (en) * 1991-11-12 1993-06-01 Sony Corp Optical semiconductor device
JPH07321146A (en) * 1994-05-25 1995-12-08 Fuji Xerox Co Ltd Arranging method of wire bonding recognition mark
JP2002314059A (en) * 2001-04-18 2002-10-25 Sony Corp Photo detector package and manufacturing method of photo receptor
JP2005072463A (en) * 2003-08-27 2005-03-17 Mitsumi Electric Co Ltd Semiconductor device
JP2007234900A (en) * 2006-03-01 2007-09-13 Sanyo Electric Co Ltd Semiconductor device and manufacturing method thereof
JP2010147200A (en) * 2008-12-18 2010-07-01 Panasonic Corp Solid-state imaging apparatus and method of manufacturing same

Also Published As

Publication number Publication date
JP2014063767A (en) 2014-04-10

Similar Documents

Publication Publication Date Title
US9899299B2 (en) Semiconductor device
JP4068635B2 (en) Wiring board
JP2006074736A (en) Piezoelectric oscillator and method of manufacturing the same
JP2020136507A (en) Semiconductor device and manufacturing method of the same
WO2012098595A1 (en) Wiring substrate and semiconductor device using same
JP4435074B2 (en) Semiconductor device and manufacturing method thereof
JP2017199897A (en) Semiconductor device
JPH0558657B2 (en)
US20200411425A1 (en) Semiconductor device
JP2006278756A (en) Package for piezoelectric vibrator storage and piezoelectric device
CN107331767B (en) Semiconductor device with a plurality of transistors
JP2019102651A (en) Semiconductor device and semiconductor device manufacturing method
JP2006186282A (en) Semiconductor device and its manufacturing method
JP2004363319A (en) Mount substrate and semiconductor device
JP4400881B2 (en) Hall element package and composite mounting module
JP5742623B2 (en) Semiconductor device
JP4712426B2 (en) Semiconductor device
JP6842236B2 (en) Magnetic sensor module
JP2008010922A (en) Piezoelectric oscillator
JP2017224706A (en) Semiconductor device
JP2024058208A (en) Semiconductor device, sensor, and method for manufacturing the semiconductor device
JP2014027126A (en) Semiconductor device
JP2015032705A (en) Mold package
JP4409528B2 (en) Semiconductor device
JP2009194132A (en) Semiconductor chip, photoelectric conversion chip, and manufacturing method of semiconductor chip

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 11856288

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 11856288

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP