JPH05114609A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH05114609A
JPH05114609A JP3272881A JP27288191A JPH05114609A JP H05114609 A JPH05114609 A JP H05114609A JP 3272881 A JP3272881 A JP 3272881A JP 27288191 A JP27288191 A JP 27288191A JP H05114609 A JPH05114609 A JP H05114609A
Authority
JP
Japan
Prior art keywords
polysilicon layer
region
source
layer
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3272881A
Other languages
Japanese (ja)
Inventor
Sonte An
アン・ソンテ
Shigeki Hayashida
茂樹 林田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP3272881A priority Critical patent/JPH05114609A/en
Publication of JPH05114609A publication Critical patent/JPH05114609A/en
Pending legal-status Critical Current

Links

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PURPOSE:To manufacture a semiconductor device having high reliability by incorporating the step of laminating a polysilicon layer on a semiconductor substrate and then ion implanting a source/drain region through the layer and the step of oxidizing the layer in an oxidative atmosphere. CONSTITUTION:An active region and an element isolating region 2 made of a field oxide film are formed on a silicon substrate 1. After a gate electrode 3 is formed on the region 2 through a gate oxide film 9 made of SiO2, As is implanted to form a source/drain region 5 in which a low concentration impurity is diffused. Further, a sidewall 4 made of SiO2 is formed on the electrode 3. Then, a polysilicon layer 6 is formed on the substrate 1. Thereafter, with the electrode 3 as a mask As is implanted through the layer 6 to form a high concentration impurity diffused region 5b on the low concentration impurity diffused region 5a. Thereafter, it is heat treated in an oxidative atmosphere.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置の製造方法に
関し、より詳細にはMOS型半導体装置の製造方法に関
する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a MOS type semiconductor device.

【0002】[0002]

【従来の技術】従来のMOS型トランジスタを製造する
場合、まず、活性領域及びフィールド酸化膜からなる素
子分離領域が形成され、さらに活性領域にゲート酸化膜
を介してゲート電極が形成された半導体基板に、n-
オンを注入してソース/ドレイン領域を形成する。次い
でゲート電極にSiO2からなるサイドウォールを形成
した後、n+ イオンを再度ソース/ドレイン領域に注入
することにより、LDD構造を有するソース/ドレイン
領域を形成している。
2. Description of the Related Art When manufacturing a conventional MOS transistor, a semiconductor substrate is first formed with an element isolation region including an active region and a field oxide film, and further with a gate electrode formed in the active region via a gate oxide film. Then, n ions are implanted to form source / drain regions. Next, after forming a sidewall made of SiO 2 on the gate electrode, n + ions are implanted again into the source / drain regions to form the source / drain regions having the LDD structure.

【0003】[0003]

【発明が解決しようとする課題】MOS型トランジスタ
等のデバイスの動作の高速化及び微細化等につれて、接
合深さの浅いソース/ドレインの形成が不可欠である
が、上記した半導体装置の製造方法においては、半導体
基板にイオン注入による損傷が生じたり、熱処理により
半導体基板への不純物拡散が促進されるという問題点が
ある。従って、接合部のリーク電流が生じ、良好な接合
特性を有する浅いp/n接合を形成するのは困難である
という課題があった。
With the speeding up and miniaturization of devices such as MOS transistors, it is essential to form a source / drain with a shallow junction depth. In the method of manufacturing a semiconductor device described above, However, there are problems that the semiconductor substrate is damaged by ion implantation, and that the heat treatment promotes the diffusion of impurities into the semiconductor substrate. Therefore, there is a problem that a leak current occurs at the junction and it is difficult to form a shallow p / n junction having good junction characteristics.

【0004】本発明はこのような課題を鑑みなされたも
のであり、良好な接合特性を有する、浅いp/n接合を
形成することができる半導体装置の製造方法を提供する
ことを目的としている。
The present invention has been made in view of the above problems, and an object of the present invention is to provide a method of manufacturing a semiconductor device having excellent junction characteristics and capable of forming a shallow p / n junction.

【0005】[0005]

【課題を解決するための手段】上記記載の課題を解決す
るために本発明によれば、サイドウォールが形成された
ゲート電極が配設され、ソース/ドレイン領域が形成さ
れた半導体基板上にポリシリコン層を積層させた後、該
ポリシリコン層を通してソース/ドレイン領域にイオン
注入を行う工程、ポリシリコン層を酸化性雰囲気下で酸
化する工程を含むことを特徴としている。
According to the present invention, in order to solve the above-mentioned problems, according to the present invention, a polysilicon film is formed on a semiconductor substrate on which a gate electrode having a sidewall is arranged and a source / drain region is formed. The method is characterized by including a step of implanting ions into the source / drain regions through the polysilicon layer after stacking the silicon layer, and a step of oxidizing the polysilicon layer in an oxidizing atmosphere.

【0006】本発明において、ポリシリコン層は20〜
60nmの厚さで形成するのが好ましい。また、本発明
で用いるソース/ドレイン領域が形成された半導体基板
は、ソース/ドレイン領域がP型不純物拡散領域の場合
にはB等、N型不純物拡散領域の場合にはAs、P等が
40〜80KeV、1〜3×1012cm-2程度の濃度で
注入されているものが好ましく、ポリシリコン層を通し
てソース/ドレイン領域にイオン注入を行う工程におい
て、ソース/ドレイン領域をP型不純物拡散領域に形成
する場合にはB等、N型不純物拡散領域に形成する場合
にはAs、P等を40〜80KeV、1〜3×1015
-2程度の濃度で注入するのが好ましい。
In the present invention, the polysilicon layer is 20 to
It is preferably formed with a thickness of 60 nm. Further, in the semiconductor substrate in which the source / drain regions used in the present invention are formed, B or the like is 40 when the source / drain regions are P-type impurity diffusion regions, and As, P or the like is 40 when the source / drain regions are N-type impurity diffusion regions. ~80KeV, 1~3 × 10 12 cm -2 order is preferably one that is implanted at a concentration of, in the step of performing ion implantation into the source / drain regions through the polysilicon layer, the source / drain regions of the P-type impurity diffusion regions In the case of forming in the N type impurity diffusion region, As and P in the case of forming in the N type impurity diffusion region 40 to 80 KeV, 1 to 3 × 10 15 c
It is preferable to inject at a concentration of about m −2 .

【0007】本発明におけるゲート酸化膜、サイドウォ
ール等、さらに、ゲート電極及びポリシリコン層の形成
はCVD法等の公知の方法によって行うことができる。
また、ポリシリコン層を酸化性雰囲気下で酸化する工程
はイオン注入を行った後の熱処理を同時に行うことがで
きる。この場合、900〜1000℃の温度範囲で30
分〜1時間程度行うのが好ましい。さらに、この工程を
行った後のポリシリコン層は全て酸化され、後工程で酸
化膜として取り扱うことができる。
The gate oxide film, the side wall, etc., and the gate electrode and the polysilicon layer in the present invention can be formed by a known method such as a CVD method.
In the step of oxidizing the polysilicon layer in an oxidizing atmosphere, heat treatment after ion implantation can be performed at the same time. In this case, 30 in the temperature range of 900 to 1000 ° C.
It is preferable to carry out for about 1 minute to 1 hour. Furthermore, the polysilicon layer after this step is entirely oxidized and can be handled as an oxide film in a later step.

【0008】[0008]

【作用】上記した半導体装置の製造方法によれば、サイ
ドウォールが形成されたゲート電極が配設され、ソース
/ドレイン領域が形成された半導体基板上にポリシリコ
ン層を積層させた後、該ポリシリコン層を通して前記ソ
ース/ドレイン領域にイオン注入を行う工程、ポリシリ
コン層を酸化性雰囲気下で酸化する工程を含むので、ま
ず、前記半導体基板上に積層された前記ポリシリコン層
にイオン注入が行われる。これにより、前記半導体基板
内に、イオン注入によって生じる損傷が回避されるとと
もに、前記ポリシリコン層からの固相拡散によって所望
の不純物を拡散させた前記ソース/ドレイン領域が形成
されることとなる。
According to the method of manufacturing a semiconductor device described above, a polysilicon layer is laminated on a semiconductor substrate on which a gate electrode having a sidewall is formed and a source / drain region is formed, and then the polysilicon layer is deposited. Since the step of implanting ions into the source / drain regions through the silicon layer and the step of oxidizing the polysilicon layer in an oxidizing atmosphere are included, first, the ion implantation is performed on the polysilicon layer stacked on the semiconductor substrate. Be seen. This avoids damage caused by ion implantation and forms the source / drain regions in which desired impurities are diffused by solid phase diffusion from the polysilicon layer in the semiconductor substrate.

【0009】また、前記ポリシリコン層はすべて酸化さ
れるので、後工程で前記ポリシリコン層を除去すること
なく、酸化膜として取り扱われる。従って、前記半導体
基板内に損傷の少ない、良好な接合特性を有する浅いp
/n接合が形成されることとなる。
Further, since the polysilicon layer is entirely oxidized, it is handled as an oxide film without removing the polysilicon layer in a later step. Therefore, a shallow p-shaped semiconductor substrate with less damage and good junction characteristics is provided.
A / n junction will be formed.

【0010】[0010]

【実施例】本発明に係る半導体装置の製造方法の実施例
を図面に基づいて説明する。まず、半導体基板としてシ
リコン基板(1)に活性領域及びフィールド酸化膜から
なる素子分離領域(2)を形成する。そして、素子形成
領域にSiO2 からなるゲート酸化膜(9)を介してゲ
ート電極(3)を形成した後、例えば、Asを80Ke
V、1×1012cm-2程度の濃度で注入して低濃度不純
物が拡散したソース/ドレイン領域(5)を形成する。
さらに、ゲート電極(3)にSiO2 からなるサイドウ
ォール(4)を形成する(図1(a))。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method for manufacturing a semiconductor device according to the present invention will be described with reference to the drawings. First, an element isolation region (2) made of an active region and a field oxide film is formed on a silicon substrate (1) as a semiconductor substrate. Then, after forming the gate electrode (3) in the element formation region via the gate oxide film (9) made of SiO 2 , As is 80 Ke, for example.
The source / drain region (5) is formed by implanting V at a concentration of about 1 × 10 12 cm −2 and diffusing low concentration impurities.
Further, a sidewall (4) made of SiO 2 is formed on the gate electrode (3) (FIG. 1 (a)).

【0011】次いで、シリコン基板(1)上に約20n
mの厚さのポリシリコンを積層してポリシリコン層
(6)を形成したのち、ゲート電極(3)をマスクと
し、ポリシリコン層(6)を通してAsを80KeV、
1×1015cm-2程度の濃度で注入して、低濃度不純物
拡散領域(5a)上に高濃度不純物拡散領域(5b)を
形成することにより、ソース/ドレイン領域(5)を形
成する(図1(b))。
Then, about 20n is formed on the silicon substrate (1).
After forming a polysilicon layer (6) by stacking polysilicon having a thickness of m, As is 80 KeV through the polysilicon layer (6) using the gate electrode (3) as a mask,
The source / drain region (5) is formed by implanting at a concentration of about 1 × 10 15 cm −2 and forming the high concentration impurity diffusion region (5b) on the low concentration impurity diffusion region (5a) ( FIG. 1B).

【0012】その後、酸化性雰囲気下、900℃で30
分間熱処理を行って、ソース/ドレイン領域(5)に不
純物を拡散させるとともに、ポリシリコン層(6)を全
て酸化して、SiO2 膜(7)を形成する(図1
(c))。本実施例においてはNMOSを作製する場合
について説明しているが、PMOS、あるいはCMOS
についても同様に行うことができる。
After that, in an oxidizing atmosphere, at 900 ° C. for 30 minutes.
Heat treatment is performed for a minute to diffuse the impurities into the source / drain regions (5) and oxidize the entire polysilicon layer (6) to form a SiO 2 film (7) (FIG.
(C)). In this embodiment, the case where the NMOS is manufactured is described, but the PMOS or the CMOS is used.
Can be similarly performed.

【0013】[0013]

【発明の効果】本発明に係る半導体装置の製造方法によ
れば、サイドウォールが形成されたゲート電極が配設さ
れ、ソース/ドレイン領域が形成された半導体基板上に
ポリシリコン層を積層させた後、該ポリシリコン層を通
してソース/ドレイン領域にイオン注入を行う工程、ポ
リシリコン層を酸化性雰囲気下で酸化する工程を含むの
で、まず、前記半導体基板上に積層された前記ポリシリ
コン層にイオン注入が行われる。これにより、前記半導
体基板内に、イオン注入によって生じる損傷を回避する
ことができるとともに、ポリシリコン層からの固相拡散
によって所望の不純物を拡散させたソース/ドレイン領
域を形成することができる。
According to the method of manufacturing a semiconductor device of the present invention, a polysilicon layer is laminated on a semiconductor substrate having a gate electrode having a sidewall formed therein and having source / drain regions formed therein. After that, since a step of implanting ions into the source / drain regions through the polysilicon layer and a step of oxidizing the polysilicon layer in an oxidizing atmosphere are included, first, ions are implanted in the polysilicon layer stacked on the semiconductor substrate. The injection is done. This makes it possible to avoid damage caused by ion implantation in the semiconductor substrate, and form source / drain regions in which desired impurities are diffused by solid phase diffusion from the polysilicon layer.

【0014】従って、複雑な製造工程を経ないで、半導
体基板内に損傷の少ない、良好な接合特性を有する浅い
p/n接合を形成することができ、接合部のリーク電流
を防止して信頼性の高い半導体装置を製造することが可
能となる。
Therefore, it is possible to form a shallow p / n junction with a small amount of damage and good junction characteristics in a semiconductor substrate without complicated manufacturing steps, and prevent leakage current at the junction to be reliable. It becomes possible to manufacture a semiconductor device having high property.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係わる半導体装置の製造方法の実施例
を示す概略断面図である。
FIG. 1 is a schematic cross-sectional view showing an embodiment of a method for manufacturing a semiconductor device according to the present invention.

【符号の説明】[Explanation of symbols]

1 シリコン基板(半導体基板) 3 ゲート電極 4 サイドウォール 5 ソース/ドレイン領域 6 ポリシリコン層 9 ゲート酸化膜 1 Silicon Substrate (Semiconductor Substrate) 3 Gate Electrode 4 Sidewall 5 Source / Drain Region 6 Polysilicon Layer 9 Gate Oxide Film

フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 H01L 27/092 7342−4M H01L 27/08 321 E Continuation of front page (51) Int.Cl. 5 Identification number Office reference number FI technical display location H01L 27/092 7342-4M H01L 27/08 321 E

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 サイドウォールが形成されたゲート電極
が配設され、ソース/ドレイン領域が形成された半導体
基板上にポリシリコン層を積層させた後、該ポリシリコ
ン層を通してソース/ドレイン領域にイオン注入を行う
工程、ポリシリコン層を酸化性雰囲気下で酸化する工程
を含むことを特徴とする半導体装置の製造方法。
1. A polysilicon layer is stacked on a semiconductor substrate on which a gate electrode having a sidewall is formed and a source / drain region is formed, and then an ion is deposited on the source / drain region through the polysilicon layer. A method of manufacturing a semiconductor device, comprising: a step of implanting and a step of oxidizing a polysilicon layer in an oxidizing atmosphere.
JP3272881A 1991-10-21 1991-10-21 Manufacture of semiconductor device Pending JPH05114609A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3272881A JPH05114609A (en) 1991-10-21 1991-10-21 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3272881A JPH05114609A (en) 1991-10-21 1991-10-21 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH05114609A true JPH05114609A (en) 1993-05-07

Family

ID=17520064

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3272881A Pending JPH05114609A (en) 1991-10-21 1991-10-21 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH05114609A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103681280A (en) * 2012-09-26 2014-03-26 中芯国际集成电路制造(上海)有限公司 Semiconductor device and formation method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103681280A (en) * 2012-09-26 2014-03-26 中芯国际集成电路制造(上海)有限公司 Semiconductor device and formation method thereof
KR101466847B1 (en) * 2012-09-26 2014-12-02 세미컨덕터 매뉴팩춰링 인터내셔널 (상하이) 코포레이션 Semiconductor device and method for forming the same

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